KR0164514B1 - Forming method of interpoly insulating film - Google Patents
Forming method of interpoly insulating film Download PDFInfo
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- KR0164514B1 KR0164514B1 KR1019950061323A KR19950061323A KR0164514B1 KR 0164514 B1 KR0164514 B1 KR 0164514B1 KR 1019950061323 A KR1019950061323 A KR 1019950061323A KR 19950061323 A KR19950061323 A KR 19950061323A KR 0164514 B1 KR0164514 B1 KR 0164514B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
Abstract
본 발명은 인터폴리 절연막 형성방법에 관한 것으로서, 특히 하부 폴리실리콘층의 표면을 산화시켜서 폴리산화막을 형성하는 단계; 폴리산화막 상에 700℃ 미만의 온도조건에서 분당 7Å 미만의 성막비율로 질화막을 형성하는 단계; 질화막의 표면을 산화시켜서 질화산화막을 형성하는 단계를 구비하는 것을 특징으로 한다.The present invention relates to a method for forming an interpoly insulating film, particularly comprising: oxidizing a surface of a lower polysilicon layer to form a poly oxide film; Forming a nitride film on the poly oxide film at a film forming ratio of less than 7 Pa / min at a temperature of less than 700 ° C .; Oxidizing the surface of the nitride film to form a nitride oxide film.
따라서, 본 발명에서는 질화산화막의 형성시 전체적으로 균일한 질화산화막을 얻을 수 있다.Therefore, in the present invention, a uniform nitride oxide film as a whole can be obtained when the nitride oxide film is formed.
Description
제1도는 일반적인 ONO구조의 인터폴리 절연막의 구조를 나타낸 수직 단면도.1 is a vertical cross-sectional view showing the structure of an interpoly insulating film of a general ONO structure.
제2도는 본 발명에 의한 인터폴리 절연막의 TDDB평가를 나타낸 그래프선도.2 is a graph showing TDDB evaluation of an interpoly insulation film according to the present invention.
본 발명은 인터폴리 절연막 형성방법에 관한 것으로서, 특히 ONO구조의 절연막질의 특성이 양호한 인터폴리 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an interpoly insulation film, and more particularly to a method of forming an interpoly insulation film having good characteristics of an insulating film quality of an ONO structure.
반도체 메모리의 고용량에 따라 메모리셀 크기의 축소는 현저하며, 이러한 크기의 축소에는 여러 가지 제약이 따른다.Reduction of the size of the memory cell is remarkable according to the high capacity of the semiconductor memory, and there are various constraints on the size reduction.
플로팅 게이트(Floating-Gate)형 불휘발성(Nonvolatile) 반도체 기억소자의 경우 사진식각 공정의 제약 외에 프로그램에 필요한 고전압에 견디고, 전하보존특성이 양호한 얇은 인터폴리 절연체를 형성하는 것도 큰 제약 요소중의 하나이다.In the case of floating-gate nonvolatile semiconductor memory devices, in addition to the limitations of the photolithography process, forming a thin interpoly insulator that can withstand high voltages required for programming and has good charge retention characteristics is one of the major constraints. .
예를들어 프로그램 동작 전압이 20V 수준인 플로팅 게이트 형 EEPROM 반도체 메모리 장치의 공정 조건의 경우 셀의 정상 동작에 필요한 0.7 정도의 커플링 율(Coupling Ration)를 얻기 위해서는 절연막 두께를 400㎛이하로 해야 하는 데 이때 통상의 폴리산화막의 경우 프로그램 및 소거시에 인가되는 고전압에 비해 파괴전압이 낮고 누설 전류가 커서 프로그램 특성이 저하되는 문제가 있다.For example, in the case of the process conditions of a floating gate type EEPROM semiconductor memory device having a program operating voltage of about 20V, in order to obtain a coupling ratio of about 0.7 required for the normal operation of the cell, the insulating film thickness must be 400 μm or less. In this case, the conventional polyoxide film has a problem that the breakdown voltage is low and the leakage current is large compared to the high voltage applied during programming and erasing, thereby degrading program characteristics.
이러한 문제를 해결하기 위해 인터폴리층에 보다 큰 유전율의 물질을 사용하여 인터폴리 절연막의 유효두께를 얇게 유지하므로써 프로그램 특성을 양호하게 유지하는 방법으로 고유전율을 가진 실리콘질화막(=7.5)을 사용하고 있는 데 질화막을 폴리실리콘에 직접 접촉시키면 낮은 전압에서 누설 전류가 증대하여 실제로 사용하기 어렵다.To solve this problem, a silicon nitride film (= 7.5) having a high dielectric constant is used as a method of maintaining a good program characteristic by maintaining a thin effective thickness of the interpoly insulation film by using a material having a higher dielectric constant in the interpoly layer. If the nitride film is in direct contact with polysilicon, the leakage current increases at low voltage, making it difficult to actually use it.
따라서, 제1도에 도시한 바와 같이 반도체 기판(10) 상에 필드산화막(14)을 형성하여 액티브 영역을 한정시키고 액티브 영역에는 터널 산화막(12)을 형성하고 그위에 하부 폴리실리콘층(20)을 형성하고 그 위에 차례로 폴리산화막(22), 질화막(24), 질화산화막(26)을 형성하고 그위에 상부 폴리실리콘층(28)을 형성하여서 플로팅 게이트 불휘발성 반도체 메모리 장치를 제조한다. 이와 같은 구조에서는 폴리실리콘에 접한 부분에는 산화막이 있도록 하고 그 사이에 질화막이 형성되어 있는 ONO(Oxide-Nitride-Oxide) 공정 구조는 이미 잘 알려져 있다.Accordingly, as shown in FIG. 1, the field oxide film 14 is formed on the semiconductor substrate 10 to define the active region, and the tunnel oxide film 12 is formed in the active region, and the lower polysilicon layer 20 is formed thereon. And a polyoxide film 22, a nitride film 24, and a nitride oxide film 26 are formed thereon, and an upper polysilicon layer 28 is formed thereon to manufacture a floating gate nonvolatile semiconductor memory device. In such a structure, an oxide-nitride-oxide (ONO) process structure in which an oxide film is provided at a portion in contact with polysilicon and a nitride film is formed therebetween is well known.
이때 ONO 절연막 침적후 상부 폴리실리콘과의 접착 불안정 문제를 해결하기 위하여 질화 산화막 성장 공정을 진행하는 데, 이 과정에서 질화막질의 공정 조건 및 균일한 상태와 질화산화막의 성장 조건 등에 따라 질화막의 전면을 코팅하지 못하고 부분적으로 두꺼운 산화막질을 형성시키는 이른바 ONO 결함을 유발시킨다.At this time, in order to solve the problem of adhesion instability with the upper polysilicon after depositing the ONO insulating film, a nitride oxide growth process is performed. During this process, the entire surface of the nitride film is coated according to the process conditions, uniform conditions, and growth conditions of the nitride oxide film. They fail to cause so-called ONO defects that partially form thick oxide films.
이러한 결함은 칩에 직접적인 영향으로 수율 저하를 가져온다.These defects have a direct impact on the chip, resulting in lower yields.
본 발명의 목적은 상술한 종래 기술의 문제점을 해결하기 위하여 질화막 침적 공정의 조건을 변경하여 이러한 결함 발생을 최소화시킬 수 있는 인터폴리 절연막을 형성하는 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming an interpoly insulation film capable of minimizing such defects by changing the conditions of a nitride film deposition process in order to solve the above-described problems of the prior art.
상기 목적을 달성하기 위하여 본 발명은 하부 폴리실리콘층과 상부 폴리실리콘층의 사이에 절연막을 형성하는 방법에 있어서, 하부 폴리실리콘층의 표면을 산화시켜서 폴리산화막을 형성하는 단계; 하부 폴리산화층 상에 700℃ 미만의 온도조건에서 분당 7Å 미만의 성막비율로 질화막을 형성하는 단계; 및 질화막의 표면을 산화시켜서 질화산화막을 형성하는 단계를 구비하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming an insulating film between a lower polysilicon layer and an upper polysilicon layer, comprising: oxidizing a surface of a lower polysilicon layer to form a polyoxide film; Forming a nitride film on the lower polyoxide layer at a film forming ratio of less than 7 Pa / min at a temperature of less than 700 ° C .; And oxidizing the surface of the nitride film to form a nitride oxide film.
이하, 첨부한 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.
본 발명에서는 ONO구조의 인터폴리 절연막의 질화산화막 형성을 위한 산화시 국부적으로 두꺼운 질화산화막이 형성되어 균일한 막 두께를 유지할 수 없는 것을 개선하기 위하여 제1도에 도시한 바와 같이, 하부 폴리실리콘층(20)의 표면을 산화시켜서 폴리산화막(22)을 형성한다. 하부 폴리산화막(22) 상에 700℃ 미만의 온도조건에서 분당 7Å 미만의 성막비율로 질화막(24)을 형성하고 상기 질화막(14)의 표면을 산화시켜서 질화산화막(26)을 형성하고 그위에 상부 폴리실리콘층(28)을 형성한다.In the present invention, as shown in FIG. 1, in order to improve that a locally thick nitride oxide film is formed at the time of oxidation for forming the nitride oxide film of the interpoly insulation film having an ONO structure, it is not possible to maintain a uniform film thickness. The surface of 20 is oxidized to form a polyoxide film 22. The nitride film 24 is formed on the lower poly oxide film 22 at a temperature ratio of less than 700 ° C. at a temperature of less than 700 ° C., and the surface of the nitride film 14 is oxidized to form a nitride oxide film 26. The polysilicon layer 28 is formed.
즉, 본 발명에서는 질화막의 공정조건을 종래 기술과 비교하면 다음 표 1과 같다.That is, in the present invention, the process conditions of the nitride film are shown in Table 1 below when compared with the prior art.
상기 표 1에 나타난 바와 같이 식각비의 경우에는 질화막의 식각용액을 사용할 때 종래 방법의 막질보다 약 10Å/M 가량 높다.As shown in Table 1, in the case of the etching ratio, when the etching solution of the nitride film is used, it is about 10 μs / M higher than the film quality of the conventional method.
전기적 특성 평가를 위해 다음과 같은 방법으로 시료를 제작하여 TDDB 평가를 하였다.In order to evaluate the electrical characteristics, the TDDB was evaluated by fabricating a sample as follows.
4인치 웨이퍼의 상부에 제1폴리실리콘을 5000Å의 두께로 침적한 후, 제 1 폴리실리콘에 Pocl(13.8Ω/SQR)의 불순물 주입공정을 거친 후에 제1폴리실리콘을 디글라이징 하고, 제1폴리실리콘의 표면을 산화시켜서 폴리실리콘-산화막을 125Å의 두께로 성장시킨 다음에, 상기 표 1의 공정조건에 의해 질화막을 125Å두께로 침적시킨다. 그 다음에 질화막의 표면을 산화시켜서 질화산화막을 3000Å의 두께로 성장시키고 금속을 증착한 후 이를 사진식각하여 백-랩(Back-Lap)을 측정하였더니 425㎛이었다.After depositing the first polysilicon on the 4-inch wafer to a thickness of 5000Å, Pocl (13.8Ω / SQR) impurity implantation process on the first polysilicon and then deglazing the first polysilicon, the first polysilicon After oxidizing the surface of silicon to grow the polysilicon oxide film to a thickness of 125 kV, the nitride film was deposited to 125 kPa by the process conditions shown in Table 1 above. Then, the surface of the nitride film was oxidized, the nitride oxide film was grown to a thickness of 3000 Å, the metal was deposited, and the back-lap was measured by photolithography. The back-lap was 425 μm.
제2도에 도시한 바와 같이, 질화막의 경우 목표 125Å은 유지하면서 성막비율조건을 종래기술(DN)과 신규기술(DD)로 분리하였고, 질화산화막의 경우 베어 상의 산화막의 막질 두께를 산화막 형성시 주는 충격을 최소화 시키는 쪽으로 낮추어서 산화막 두께를 기존(3300Å, SN)과 변경조건(1800Å, SD)으로 평가해 보았다.As shown in FIG. 2, in the case of the nitride film, the deposition rate condition was separated into the conventional technology (DN) and the new technology (DD) while maintaining the target of 125 Å. The state was lowered to minimize the impact, and the thickness of the oxide film was evaluated with the existing (3300Å, SN) and the modified condition (1800Å, SD).
여기에서 질화산화막은 기존 3300Å(Bare Wafer 상)조건에서 성막비율 다운조건이 가장 양호한 결과를 얻었다.In this case, the nitride oxide film had the best film forming ratio down condition under the existing 3300Å (bare wafer phase) condition.
실제 런적용 결과는 다음 표 2와 같다.Actual run results are shown in Table 2 below.
표2에 나타난 바와 같이 본 발명에 의한 인터폴리 절연막 형성공정을 사용한 반도체 메모리의 경우에는 종래 기술의 반도체 메모리에 비해 수율이 향상됨을 알 수 있다.As shown in Table 2, in the case of the semiconductor memory using the interpoly insulation film forming process according to the present invention, it can be seen that the yield is improved compared to the semiconductor memory of the prior art.
Claims (3)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950061323A KR0164514B1 (en) | 1995-12-28 | 1995-12-28 | Forming method of interpoly insulating film |
| JP8186329A JPH09186258A (en) | 1995-12-28 | 1996-07-16 | Forming method of interpoly insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950061323A KR0164514B1 (en) | 1995-12-28 | 1995-12-28 | Forming method of interpoly insulating film |
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| Publication Number | Publication Date |
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| KR970052846A KR970052846A (en) | 1997-07-29 |
| KR0164514B1 true KR0164514B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950061323A KR0164514B1 (en) | 1995-12-28 | 1995-12-28 | Forming method of interpoly insulating film |
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|---|---|
| JP (1) | JPH09186258A (en) |
| KR (1) | KR0164514B1 (en) |
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1995
- 1995-12-28 KR KR1019950061323A patent/KR0164514B1/en not_active IP Right Cessation
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1996
- 1996-07-16 JP JP8186329A patent/JPH09186258A/en not_active Withdrawn
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| KR970052846A (en) | 1997-07-29 |
| JPH09186258A (en) | 1997-07-15 |
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