KR860000708A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR860000708A
KR860000708A KR1019850003834A KR850003834A KR860000708A KR 860000708 A KR860000708 A KR 860000708A KR 1019850003834 A KR1019850003834 A KR 1019850003834A KR 850003834 A KR850003834 A KR 850003834A KR 860000708 A KR860000708 A KR 860000708A
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South Korea
Prior art keywords
copper
layer
lead
ferret
semiconductor device
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KR1019850003834A
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English (en)
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KR930010073B1 (ko
Inventor
아기라 스즈기 (외 2)
Original Assignee
미쓰다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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Publication of KR860000708A publication Critical patent/KR860000708A/ko
Application granted granted Critical
Publication of KR930010073B1 publication Critical patent/KR930010073B1/ko

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Abstract

내용 없음

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는, 본 발명의 실시예에 있어서의 반도체 장치의 부분 확대단면도. 제3도는, 본 발명의 다른 실시예인 PLCC형의 반도체장치를 도시한 부분 절단 사시도.

Claims (16)

  1. 반도체 소자를 주요소로 한 전기회로가 형성되여 있는 페렛과, 페렛에 있어서의 다수개의 전기단자와 전기적으로 접속되여 있는 여러줄의 리이드와, 페렛과 각각의 리이드의 일부를 봉지하고 있는 봉지체로 되는 반도체 장치에 있어서, 상기 리이드에 있어서의 봉지체에서 노출하고 있는 부분의 리이드는, 표면에 땜남층이 형성되며, 그 땜남층의 밑바닥층으로서, 동을 주성분으로 하는 금속 도금층이 마련되여 있는 것을 특징으로 하는 반도체장치.
  2. 특허청구의 범위 제1항에 있어서, 리이드의 모재는, 동을 주성분으로 하는 동합금이다.
  3. 특허청구의 범위 제1항에 있어서, 리이드의 모재는, 동을 주성분으로 하는 동합금이며, 리이드의 모재표면에 주석과 니켈과의 합금층이 형성되여 있다.
  4. 특허청구의 범위 제1항에 있어서, 리이드의 모재는, 동을 주성분으로 하는 동합금이며, 리이드의 모재 표면에 철과 니켈과의 합금층이 형성되여 있다.
  5. 특허청구의 범위 제1항에 있어서, 동을 주성분으로 하는 금속 도금층은, 순수한 동과 불가피한 불순물으로 되는 순수한 동 도금층이다.
  6. 특허청구의 범위 제1항에 있어서, 동을 주성분으로 하는 금속 도금층은, 아연 0.05∼0.2중량%을 포함하고, 나머지는 동과 불가피한 불순물로 되는 아연과 동과의 합금 도금층이다.
  7. 반도체 소자를 주요소로 한 반도체 집적회로가 형성되여 있는 페렛과, 페렛에 있어서의 다수개의 본딩페드와 가느다란 금속선에 의해 전기적으로 접속되여 있는 여러줄의 리이드와, 페렛과 가느다란 금속선에 가느다란 금속선이 접속되여 있는 리이드 주변인 일부와를 봉지하고 있는 수지 봉지체로 되는 반도체장치에 있어서, 상기 리이드에 모재는 동을 주성분으로 하는 동 합금체이며, 그 리이드의 모재 전면에 주석 또는 철과 니켈과의 합금층이 형성되여 있고, 상기 리이드에 있어서의 수지봉지체에서 노출하고 있는 부분의 리이드에는, 표면에 땜남층이 형성되여 있으며, 그 땜남층의 밑바닥층으로서 동을 주성분으로 하는 금속 도금층이 마련되어 있는 것을 특징으로 하는 반도체 장치.
  8. 특허청구의 범위 제7항에 있어서, 동을 주성분으로 하는 금속 도금층으로서는, 순수한 동과, 불가피한 불순물로서 되는 순수한 동 도금층이다.
  9. 특허청구의 범위 제7항에 있어서, 동을 주성분으로 하는 금속 도금층은, 아연 0.05∼0.2중량%을 포함하고, 나머지가 동과 불가피한 불순물으로 되는 아연과 동과의 합금 도금층이다.
  10. 특허청구의 범위 제7항에 있어서, 상기 반도체 장치는 PLLC(Plastic Leaded Chip Carrier) 형의 반도체 장치이다.
  11. 특허청구의 범위 제7항에 있어서, 상기 반도체 장치는 EPP(Flat Plastic Package)형의 반도체 장치이다.
  12. 반도체 소자를 주요소로 한 전기회로가 형성되어 있는 페렛과, 페렛에 있어서의 다수개의 전기단자와 전기적으로 접속되여 있는 여러 줄의 리이드와, 페렛과 각각의 리이드의 일부와를 봉지하고 있는 봉지체로 되는 반도체 장치의 제조 방법에 있어서, 상기 리이드에 있어서의 봉지체에서 노출하고 있는 부분의 리인드에, 동을 주성분으로 하는 금속층을 도금법에 의해 형성하고, 이어서, 상기 금속층을 밑바닥층으로 해서 땜납층을 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
  13. 특허청구의 범위 제12항에 있어서, 동을 주성분으로 하는 금속층은, 순수한 동과 불가피한 불순물으로 되는 순수한 동도금법에 의해 형성하는 것을 특징으로 한다.
  14. 특허청구의 범위 제12항에 있어서, 동을 주성분으로 하는 금속층은, 아연 0.05∼0.2중량%를 포함하고, 나머지가 동과 불가피한 불순물로 되는 아연과의 합금을 도금법에 의해 형성되는 것을 특징으로 한다.
  15. 반도체 소자를 주요소로 한 반도체 집적회로가 형성되여 있는 페렛을, 동을 주성분으로 하는 동 합금을 모재로 하는 리이드 프레임에, 페렛 본딩을 하는 공정과, 페렛에 있어서의 각 본딩 페드와 그에 대응하는 리이드와를 가느다란 금속선에 의해서 와이어 본딩하는 공정과, 페렛과 그 주변을 수지에 의해 봉지하여 수지 봉지체를 형성하는 공정과, 수지봉지체에서 노출하고 있는 리이드의 표면에 순수한 동층 또는 0.05∼0.2중량%의 아연을 포함하는 동합금층을 형성하는 공정과, 상기 순수한 동층 또는 동합금층을 밑바닥층으로서 땜납층을 형성하는 반도체 장치의 제조방법.
  16. 특허청구의 범위 제15항에 있어서, 리이드 프레임으로서는, 그 모재의 표면에 주선과 니켈과의 합금층 또는 철과 니켈과의 합금층이 형성되여 있는 리이드 프레임을 사용한다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850003834A 1984-06-04 1985-06-01 반도체 장치 및 그 제조방법 KR930010073B1 (ko)

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KR930010073B1 (ko) 1993-10-14
JPS60257160A (ja) 1985-12-18
US4707724A (en) 1987-11-17

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