KR20150132371A - 집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 - Google Patents
집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 Download PDFInfo
- Publication number
- KR20150132371A KR20150132371A KR1020157029081A KR20157029081A KR20150132371A KR 20150132371 A KR20150132371 A KR 20150132371A KR 1020157029081 A KR1020157029081 A KR 1020157029081A KR 20157029081 A KR20157029081 A KR 20157029081A KR 20150132371 A KR20150132371 A KR 20150132371A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- dimensional
- tier
- memory cell
- 3dic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- H01L27/0688—
-
- H01L27/1108—
-
- H01L27/1116—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361800220P | 2013-03-15 | 2013-03-15 | |
| US61/800,220 | 2013-03-15 | ||
| US13/939,274 US9171608B2 (en) | 2013-03-15 | 2013-07-11 | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
| US13/939,274 | 2013-07-11 | ||
| PCT/US2014/022929 WO2014150317A1 (en) | 2013-03-15 | 2014-03-11 | Three-dimensional (3d) memory cell with read/write ports and access logic on different tiers of the integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167035866A Division KR20170000397A (ko) | 2013-03-15 | 2014-03-11 | 집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20150132371A true KR20150132371A (ko) | 2015-11-25 |
Family
ID=51526452
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157029081A Ceased KR20150132371A (ko) | 2013-03-15 | 2014-03-11 | 집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 |
| KR1020167035866A Withdrawn KR20170000397A (ko) | 2013-03-15 | 2014-03-11 | 집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167035866A Withdrawn KR20170000397A (ko) | 2013-03-15 | 2014-03-11 | 집적 회로의 상이한 티어들상에 판독/기록 포트들 및 액세스 로직을 가진 3차원(3d) 메모리 셀 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9171608B2 (https=) |
| EP (1) | EP2973706B1 (https=) |
| JP (2) | JP6309608B2 (https=) |
| KR (2) | KR20150132371A (https=) |
| CN (1) | CN105144381B (https=) |
| WO (1) | WO2014150317A1 (https=) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9064077B2 (en) | 2012-11-28 | 2015-06-23 | Qualcomm Incorporated | 3D floorplanning using 2D and 3D blocks |
| US9098666B2 (en) | 2012-11-28 | 2015-08-04 | Qualcomm Incorporated | Clock distribution network for 3D integrated circuit |
| US9536840B2 (en) | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
| US9041448B2 (en) | 2013-03-05 | 2015-05-26 | Qualcomm Incorporated | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods |
| US9177890B2 (en) | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
| US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
| US9418985B2 (en) | 2013-07-16 | 2016-08-16 | Qualcomm Incorporated | Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology |
| US9524920B2 (en) | 2013-11-12 | 2016-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method of three dimensional conductive lines |
| US9123721B2 (en) * | 2013-11-22 | 2015-09-01 | Qualcomm Incorporated | Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace |
| US9256246B1 (en) * | 2015-01-29 | 2016-02-09 | Qualcomm Incorporated | Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) |
| US9537471B2 (en) | 2015-02-09 | 2017-01-03 | Qualcomm Incorporated | Three dimensional logic circuit |
| US20190148286A1 (en) * | 2015-09-21 | 2019-05-16 | Monolithic 3D Inc. | Multi-level semiconductor device and structure with memory |
| US11978731B2 (en) * | 2015-09-21 | 2024-05-07 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
| US9691695B2 (en) * | 2015-08-31 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure |
| US9754660B2 (en) * | 2015-11-19 | 2017-09-05 | Samsung Electronics Co., Ltd. | Semiconductor device |
| CN105304123B (zh) * | 2015-12-04 | 2018-06-01 | 上海兆芯集成电路有限公司 | 静态随机存取存储器 |
| US10672745B2 (en) * | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D processor |
| TWI698871B (zh) * | 2017-01-03 | 2020-07-11 | 聯華電子股份有限公司 | 六電晶體靜態隨機存取記憶體單元及其操作方法 |
| US9929733B1 (en) * | 2017-02-21 | 2018-03-27 | Qualcomm Incorporated | Connection propagation for inter-logical block connections in integrated circuits |
| US10176147B2 (en) | 2017-03-07 | 2019-01-08 | Qualcomm Incorporated | Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods |
| US10572344B2 (en) | 2017-04-27 | 2020-02-25 | Texas Instruments Incorporated | Accessing error statistics from DRAM memories having integrated error correction |
| CN107240415B (zh) * | 2017-06-06 | 2020-09-15 | 上海兆芯集成电路有限公司 | 储存装置 |
| CN107230491B (zh) * | 2017-06-06 | 2020-09-04 | 上海兆芯集成电路有限公司 | 储存装置的控制方法 |
| JP2019160930A (ja) * | 2018-03-09 | 2019-09-19 | 株式会社東芝 | コンフィグレーションメモリ回路 |
| US10599806B2 (en) * | 2018-03-28 | 2020-03-24 | Arm Limited | Multi-tier co-placement for integrated circuitry |
| JP7426547B2 (ja) * | 2018-10-29 | 2024-02-02 | 東京エレクトロン株式会社 | 半導体素子のモノリシック3d集積を行うためのアーキテクチャ |
| KR102174486B1 (ko) * | 2019-02-27 | 2020-11-04 | 고려대학교 산학협력단 | 삼차원 크로스바 네트워크 기반의 그래픽 처리유닛 |
| JP6901515B2 (ja) * | 2019-04-04 | 2021-07-14 | ウィンボンド エレクトロニクス コーポレーション | 半導体装置 |
| US12513984B2 (en) * | 2020-06-18 | 2025-12-30 | Intel Corporation | Double-sided integrated circuit transistor structures with depopulated bottom channel regions |
| US11315628B1 (en) * | 2020-10-21 | 2022-04-26 | Arm Limited | Techniques for powering memory |
| US11455454B2 (en) * | 2020-11-24 | 2022-09-27 | Arm Limited | Methods and apparatuses for concurrent coupling of inter-tier connections |
| US11532353B2 (en) * | 2021-01-29 | 2022-12-20 | Arm Limited | Circuitry apportioning of an integrated circuit |
| TWI912570B (zh) * | 2021-12-16 | 2026-01-21 | 新加坡商發明與合作實驗室有限公司 | 高性能運算和高儲存容量的同構/異構積體電路系統 |
| EP4199090A1 (en) | 2021-12-20 | 2023-06-21 | Imec VZW | Multiport sram in sequential 3d technology |
| US12484207B2 (en) | 2021-12-23 | 2025-11-25 | Intel Corporation | SRAM with channel count contrast for greater read stability |
Family Cites Families (147)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3593348B2 (ja) | 1992-12-29 | 2004-11-24 | 富士通株式会社 | 集積回路 |
| JPH07176688A (ja) | 1993-12-20 | 1995-07-14 | Mitsubishi Electric Corp | 半導体集積回路 |
| US5495419A (en) | 1994-04-19 | 1996-02-27 | Lsi Logic Corporation | Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing |
| JPH097373A (ja) * | 1995-06-20 | 1997-01-10 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
| US5724557A (en) | 1995-07-10 | 1998-03-03 | Motorola, Inc. | Method for designing a signal distribution network |
| JPH09198870A (ja) * | 1996-01-24 | 1997-07-31 | Nippon Telegr & Teleph Corp <Ntt> | マルチポートメモリ |
| US5760478A (en) | 1996-08-20 | 1998-06-02 | International Business Machines Corporation | Clock skew minimization system and method for integrated circuits |
| US6374200B1 (en) | 1997-02-03 | 2002-04-16 | Fujitsu Limited | Layout apparatus for laying out objects in space and method thereof |
| DE19740695C2 (de) * | 1997-09-16 | 2002-11-21 | Infineon Technologies Ag | Datenspeicher mit Mehrebenenhierarchie |
| US6037822A (en) | 1997-09-30 | 2000-03-14 | Intel Corporation | Method and apparatus for distributing a clock on the silicon backside of an integrated circuit |
| US6686623B2 (en) | 1997-11-18 | 2004-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and electronic apparatus |
| US6295636B1 (en) | 1998-02-20 | 2001-09-25 | Lsi Logic Corporation | RTL analysis for improved logic synthesis |
| JP4085459B2 (ja) | 1998-03-02 | 2008-05-14 | セイコーエプソン株式会社 | 3次元デバイスの製造方法 |
| US6260182B1 (en) | 1998-03-27 | 2001-07-10 | Xilinx, Inc. | Method for specifying routing in a logic module by direct module communication |
| US6305001B1 (en) | 1998-06-18 | 2001-10-16 | Lsi Logic Corporation | Clock distribution network planning and method therefor |
| US6125217A (en) | 1998-06-26 | 2000-09-26 | Intel Corporation | Clock distribution network |
| US7157314B2 (en) | 1998-11-16 | 2007-01-02 | Sandisk Corporation | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| FR2797713B1 (fr) | 1999-08-20 | 2002-08-02 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| JP2001160612A (ja) | 1999-12-01 | 2001-06-12 | Takehide Shirato | 半導体装置及びその製造方法 |
| US7483329B2 (en) * | 2000-01-06 | 2009-01-27 | Super Talent Electronics, Inc. | Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages |
| TW587252B (en) * | 2000-01-18 | 2004-05-11 | Hitachi Ltd | Semiconductor memory device and data processing device |
| KR100549258B1 (ko) | 2000-06-02 | 2006-02-03 | 주식회사 실트론 | 에스오아이 웨이퍼 제조 방법 |
| US6834380B2 (en) | 2000-08-03 | 2004-12-21 | Qualcomm, Incorporated | Automated EMC-driven layout and floor planning of electronic devices and systems |
| US7700454B2 (en) | 2001-07-24 | 2010-04-20 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities |
| US6627985B2 (en) | 2001-12-05 | 2003-09-30 | Arbor Company Llp | Reconfigurable processor module comprising hybrid stacked integrated circuit die elements |
| US6754877B1 (en) | 2001-12-14 | 2004-06-22 | Sequence Design, Inc. | Method for optimal driver selection |
| US6670642B2 (en) * | 2002-01-22 | 2003-12-30 | Renesas Technology Corporation. | Semiconductor memory device using vertical-channel transistors |
| US6730540B2 (en) | 2002-04-18 | 2004-05-04 | Tru-Si Technologies, Inc. | Clock distribution networks and conductive lines in semiconductor integrated circuits |
| DE10226915A1 (de) | 2002-06-17 | 2004-01-08 | Infineon Technologies Ag | Verfahren zum Verändern von Entwurfsdaten für die Herstellung eines Bauteils sowie zugehörige Einheiten |
| US6979630B2 (en) | 2002-08-08 | 2005-12-27 | Isonics Corporation | Method and apparatus for transferring a thin layer of semiconductor material |
| US7209378B2 (en) | 2002-08-08 | 2007-04-24 | Micron Technology, Inc. | Columnar 1T-N memory cell structure |
| US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
| US7508034B2 (en) | 2002-09-25 | 2009-03-24 | Sharp Kabushiki Kaisha | Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device |
| US7042756B2 (en) | 2002-10-18 | 2006-05-09 | Viciciv Technology | Configurable storage device |
| US6965527B2 (en) | 2002-11-27 | 2005-11-15 | Matrix Semiconductor, Inc | Multibank memory on a die |
| US7138685B2 (en) | 2002-12-11 | 2006-11-21 | International Business Machines Corporation | Vertical MOSFET SRAM cell |
| JP4554152B2 (ja) | 2002-12-19 | 2010-09-29 | 株式会社半導体エネルギー研究所 | 半導体チップの作製方法 |
| US6727530B1 (en) | 2003-03-04 | 2004-04-27 | Xindium Technologies, Inc. | Integrated photodetector and heterojunction bipolar transistors |
| US6911375B2 (en) | 2003-06-02 | 2005-06-28 | International Business Machines Corporation | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature |
| US8071438B2 (en) | 2003-06-24 | 2011-12-06 | Besang Inc. | Semiconductor circuit |
| JP4019021B2 (ja) * | 2003-07-14 | 2007-12-05 | 日本テキサス・インスツルメンツ株式会社 | 半導体メモリセル |
| US7107200B1 (en) | 2003-10-03 | 2006-09-12 | Sun Microsystems, Inc. | Method and apparatus for predicting clock skew for incomplete integrated circuit design |
| US7378702B2 (en) | 2004-06-21 | 2008-05-27 | Sang-Yun Lee | Vertical memory device structures |
| JP4534132B2 (ja) * | 2004-06-29 | 2010-09-01 | エルピーダメモリ株式会社 | 積層型半導体メモリ装置 |
| JP4421957B2 (ja) * | 2004-06-29 | 2010-02-24 | 日本電気株式会社 | 3次元半導体装置 |
| US7546571B2 (en) | 2004-09-08 | 2009-06-09 | Mentor Graphics Corporation | Distributed electronic design automation environment |
| US20060190889A1 (en) | 2005-01-14 | 2006-08-24 | Cong Jingsheng J | Circuit floorplanning and placement by look-ahead enabled recursive partitioning |
| WO2006135780A1 (en) | 2005-06-10 | 2006-12-21 | The Regents Of The University Of California | Fast dual-vdd buffer insertion and buffered tree construction for power minimization |
| EP1907957A4 (en) | 2005-06-29 | 2013-03-20 | Otrsotech Ltd Liability Company | INVESTMENT METHODS AND SYSTEMS |
| US7280397B2 (en) | 2005-07-11 | 2007-10-09 | Sandisk 3D Llc | Three-dimensional non-volatile SRAM incorporating thin-film device layer |
| DE102005039365B4 (de) | 2005-08-19 | 2022-02-10 | Infineon Technologies Ag | Gate-gesteuertes Fin-Widerstandselement, welches als pinch - resistor arbeitet, zur Verwendung als ESD-Schutzelement in einem elektrischen Schaltkreis und Einrichtung zum Schutz vor elektrostatischen Entladungen in einem elektrischen Schaltkreis |
| US7663620B2 (en) | 2005-12-05 | 2010-02-16 | Microsoft Corporation | Accessing 2D graphic content using axonometric layer views |
| CA2580998A1 (en) | 2006-03-03 | 2007-09-03 | Queen's University At Kingston | Adaptive analysis methods |
| US7579654B2 (en) | 2006-05-31 | 2009-08-25 | Corning Incorporated | Semiconductor on insulator structure made using radiation annealing |
| KR20080038535A (ko) | 2006-10-30 | 2008-05-07 | 삼성전자주식회사 | 스택형 반도체 장치의 제조 방법 |
| US7859117B2 (en) | 2007-02-27 | 2010-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Clocking architecture in stacked and bonded dice |
| US7669152B1 (en) | 2007-03-13 | 2010-02-23 | Silicon Frontline Technology Inc. | Three-dimensional hierarchical coupling extraction |
| US7739642B2 (en) | 2007-05-02 | 2010-06-15 | Cadence Design Systems, Inc. | Optimizing integrated circuit design through balanced combinational slack plus sequential slack |
| US7624364B2 (en) | 2007-05-02 | 2009-11-24 | Cadence Design Systems, Inc. | Data path and placement optimization in an integrated circuit through use of sequential timing information |
| US8513791B2 (en) | 2007-05-18 | 2013-08-20 | International Business Machines Corporation | Compact multi-port CAM cell implemented in 3D vertical integration |
| US20080291767A1 (en) | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Multiple wafer level multiple port register file cell |
| US7796092B2 (en) | 2007-05-24 | 2010-09-14 | The Boeing Company | Broadband composite dipole antenna arrays for optical wave mixing |
| US7459716B2 (en) | 2007-06-11 | 2008-12-02 | Kabushiki Kaisha Toshiba | Resistance change memory device |
| KR100896883B1 (ko) | 2007-08-16 | 2009-05-14 | 주식회사 동부하이텍 | 반도체칩, 이의 제조방법 및 이를 가지는 적층 패키지 |
| US8136071B2 (en) | 2007-09-12 | 2012-03-13 | Neal Solomon | Three dimensional integrated circuits and methods of fabrication |
| US8046727B2 (en) | 2007-09-12 | 2011-10-25 | Neal Solomon | IP cores in reconfigurable three dimensional integrated circuits |
| US8059443B2 (en) | 2007-10-23 | 2011-11-15 | Hewlett-Packard Development Company, L.P. | Three-dimensional memory module architectures |
| JP2009164480A (ja) | 2008-01-09 | 2009-07-23 | Toshiba Corp | 抵抗変化メモリ装置 |
| CN101246740A (zh) * | 2008-03-13 | 2008-08-20 | 复旦大学 | 一种超低功耗非挥发静态随机存取存储单元及其操作方法 |
| US7622955B2 (en) | 2008-04-17 | 2009-11-24 | Texas Instruments Incorporated | Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme |
| US8218377B2 (en) | 2008-05-19 | 2012-07-10 | Stmicroelectronics Pvt. Ltd. | Fail-safe high speed level shifter for wide supply voltage range |
| US8716805B2 (en) | 2008-06-10 | 2014-05-06 | Toshiba America Research, Inc. | CMOS integrated circuits with bonded layers containing functional electronic devices |
| US8060843B2 (en) | 2008-06-18 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verification of 3D integrated circuits |
| US8006212B2 (en) | 2008-07-30 | 2011-08-23 | Synopsys, Inc. | Method and system for facilitating floorplanning for 3D IC |
| EP2161755A1 (en) | 2008-09-05 | 2010-03-10 | University College Cork-National University of Ireland, Cork | Junctionless Metal-Oxide-Semiconductor Transistor |
| US8230375B2 (en) | 2008-09-14 | 2012-07-24 | Raminda Udaya Madurawe | Automated metal pattern generation for integrated circuits |
| WO2010062644A2 (en) | 2008-10-28 | 2010-06-03 | The Regents Of The University Of California | Vertical group iii-v nanowires on si, heterostructures, flexible arrays and fabrication |
| KR20100048610A (ko) * | 2008-10-31 | 2010-05-11 | 삼성전자주식회사 | 반도체 패키지 및 그 형성 방법 |
| WO2010055462A1 (en) | 2008-11-13 | 2010-05-20 | Nxp B.V. | Testable integrated circuit and test method therefor |
| US20100140790A1 (en) | 2008-12-05 | 2010-06-10 | Seagate Technology Llc | Chip having thermal vias and spreaders of cvd diamond |
| US8146032B2 (en) | 2009-01-30 | 2012-03-27 | Synopsys, Inc. | Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs |
| US7884004B2 (en) | 2009-02-04 | 2011-02-08 | International Business Machines Corporation | Maskless process for suspending and thinning nanowires |
| US8536629B2 (en) | 2009-02-24 | 2013-09-17 | Nec Corporation | Semiconductor device and method for manufacturing the same |
| US8214790B2 (en) | 2009-03-04 | 2012-07-03 | Oracle America | Low RC global clock distribution |
| US7964916B2 (en) | 2009-04-14 | 2011-06-21 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
| US8362482B2 (en) | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
| US8115511B2 (en) | 2009-04-14 | 2012-02-14 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
| US8258810B2 (en) | 2010-09-30 | 2012-09-04 | Monolithic 3D Inc. | 3D semiconductor device |
| US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
| US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
| WO2010134019A2 (en) | 2009-05-19 | 2010-11-25 | Ramot At Tel Aviv University Ltd. | Vertical junction pv cells |
| US8422273B2 (en) | 2009-05-21 | 2013-04-16 | International Business Machines Corporation | Nanowire mesh FET with multiple threshold voltages |
| CN102471664A (zh) | 2009-06-30 | 2012-05-23 | 日立化成工业株式会社 | 感光性粘接剂、以及使用该粘接剂的膜状粘接剂、粘接片、粘接剂图形、带有粘接剂层的半导体晶片和半导体装置 |
| JP4883203B2 (ja) | 2009-07-01 | 2012-02-22 | 株式会社テラミクロス | 半導体装置の製造方法 |
| US7955940B2 (en) | 2009-09-01 | 2011-06-07 | International Business Machines Corporation | Silicon-on-insulator substrate with built-in substrate junction |
| US8426309B2 (en) | 2009-09-10 | 2013-04-23 | Lockheed Martin Corporation | Graphene nanoelectric device fabrication |
| KR101703207B1 (ko) * | 2009-09-30 | 2017-02-06 | 알테라 코포레이션 | 압축 및 압축해제를 이용한 향상된 멀티 프로세서 파형 데이터 교환 |
| US8164089B2 (en) | 2009-10-08 | 2012-04-24 | Xerox Corporation | Electronic device |
| US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
| US8247895B2 (en) | 2010-01-08 | 2012-08-21 | International Business Machines Corporation | 4D device process and structure |
| US8026521B1 (en) | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
| US8298875B1 (en) | 2011-03-06 | 2012-10-30 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
| US20120305893A1 (en) | 2010-02-19 | 2012-12-06 | University College Cork-National University of Ireland ,Cork | Transistor device |
| US8450779B2 (en) | 2010-03-08 | 2013-05-28 | International Business Machines Corporation | Graphene based three-dimensional integrated circuit device |
| US8315084B2 (en) | 2010-03-10 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully balanced dual-port memory cell |
| JP5629309B2 (ja) | 2010-03-15 | 2014-11-19 | 株式会社日立製作所 | 半導体装置およびそのテスト方法 |
| US20110272788A1 (en) | 2010-05-10 | 2011-11-10 | International Business Machines Corporation | Computer system wafer integrating different dies in stacked master-slave structures |
| US8395942B2 (en) | 2010-05-17 | 2013-03-12 | Sandisk Technologies Inc. | Junctionless TFT NAND flash memory |
| US8332803B1 (en) | 2010-06-28 | 2012-12-11 | Xilinx, Inc. | Method and apparatus for integrated circuit package thermo-mechanical reliability analysis |
| US7969193B1 (en) | 2010-07-06 | 2011-06-28 | National Tsing Hua University | Differential sensing and TSV timing control scheme for 3D-IC |
| TWI562313B (en) | 2010-09-06 | 2016-12-11 | shu lu Chen | Electrical switch using a recessed channel gated resistor structure and method for three dimensional integration of semiconductor device |
| US8273610B2 (en) * | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
| US8114757B1 (en) | 2010-10-11 | 2012-02-14 | Monolithic 3D Inc. | Semiconductor device and structure |
| CN102754102B (zh) | 2010-12-09 | 2016-02-03 | 松下电器产业株式会社 | 三维集成电路的设计支持装置及设计支持方法 |
| US8691179B2 (en) | 2011-01-04 | 2014-04-08 | Korea Institute Of Science And Technology | Method for fabricating graphene sheets or graphene particles using supercritical fluid |
| TWI405325B (zh) * | 2011-01-19 | 2013-08-11 | Global Unichip Corp | 靜電放電保護電路 |
| US8409957B2 (en) | 2011-01-19 | 2013-04-02 | International Business Machines Corporation | Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits |
| US8487378B2 (en) | 2011-01-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform channel junction-less transistor |
| JP5684590B2 (ja) * | 2011-01-28 | 2015-03-11 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
| FR2972077B1 (fr) | 2011-02-24 | 2013-08-30 | Thales Sa | Composant electronique, procede de fabrication et utilisation de graphene dans un composant electronique |
| WO2012119053A1 (en) | 2011-03-02 | 2012-09-07 | King Abdullah University Of Science And Technology | Cylindrical-shaped nanotube field effect transistor |
| US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
| FR2973938A1 (fr) | 2011-04-08 | 2012-10-12 | Soitec Silicon On Insulator | Procédés de formation de structures semi-conductrices collées, et structures semi-conductrices formées par ces procédés |
| US8685825B2 (en) | 2011-07-27 | 2014-04-01 | Advanced Ion Beam Technology, Inc. | Replacement source/drain finFET fabrication |
| FR2978604B1 (fr) | 2011-07-28 | 2018-09-14 | Soitec | Procede de guerison de defauts dans une couche semi-conductrice |
| US8683416B1 (en) | 2011-07-28 | 2014-03-25 | Juniper Networks, Inc. | Integrated circuit optimization |
| FR2978605B1 (fr) | 2011-07-28 | 2015-10-16 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support |
| US8576000B2 (en) | 2011-08-25 | 2013-11-05 | International Business Machines Corporation | 3D chip stack skew reduction with resonant clock and inductive coupling |
| US8803233B2 (en) | 2011-09-23 | 2014-08-12 | International Business Machines Corporation | Junctionless transistor |
| TWI573198B (zh) | 2011-09-27 | 2017-03-01 | 索泰克公司 | 在三度空間集積製程中轉移材料層之方法及其相關結構與元件 |
| US8580624B2 (en) | 2011-11-01 | 2013-11-12 | International Business Machines Corporation | Nanowire FET and finFET hybrid technology |
| TWI456739B (zh) | 2011-12-13 | 2014-10-11 | Nat Univ Tsing Hua | 三維記憶體晶片之控制結構 |
| KR101786453B1 (ko) * | 2011-12-28 | 2017-10-18 | 인텔 코포레이션 | 집적 회로 디바이스의 트랜지스터들을 적층한 장치 및 제조방법 |
| JP5456090B2 (ja) | 2012-03-13 | 2014-03-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
| KR20130126036A (ko) | 2012-05-10 | 2013-11-20 | 삼성전자주식회사 | 트랜지스터를 구비한 반도체 소자 |
| US8796829B2 (en) | 2012-09-21 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal dissipation through seal rings in 3DIC structure |
| US8737108B2 (en) | 2012-09-25 | 2014-05-27 | Intel Corporation | 3D memory configurable for performance and power |
| US8701073B1 (en) | 2012-09-28 | 2014-04-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for across-chip thermal and power management in stacked IC designs |
| US9490811B2 (en) | 2012-10-04 | 2016-11-08 | Efinix, Inc. | Fine grain programmable gate architecture with hybrid logic/routing element and direct-drive routing |
| US9064077B2 (en) | 2012-11-28 | 2015-06-23 | Qualcomm Incorporated | 3D floorplanning using 2D and 3D blocks |
| US9098666B2 (en) | 2012-11-28 | 2015-08-04 | Qualcomm Incorporated | Clock distribution network for 3D integrated circuit |
| US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
| US20140225218A1 (en) | 2013-02-12 | 2014-08-14 | Qualcomm Incorporated | Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems |
| US9536840B2 (en) | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
| US9041448B2 (en) | 2013-03-05 | 2015-05-26 | Qualcomm Incorporated | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods |
| US9177890B2 (en) | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
| US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
-
2013
- 2013-07-11 US US13/939,274 patent/US9171608B2/en active Active
-
2014
- 2014-03-11 CN CN201480014060.7A patent/CN105144381B/zh not_active Expired - Fee Related
- 2014-03-11 JP JP2016501104A patent/JP6309608B2/ja not_active Expired - Fee Related
- 2014-03-11 EP EP14712553.8A patent/EP2973706B1/en not_active Not-in-force
- 2014-03-11 WO PCT/US2014/022929 patent/WO2014150317A1/en not_active Ceased
- 2014-03-11 KR KR1020157029081A patent/KR20150132371A/ko not_active Ceased
- 2014-03-11 KR KR1020167035866A patent/KR20170000397A/ko not_active Withdrawn
-
2015
- 2015-07-02 US US14/790,510 patent/US9583179B2/en active Active
-
2016
- 2016-12-02 JP JP2016234984A patent/JP2017085120A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP2973706B1 (en) | 2020-12-30 |
| US9171608B2 (en) | 2015-10-27 |
| CN105144381B (zh) | 2018-01-19 |
| KR20170000397A (ko) | 2017-01-02 |
| EP2973706A1 (en) | 2016-01-20 |
| WO2014150317A1 (en) | 2014-09-25 |
| JP2016514375A (ja) | 2016-05-19 |
| US9583179B2 (en) | 2017-02-28 |
| US20150302919A1 (en) | 2015-10-22 |
| JP6309608B2 (ja) | 2018-04-11 |
| US20140269022A1 (en) | 2014-09-18 |
| JP2017085120A (ja) | 2017-05-18 |
| CN105144381A (zh) | 2015-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9171608B2 (en) | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods | |
| US9041448B2 (en) | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods | |
| US9754923B1 (en) | Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) | |
| TWI890138B (zh) | 堆疊fet標準單元架構 | |
| KR101588612B1 (ko) | 판독-우선 셀 구조들, 기입 드라이버들을 갖는 정적 랜덤 액세스 메모리들 (sram), 관련 시스템들, 및 방법들 | |
| US10146900B2 (en) | Hybrid diffusion standard library cells, and related systems and methods | |
| US11862640B2 (en) | Cross field effect transistor (XFET) library architecture power routing | |
| JP6147930B2 (ja) | 垂直メモリ構成要素を有するモノリシック3次元(3d)集積回路(ics)(3dic) | |
| TW202543446A (zh) | 利用頂側及背側資源的垂直電晶體單元結構 | |
| CN117999651A (zh) | 用于利用减小的接触栅极多晶硅间距和双高度单元来减小电压降的标准单元设计架构 | |
| US20140293682A1 (en) | Memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area, and related systems and methods | |
| TWI917087B (zh) | Sram巨集設計架構 | |
| US20260082953A1 (en) | Interconnects for complementary field-effect transistor (cfet) devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20151013 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| A302 | Request for accelerated examination | ||
| AMND | Amendment | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20151204 Comment text: Request for Examination of Application |
|
| PA0302 | Request for accelerated examination |
Patent event date: 20151204 Patent event code: PA03022R01D Comment text: Request for Accelerated Examination |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20151214 Patent event code: PE09021S01D |
|
| AMND | Amendment | ||
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20160520 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20151214 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |
|
| AMND | Amendment | ||
| PX0901 | Re-examination |
Patent event code: PX09011S01I Patent event date: 20160520 Comment text: Decision to Refuse Application Patent event code: PX09012R01I Patent event date: 20160314 Comment text: Amendment to Specification, etc. Patent event code: PX09012R01I Patent event date: 20151204 Comment text: Amendment to Specification, etc. |
|
| PX0601 | Decision of rejection after re-examination |
Comment text: Decision to Refuse Application Patent event code: PX06014S01D Patent event date: 20160921 Comment text: Amendment to Specification, etc. Patent event code: PX06012R01I Patent event date: 20160819 Comment text: Decision to Refuse Application Patent event code: PX06011S01I Patent event date: 20160520 Comment text: Amendment to Specification, etc. Patent event code: PX06012R01I Patent event date: 20160314 Comment text: Notification of reason for refusal Patent event code: PX06013S01I Patent event date: 20151214 Comment text: Amendment to Specification, etc. Patent event code: PX06012R01I Patent event date: 20151204 |
|
| A107 | Divisional application of patent | ||
| J201 | Request for trial against refusal decision | ||
| PA0104 | Divisional application for international application |
Comment text: Divisional Application for International Patent Patent event code: PA01041R01D Patent event date: 20161221 |
|
| PJ0201 | Trial against decision of rejection |
Patent event date: 20161221 Comment text: Request for Trial against Decision on Refusal Patent event code: PJ02012R01D Patent event date: 20160921 Comment text: Decision to Refuse Application Patent event code: PJ02011S01I Patent event date: 20160520 Comment text: Decision to Refuse Application Patent event code: PJ02011S01I Appeal kind category: Appeal against decision to decline refusal Appeal identifier: 2016101007148 Request date: 20161221 |
|
| J301 | Trial decision |
Free format text: TRIAL NUMBER: 2016101007148; TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20161221 Effective date: 20170426 |
|
| PJ1301 | Trial decision |
Patent event code: PJ13011S01D Patent event date: 20170426 Comment text: Trial Decision on Objection to Decision on Refusal Appeal kind category: Appeal against decision to decline refusal Request date: 20161221 Decision date: 20170426 Appeal identifier: 2016101007148 |