KR20080004356A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR20080004356A
KR20080004356A KR1020070065074A KR20070065074A KR20080004356A KR 20080004356 A KR20080004356 A KR 20080004356A KR 1020070065074 A KR1020070065074 A KR 1020070065074A KR 20070065074 A KR20070065074 A KR 20070065074A KR 20080004356 A KR20080004356 A KR 20080004356A
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KR
South Korea
Prior art keywords
wiring board
chip
semiconductor device
memory chip
main surface
Prior art date
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Withdrawn
Application number
KR1020070065074A
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English (en)
Korean (ko)
Inventor
도시히꼬 아끼바
다까히로 나이또
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
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Publication of KR20080004356A publication Critical patent/KR20080004356A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
KR1020070065074A 2006-07-04 2007-06-29 반도체 장치 및 그 제조 방법 Withdrawn KR20080004356A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2006-00183993 2006-07-04
JP2006183993A JP5259059B2 (ja) 2006-07-04 2006-07-04 半導体装置

Publications (1)

Publication Number Publication Date
KR20080004356A true KR20080004356A (ko) 2008-01-09

Family

ID=38918408

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070065074A Withdrawn KR20080004356A (ko) 2006-07-04 2007-06-29 반도체 장치 및 그 제조 방법

Country Status (5)

Country Link
US (1) US7847413B2 (enExample)
JP (1) JP5259059B2 (enExample)
KR (1) KR20080004356A (enExample)
CN (1) CN101101909A (enExample)
TW (1) TW200816435A (enExample)

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KR20130000319A (ko) * 2011-06-22 2013-01-02 스태츠 칩팩, 엘티디. 수직 상호연결들을 갖는 집적 회로 패키징 시스템 및 그 제조 방법
US8928132B2 (en) 2011-02-17 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package

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JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
SG166773A1 (en) * 2007-04-24 2010-12-29 United Test & Assembly Ct Lt Bump on via-packaging and methodologies
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
US8258015B2 (en) * 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US8304869B2 (en) * 2008-08-01 2012-11-06 Stats Chippac Ltd. Fan-in interposer on lead frame for an integrated circuit package on package system
JP5140565B2 (ja) * 2008-11-28 2013-02-06 三洋電機株式会社 素子搭載用基板、半導体モジュール、および携帯機器
US8097956B2 (en) * 2009-03-12 2012-01-17 Apple Inc. Flexible packaging for chip-on-chip and package-on-package technologies
JP2010238995A (ja) * 2009-03-31 2010-10-21 Sanyo Electric Co Ltd 半導体モジュールおよびこれを搭載したカメラモジュール
JP5521424B2 (ja) * 2009-07-28 2014-06-11 セイコーエプソン株式会社 集積回路装置、電子機器及び電子機器の製造方法
US8064202B2 (en) * 2010-02-24 2011-11-22 Monolithic Power Systems, Inc. Sandwich structure with double-sided cooling and EMI shielding
KR101686199B1 (ko) 2010-03-26 2016-12-14 삼성전자주식회사 반도체 패키지 구조물
CN102157394A (zh) * 2011-03-22 2011-08-17 南通富士通微电子股份有限公司 高密度系统级封装方法
KR20130007049A (ko) * 2011-06-28 2013-01-18 삼성전자주식회사 쓰루 실리콘 비아를 이용한 패키지 온 패키지
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
KR101797079B1 (ko) * 2011-12-30 2017-11-14 삼성전자 주식회사 Ｐｏｐ 구조의 반도체 패키지
US8742597B2 (en) 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
CN103579128B (zh) * 2012-07-26 2016-12-21 碁鼎科技秦皇岛有限公司 芯片封装基板、芯片封装结构及其制作方法
US9368477B2 (en) * 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8860202B2 (en) * 2012-08-29 2014-10-14 Macronix International Co., Ltd. Chip stack structure and manufacturing method thereof
JP5996500B2 (ja) * 2013-09-11 2016-09-21 株式会社東芝 半導体装置および記憶装置
US9281284B2 (en) * 2014-06-20 2016-03-08 Freescale Semiconductor Inc. System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
JP6543129B2 (ja) * 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
KR102438753B1 (ko) * 2015-10-01 2022-09-01 에스케이하이닉스 주식회사 반도체 장치
WO2017122449A1 (ja) * 2016-01-15 2017-07-20 ソニー株式会社 半導体装置および撮像装置
US11487445B2 (en) * 2016-11-22 2022-11-01 Intel Corporation Programmable integrated circuit with stacked memory die for storing configuration data
CN108400117A (zh) * 2017-02-06 2018-08-14 钰桥半导体股份有限公司 三维整合的散热增益型半导体组件及其制作方法
US10475770B2 (en) * 2017-02-28 2019-11-12 Amkor Technology, Inc. Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof
JP6679528B2 (ja) * 2017-03-22 2020-04-15 キオクシア株式会社 半導体装置
TWI678747B (zh) * 2018-10-01 2019-12-01 點序科技股份有限公司 測試裝置及其晶片承載板
JP2020150145A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
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JP2004281920A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
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JP3858854B2 (ja) 2003-06-24 2006-12-20 富士通株式会社 積層型半導体装置
JP2006032379A (ja) * 2004-07-12 2006-02-02 Akita Denshi Systems:Kk 積層半導体装置及びその製造方法
JP4199724B2 (ja) * 2004-12-03 2008-12-17 エルピーダメモリ株式会社 積層型半導体パッケージ
JP4408090B2 (ja) * 2005-03-01 2010-02-03 パナソニック株式会社 部品内蔵モジュールの製造方法
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Publication number Priority date Publication date Assignee Title
US8928132B2 (en) 2011-02-17 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package
KR20130000319A (ko) * 2011-06-22 2013-01-02 스태츠 칩팩, 엘티디. 수직 상호연결들을 갖는 집적 회로 패키징 시스템 및 그 제조 방법

Also Published As

Publication number Publication date
JP2008016519A (ja) 2008-01-24
TW200816435A (en) 2008-04-01
US20080006947A1 (en) 2008-01-10
JP5259059B2 (ja) 2013-08-07
US7847413B2 (en) 2010-12-07
CN101101909A (zh) 2008-01-09

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