KR20070107180A - 기판 강화 방법 및 그 결과물인 디바이스 - Google Patents

기판 강화 방법 및 그 결과물인 디바이스 Download PDF

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Publication number
KR20070107180A
KR20070107180A KR1020077022337A KR20077022337A KR20070107180A KR 20070107180 A KR20070107180 A KR 20070107180A KR 1020077022337 A KR1020077022337 A KR 1020077022337A KR 20077022337 A KR20077022337 A KR 20077022337A KR 20070107180 A KR20070107180 A KR 20070107180A
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KR
South Korea
Prior art keywords
substrate
predetermined thickness
cleaving
handle
donor
Prior art date
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Ceased
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KR1020077022337A
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English (en)
Korean (ko)
Inventor
프란코이스 제이 헨리
해리 로버트 커크
제임스 앤드류 설리반
Original Assignee
실리콘 제너시스 코포레이션
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Publication of KR20070107180A publication Critical patent/KR20070107180A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Laminated Bodies (AREA)
  • Electroluminescent Light Sources (AREA)
KR1020077022337A 2005-02-28 2006-02-24 기판 강화 방법 및 그 결과물인 디바이스 Ceased KR20070107180A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US65726205P 2005-02-28 2005-02-28
US65755805P 2005-02-28 2005-02-28
US60/657,558 2005-02-28
US60/657,262 2005-02-28

Publications (1)

Publication Number Publication Date
KR20070107180A true KR20070107180A (ko) 2007-11-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077022337A Ceased KR20070107180A (ko) 2005-02-28 2006-02-24 기판 강화 방법 및 그 결과물인 디바이스

Country Status (7)

Country Link
US (2) US8241996B2 (https=)
EP (1) EP1894234B1 (https=)
JP (2) JP2008532317A (https=)
KR (1) KR20070107180A (https=)
CN (1) CN101248519B (https=)
TW (1) TWI428956B (https=)
WO (1) WO2006093817A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101331469B1 (ko) * 2012-04-23 2013-11-21 국방과학연구소 양극 접합된 실리콘/유리 기판 결합체의 휨 저감방법
KR20160044479A (ko) * 2013-08-21 2016-04-25 신에쯔 한도타이 가부시키가이샤 접합웨이퍼의 제조방법

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TW200633001A (en) 2006-09-16
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US20060211219A1 (en) 2006-09-21
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US7772088B2 (en) 2010-08-10
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