KR20060127190A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR20060127190A
KR20060127190A KR1020067018704A KR20067018704A KR20060127190A KR 20060127190 A KR20060127190 A KR 20060127190A KR 1020067018704 A KR1020067018704 A KR 1020067018704A KR 20067018704 A KR20067018704 A KR 20067018704A KR 20060127190 A KR20060127190 A KR 20060127190A
Authority
KR
South Korea
Prior art keywords
power supply
esd protection
bonding pad
terminal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020067018704A
Other languages
English (en)
Korean (ko)
Inventor
다쿠미 가토
히데오 하라
Original Assignee
로무 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 로무 가부시키가이샤 filed Critical 로무 가부시키가이샤
Publication of KR20060127190A publication Critical patent/KR20060127190A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Semiconductor Integrated Circuits (AREA)
KR1020067018704A 2004-03-12 2005-03-11 반도체 장치 Withdrawn KR20060127190A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004070380 2004-03-12
JPJP-P-2004-00070380 2004-03-12

Publications (1)

Publication Number Publication Date
KR20060127190A true KR20060127190A (ko) 2006-12-11

Family

ID=34975862

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067018704A Withdrawn KR20060127190A (ko) 2004-03-12 2005-03-11 반도체 장치

Country Status (6)

Country Link
US (1) US20070158817A1 (enExample)
JP (1) JP4978998B2 (enExample)
KR (1) KR20060127190A (enExample)
CN (1) CN1930676B (enExample)
TW (1) TW200535963A (enExample)
WO (1) WO2005088701A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103274A (ja) * 2008-10-23 2010-05-06 Nec Electronics Corp 半導体パッケージ
JP5071465B2 (ja) * 2009-11-11 2012-11-14 株式会社村田製作所 高周波モジュール
JP5703103B2 (ja) * 2011-04-13 2015-04-15 株式会社東芝 半導体装置及びｄｃ−ｄｃコンバータ
JP6266444B2 (ja) 2014-06-20 2018-01-24 ザインエレクトロニクス株式会社 半導体装置
JP6514949B2 (ja) * 2015-04-23 2019-05-15 日立オートモティブシステムズ株式会社 オンチップノイズ保護回路を有する半導体チップ
CN105977938B (zh) 2016-06-17 2018-09-25 中国电子科技集团公司第二十四研究所 芯片esd保护电路
KR102866504B1 (ko) * 2019-05-20 2025-10-01 삼성디스플레이 주식회사 표시 장치 및 그것을 포함하는 전자 장치
CN117546281A (zh) * 2021-07-16 2024-02-09 罗姆股份有限公司 I/o电路、半导体装置、单元库和设计半导体装置的电路的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065705B2 (ja) * 1989-08-11 1994-01-19 株式会社東芝 半導体集積回路装置
US5430595A (en) * 1993-10-15 1995-07-04 Intel Corporation Electrostatic discharge protection circuit
JP2616721B2 (ja) * 1994-11-22 1997-06-04 日本電気株式会社 半導体集積回路装置
US5781388A (en) * 1996-09-03 1998-07-14 Motorola, Inc. Non-breakdown triggered electrostatic discharge protection circuit for an integrated circuit and method therefor
JP2870514B2 (ja) * 1996-12-16 1999-03-17 日本電気株式会社 半導体装置
US6078068A (en) * 1998-07-15 2000-06-20 Adaptec, Inc. Electrostatic discharge protection bus/die edge seal
US6204537B1 (en) * 1998-10-01 2001-03-20 Micron Technology, Inc. ESD protection scheme
US6445039B1 (en) * 1998-11-12 2002-09-03 Broadcom Corporation System and method for ESD Protection
JP2000208718A (ja) * 1999-01-19 2000-07-28 Matsushita Electric Ind Co Ltd 半導体装置
JP3302665B2 (ja) * 1999-10-25 2002-07-15 ローム株式会社 半導体集積回路装置
US6624998B2 (en) * 2000-01-24 2003-09-23 Medtronic, Inc. Electrostatic discharge protection scheme in low potential drop environments
JP2001298157A (ja) * 2000-04-14 2001-10-26 Nec Corp 保護回路及びこれを搭載した半導体集積回路
US6355960B1 (en) * 2000-09-18 2002-03-12 Vanguard International Semiconductor Corporation ESD protection for open drain I/O pad in integrated circuit with parasitic field FET devices
JP2002110919A (ja) * 2000-09-27 2002-04-12 Toshiba Corp 静電破壊保護回路
TWI222208B (en) * 2002-05-29 2004-10-11 Sanyo Electric Co Semiconductor integrated circuit device
US6798022B1 (en) * 2003-03-11 2004-09-28 Oki Electric Industry Co., Ltd. Semiconductor device with improved protection from electrostatic discharge
JP3732834B2 (ja) * 2003-04-17 2006-01-11 株式会社東芝 入力保護回路
JP3949647B2 (ja) * 2003-12-04 2007-07-25 Ｎｅｃエレクトロニクス株式会社 半導体集積回路装置
US7202114B2 (en) * 2004-01-13 2007-04-10 Intersil Americas Inc. On-chip structure for electrostatic discharge (ESD) protection
JP2005317830A (ja) * 2004-04-30 2005-11-10 Elpida Memory Inc 半導体装置、マルチチップパッケージ、およびワイヤボンディング方法
JP2006303110A (ja) * 2005-04-19 2006-11-02 Nec Electronics Corp 半導体装置
US7463466B2 (en) * 2005-10-24 2008-12-09 United Microelectronics Corp. Integrated circuit with ESD protection circuit

Also Published As

Publication number Publication date
JP4978998B2 (ja) 2012-07-18
CN1930676A (zh) 2007-03-14
WO2005088701A1 (ja) 2005-09-22
JPWO2005088701A1 (ja) 2008-01-31
CN1930676B (zh) 2010-06-16
US20070158817A1 (en) 2007-07-12
TWI355016B (enExample) 2011-12-21
TW200535963A (en) 2005-11-01

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20060912

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid