KR20050062442A - 반도체 스택을 구비한 반도체 모듈 및 그 생성 방법 - Google Patents
반도체 스택을 구비한 반도체 모듈 및 그 생성 방법 Download PDFInfo
- Publication number
- KR20050062442A KR20050062442A KR1020040108065A KR20040108065A KR20050062442A KR 20050062442 A KR20050062442 A KR 20050062442A KR 1020040108065 A KR1020040108065 A KR 1020040108065A KR 20040108065 A KR20040108065 A KR 20040108065A KR 20050062442 A KR20050062442 A KR 20050062442A
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- Prior art keywords
- intervening
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 330
- 238000000034 method Methods 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 61
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- LNUFLCYMSVYYNW-ZPJMAFJPSA-N [(2r,3r,4s,5r,6r)-2-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[[(3s,5s,8r,9s,10s,13r,14s,17r)-10,13-dimethyl-17-[(2r)-6-methylheptan-2-yl]-2,3,4,5,6,7,8,9,11,12,14,15,16,17-tetradecahydro-1h-cyclopenta[a]phenanthren-3-yl]oxy]-4,5-disulfo Chemical compound O([C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1C[C@@H]2CC[C@H]3[C@@H]4CC[C@@H]([C@]4(CC[C@@H]3[C@@]2(C)CC1)C)[C@H](C)CCCC(C)C)[C@H]1O[C@H](COS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@H](OS(O)(=O)=O)[C@H]1OS(O)(=O)=O LNUFLCYMSVYYNW-ZPJMAFJPSA-N 0.000 claims description 13
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Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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Abstract
Description
Claims (17)
- 반도체 스택(10)을 구비한 반도체 모듈에 있어서,하나가 다른 하나 위에 배치된 반도체 구성요소(1, 2)들을 구비하고, 하나의 기본 반도체 구성요소(1)는, 상기 기본 반도체 구성요소(1)의 하부면(7) 상의 하부 개재 유닛(3)의 하부 외부 콘택 패드(5)들과 상기 기본 반도체 구성요소(1)의 상부면(8) 상의 상부 개재 유닛(4)의 상부 외부 콘택 패드(6)들을 가지는 두 개재 유닛(3, 4)들을 구비하며, 상기 두 개재 유닛(3, 4)들의 상기 외부 콘택 패드(5, 6)들은 상기 두 개재 유닛(3, 4)의 에지 영역(14, 15)들에서 본딩면(12, 13)들간의 본딩 연결부(9)들을 통해 전기적으로 접속되고, 상기 하부 개재 유닛(3)의 상기 외부 콘택 패드(5, 6)들은 상기 반도체 모듈(10)의 외부 콘택(17)들을 구비하며, 상기 상부 개재 유닛(4)의 상기 외부 콘택 패드(6)들은 스택된 반도체 구성요소(2)의 외부 콘택 패드(6)들과 핏팅되는 것을 특징으로 하는 반도체 모듈.
- 제 1항에 있어서,상기 본딩 연결부(9)들은 플라스틱 하우징 컴파운드(18) 내에 임베딩되는 것을 특징으로 하는 반도체 모듈.
- 제 1항 또는 제 2항에 있어서,상기 기본 반도체 구성요소(1)는 상기 두 개재 유닛(3, 4) 사이에 반도체 칩(19)을 가지는 것을 특징으로 하는 반도체 모듈.
- 제 1항 내지 제 3항 중 어느 한 항에 있어서,상기 기본 반도체 구성요소(1)는 상기 두 개재 유닛(3, 4)들 사이에 스페이서(22)를 구비하고, 상기 스페이서(22)는 하우징을 형성하며, 상기 스페이서(22)는 상기 상부 개재 유닛(4)의 하부면(24) 상으로 캐스팅되고, 상기 스페이서(22)는 상기 하부 개재 유닛(3) 상의 상부면(25)에 접착제로 본딩되는 것을 특징으로 하는 반도체 모듈.
- 제 4항에 있어서,상기 스페이서(22)는 상기 기본 반도체 구성요소(1)의 상기 반도체 칩(19)을 그 에지면(27, 28) 상에서 둘러싸는 것을 특징으로 하는 반도체 모듈.
- 제 4항에 있어서,상기 기본 반도체 구성요소(1)는 상기 반도체 칩(19)과 상기 스페이서(22) 사이에 공동(32)을 구비하는 것을 특징으로 하는 반도체 모듈.
- 제 4항에 있어서,상기 스페이서(22)는 상기 기본 반도체 구성요소(1)의 상기 반도체 칩(19)을 대향하는 두 에지면(27, 28) 상에서 둘러싸는 것을 특징으로 하는 반도체 모듈.
- 제 4항에 있어서,플라스틱 하우징 컴파운드(18)가, 상기 스페이서(22)와 상기 기본 반도체 구성요소(1)의 상기 반도체 칩(19) 사이에 배치되는 것을 특징으로 하는 반도체 모듈.
- 제 1항 내지 제 8항 중 어느 한 항에 있어서,상기 기본 반도체 구성요소(1)는 상기 두 개재 유닛(3, 4) 사이에 반도체 칩(49)을 구비하고, 상기 반도체 칩(49)의 후방면(13)은 상기 하부 개재 유닛(3) 상에 배치되는 한편, 그 활성 상부면(34) 상의 그 콘택 패드(35)들은 상기 하부 개재 유닛(3)의 상기 상부면(25) 상의 개재 구조체(37)의 본딩면들에 대해 본딩 연결부(36)들을 통해 전기적으로 접속되며, 상기 반도체 칩(49) 및 상기 반도체 칩(49)의 상기 본딩 연결부(36)들은 플라스틱 하우징(38) 내에 임베딩되어, 그 상부면(42) 위에 상기 기본 반도체 구성요소(1)의 상기 상부 개재 유닛(4)이 배치되는 것을 특징으로 하는 반도체 모듈.
- 제 9항에 있어서,상기 하부 개재 유닛(3)은 절연 마운팅 보드(43)를 구비하여, 그 상부면(25) 위에 개재 구조체(37)가 배치되고, 이는 상기 반도체 칩(49)의 본딩 연결부(36)들에 대하여 그 에지면들 상에 본딩면(44)들을 가지며, 개재 라인들은 상기 본딩면(44)들로부터 상기 반도체 칩(49)의 후방면(33) 밑에 있는 상기 마운팅 보드(43) 상의 비아(45)들까지 연장되고, 상기 비아(45)들은 상기 하부 개재 유닛(3) 상의 상기 외부 콘택 패드(5)들에 전기적으로 접속되는 것을 특징으로 하는 반도체 모듈.
- 제 1항 내지 제 10항 중 어느 한 항에 있어서,상기 기본 반도체 구성요소(1)는 상기 두 개재 유닛(3, 4)들 사이에 플립칩 콘택(46)들을 구비한 반도체 칩(19, 29, 39)을 구비하고, 상기 플립칩 콘택(46)들은 상기 하부 개재 유닛(3)의 상부면(25) 상에서 개재 구조체(37)의 콘택 연결 패드(47)들에 전기적으로 접속되는 것을 특징으로 하는 반도체 모듈.
- 제 11항에 있어서,상기 하부 개재 유닛(3)은 절연 마운팅 보드(43)를 구비하여, 그 상부면(25) 위에 개재 구조체(38)가 배치되고, 이는 상기 반도체 칩(19, 29, 39) 상의 플립칩 콘택(46)들을 위한 콘택 연결 패드(47)들을 구비하고, 그 에지 영역(15)들에서 본딩면(13)들에 대한 그리고 상기 마운팅 보드(43) 상의 비아(45)들에 대한 개재 라인들을 구비하며, 상기 비아(45)들은 상기 하부 개재 유닛(3) 상의 상기 외부 콘택 패드(5)들에 전기적으로 접속되는 것을 특징으로 하는 반도체 모듈.
- 2 이상의 개재 위치(54)들을 갖는 개재 보드에 있어서,상기 개재 위치들은 로우 및 컬럼들로 배치되며, 상기 개재 보드(51)의 상부면(26) 상에 상기 개재 위치(54)들에서의 외부 콘택 패드(6)들을 구비한 금속성 개재 구조체(37)들을 구비하고, 상기 개재 보드(51)는 간격 구조체(52)를 구비하며, 상기 간격 구조체는 하우징을 형성하고, 캐스트-온되고 상승된 리브(53)들 및/또는 상기 상부면(26)에 대향하는 하부면(24) 상의 상승된 그리드 구조체(58)로 이루어지며, 이들은 하우징들을 형성하고 상기 개재 위치(54)들의 에지 영역(14, 15) 내에 배치되는 스페이서(22)의 형태인 것을 특징으로 하는 개재 보드.
- 반도체 모듈(10)의 기본 반도체 구성요소(1)에 대해 로우(54) 및 컬럼(56)들로 배치되는 2 이상의 개재 위치(54)들을 구비한 개재 보드(51)로 형성되는 상부 개재 유닛(4)의 생성 방법에 있어서,- 상부면 상에 금속-코팅되는 마운팅 보드(43)를 제공하는 단계,- 상기 개재 위치(54)들의 에지 영역(14)들에서 본딩면(12)들에 대한 개재 라인들 및 외부 콘택 패드(6)들을 구비한 상기 개재 위치(54)들에서 개재 구조체들을 형성하기 위하여 상기 마운팅 보드(43) 상에 금속 코팅을 구조화하는 단계,- 하우징을 형성하고 캐스트-온되고 상승된 리브(53)들 및/또는 상부면(26)에 대향하는 하부면(24) 상의 상승된 그리드 구조체(58)로 이루어지는 간격 구조체(52)를 핏팅하는 단계를 포함하되, 상기 리브(53)들 및/또는 상기 그리드 구조체(58)는 하우징(들)을 형성하는 스페이서(들)로서 구조화되고, 상기 개재 위치(54)들의 에지 영역(14)들에 배치되며,- 반도체 모듈(10)의 기본 반도체 구성요소(1)에 대한 상부 개재 유닛(4)들을 형성하기 위하여 상기 개재 보드(51)를 분리시키는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 14항에 있어서,하우징을 형성하는 간격 구조체(52)는 플라스틱 하우징 컴파운드(18)의 인젝션 몰딩 또는 다이캐스팅에 의하여 핏팅되는 것을 특징으로 하는 방법.
- 반도체 모듈(10)용 기본 반도체 구성요소(1)들의 생성 방법에 있어서,- 제 14항 또는 제 15항에 따라 상부 개재 유닛(4)들을 생성하는 단계,- 2 이상의 반도체 모듈 위치(50)들을 갖는 하부 개재 보드(57)를 생성하는 단계를 포함하되, 상기 하부 개재 보드는 그 상부면(25) 상에 개재 구조체(37)들과, 그 하부면(23) 상에 상기 반도체 모듈 위치(50)들 내의 외부 콘택 패드(5)들을 구비하며,- 상기 반도체 모듈 위치(50)들에서 상기 하부 개재 보드(57)의 상부면에 반도체 칩(19)들을 핏팅하는 단계,- 상기 하부 개재 보드(57)의 대응하는 개재 구조체(37)들에 상기 반도체 칩(19)들을 연결시키는 단계,상기 하부 개재 보드(57)에 상부 개재 유닛(4)들을 핏팅하는 단계를 포함하되, 상기 상부 개재 유닛(4)들 상에 하우징(들)을 형성하는 상기 간격 구조체(52)들은 상기 하부 개재 보드(57)의 상기 상부면(25) 상에 접착제로 본딩되고, 상기 반도체 칩(19)들은 하우징(들)을 형성하는 스페이서(22)들에 의해 둘러싸여지며,- 상기 반도체 모듈 위치(50)들에서 상기 하부 개재 보드(57)의 상기 개재 구조체(37) 및 상부 개재 유닛(4)들 사이에 본딩 연결부(9)들을 생성하는 단계,- 상기 상부 개재 유닛(4)들의 상기 개재 구조체(37)와 상기 하부 개재 보드(57)의 상기 개재 구조체(37)들 사이에 본딩 연결부(9)들을 생성하는 단계,- 플라스틱 하우징 컴파운드(18) 내에 상기 본딩 연결부(9)들을 임베딩하는 단계,- 기본 반도체 구성요소(1)들을 형성하기 위하여 상기 반도체 모듈 위치들에서 상기 하부 개재 보드(57)를 분리시키는 단계를 포함하는 것을 특징으로 하는 방법.
- 반도체 모듈(10)들의 생성 방법에 있어서,- 제 16항에 따라 기본 반도체 구성요소(1)들을 생성하는 단계,- 상기 기본 반도체 구성요소(1)들의 상부 개재 유닛(4)들 상에 스택된 반도체 구성요소(2)들을 핏팅하는 단계를 포함하되, 상기 기본 반도체 구성요소(1)들의 상부 외부 콘택 패드(5)들은 스택된 반도체 구성요소(2)의 외부 콘택(16)들에 연결되는 것을 특징으로 하는 방법.
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US145039A (en) * | 1873-11-25 | Improvement in caissons | ||
KR20000056804A (ko) * | 1999-02-26 | 2000-09-15 | 윤종용 | 적층형 볼 그리드 어레이 패키지 |
US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
US6404043B1 (en) * | 2000-06-21 | 2002-06-11 | Dense-Pac Microsystems, Inc. | Panel stacking of BGA devices to form three-dimensional modules |
JP2002343930A (ja) * | 2001-05-16 | 2002-11-29 | Fujitsu Ltd | 半導体装置 |
KR20030018204A (ko) * | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | 스페이서를 갖는 멀티 칩 패키지 |
US6787916B2 (en) * | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
TW556961U (en) * | 2002-12-31 | 2003-10-01 | Advanced Semiconductor Eng | Multi-chip stack flip-chip package |
US6861288B2 (en) * | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
JP3917946B2 (ja) * | 2003-03-11 | 2007-05-23 | 富士通株式会社 | 積層型半導体装置 |
KR100546374B1 (ko) * | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법 |
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KR100727889B1 (ko) | 2007-06-14 |
US20050133932A1 (en) | 2005-06-23 |
DE10360708A1 (de) | 2005-07-28 |
DE10360708B4 (de) | 2008-04-10 |
US7456495B2 (en) | 2008-11-25 |
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