KR20040102187A - 실리사이드화를 이용한 금속 게이트 전극 및 그 형성 방법 - Google Patents

실리사이드화를 이용한 금속 게이트 전극 및 그 형성 방법 Download PDF

Info

Publication number
KR20040102187A
KR20040102187A KR10-2004-7017334A KR20047017334A KR20040102187A KR 20040102187 A KR20040102187 A KR 20040102187A KR 20047017334 A KR20047017334 A KR 20047017334A KR 20040102187 A KR20040102187 A KR 20040102187A
Authority
KR
South Korea
Prior art keywords
polysilicon
gate
dielectric
polysilicon body
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR10-2004-7017334A
Other languages
English (en)
Korean (ko)
Inventor
마스자라위톨드피
크리보카픽조란
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20040102187A publication Critical patent/KR20040102187A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
KR10-2004-7017334A 2002-04-30 2003-04-28 실리사이드화를 이용한 금속 게이트 전극 및 그 형성 방법 Ceased KR20040102187A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/135,227 US6599831B1 (en) 2002-04-30 2002-04-30 Metal gate electrode using silicidation and method of formation thereof
US10/135,227 2002-04-30
PCT/US2003/012958 WO2003094243A1 (en) 2002-04-30 2003-04-28 Metal gate electrode using silicidation and method of formation thereof

Publications (1)

Publication Number Publication Date
KR20040102187A true KR20040102187A (ko) 2004-12-03

Family

ID=27610948

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2004-7017334A Ceased KR20040102187A (ko) 2002-04-30 2003-04-28 실리사이드화를 이용한 금속 게이트 전극 및 그 형성 방법

Country Status (8)

Country Link
US (2) US6599831B1 (enExample)
EP (1) EP1502305A1 (enExample)
JP (1) JP2005524243A (enExample)
KR (1) KR20040102187A (enExample)
CN (2) CN102157362B (enExample)
AU (1) AU2003231119A1 (enExample)
TW (1) TWI270935B (enExample)
WO (1) WO2003094243A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200116178A (ko) * 2019-03-08 2020-10-12 삼성전자주식회사 반도체 소자 및 그의 제조 방법

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
US7183182B2 (en) * 2003-09-24 2007-02-27 International Business Machines Corporation Method and apparatus for fabricating CMOS field effect transistors
JP4011024B2 (ja) * 2004-01-30 2007-11-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP4521597B2 (ja) * 2004-02-10 2010-08-11 ルネサスエレクトロニクス株式会社 半導体記憶装置およびその製造方法
US7056782B2 (en) * 2004-02-25 2006-06-06 International Business Machines Corporation CMOS silicide metal gate integration
JP3998665B2 (ja) * 2004-06-16 2007-10-31 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2006013270A (ja) * 2004-06-29 2006-01-12 Renesas Technology Corp 半導体装置およびその製造方法
KR100558011B1 (ko) * 2004-07-12 2006-03-06 삼성전자주식회사 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JP2006108355A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
KR100593452B1 (ko) * 2005-02-01 2006-06-28 삼성전자주식회사 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JP2006245417A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 半導体装置およびその製造方法
WO2006098369A1 (ja) * 2005-03-15 2006-09-21 Nec Corporation 半導体装置の製造方法及び半導体装置
US20060258074A1 (en) * 2005-05-12 2006-11-16 Texas Instruments Incorporated Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows
JP2006339324A (ja) * 2005-06-01 2006-12-14 Fujitsu Ltd 半導体装置の製造方法
JP2006339441A (ja) * 2005-06-02 2006-12-14 Fujitsu Ltd 半導体装置の製造方法
EP1744351A3 (en) * 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
JP2007027727A (ja) * 2005-07-11 2007-02-01 Interuniv Micro Electronica Centrum Vzw フルシリサイド化ゲートｍｏｓｆｅｔの形成方法及び該方法により得られるデバイス
KR100646937B1 (ko) 2005-08-22 2006-11-23 삼성에스디아이 주식회사 다결정 실리콘 박막트랜지스터 및 그 제조방법
JP2007173347A (ja) * 2005-12-20 2007-07-05 Renesas Technology Corp 半導体装置及びその製造方法
JPWO2007077814A1 (ja) * 2006-01-06 2009-06-11 日本電気株式会社 半導体装置及びその製造方法
JP2007251030A (ja) * 2006-03-17 2007-09-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7491643B2 (en) * 2006-05-24 2009-02-17 International Business Machines Corporation Method and structure for reducing contact resistance between silicide contact and overlying metallization
US7297618B1 (en) 2006-07-28 2007-11-20 International Business Machines Corporation Fully silicided gate electrodes and method of making the same
JPWO2008035490A1 (ja) * 2006-09-20 2010-01-28 日本電気株式会社 半導体装置およびその製造方法
WO2008065908A1 (fr) * 2006-11-29 2008-06-05 Phyzchemix Corporation Procédé de formation d'un film de composé d'élément métallique du groupe iv et procédé de fabrication d'un dispositif semi-conducteur
US7727842B2 (en) * 2007-04-27 2010-06-01 Texas Instruments Incorporated Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
JP2009026997A (ja) * 2007-07-20 2009-02-05 Renesas Technology Corp 半導体装置およびその製造方法
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits
CN101981688B (zh) * 2008-04-02 2014-04-02 Imec公司 制造半导体器件的方法以及半导体器件
CN101562131B (zh) * 2008-04-15 2012-04-18 和舰科技(苏州)有限公司 栅极结构的制造方法
US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
US9871035B2 (en) * 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with metal silicide blocking region and method of manufacturing the same
US9972694B2 (en) * 2015-10-20 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition methods and structures thereof

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7510903A (nl) * 1975-09-17 1977-03-21 Philips Nv Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze.
JPS59125650A (ja) * 1983-01-07 1984-07-20 Toshiba Corp 半導体装置の製造方法
US4450620A (en) * 1983-02-18 1984-05-29 Bell Telephone Laboratories, Incorporated Fabrication of MOS integrated circuit devices
JPS616867A (ja) * 1984-06-20 1986-01-13 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4755865A (en) * 1986-01-21 1988-07-05 Motorola Inc. Means for stabilizing polycrystalline semiconductor layers
US4746964A (en) * 1986-08-28 1988-05-24 Fairchild Semiconductor Corporation Modification of properties of p-type dopants with other p-type dopants
US5237196A (en) * 1987-04-14 1993-08-17 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JPH01243549A (ja) * 1988-03-25 1989-09-28 Seiko Epson Corp 半導体装置
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5767558A (en) * 1996-05-10 1998-06-16 Integrated Device Technology, Inc. Structures for preventing gate oxide degradation
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US5851891A (en) * 1997-04-21 1998-12-22 Advanced Micro Devices, Inc. IGFET method of forming with silicide contact on ultra-thin gate
US6117761A (en) * 1997-08-23 2000-09-12 Micron Technology, Inc. Self-aligned silicide strap connection of polysilicon layers
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
JPH11284179A (ja) * 1998-03-30 1999-10-15 Sony Corp 半導体装置およびその製造方法
US6091123A (en) * 1998-06-08 2000-07-18 Advanced Micro Devices Self-aligned SOI device with body contact and NiSi2 gate
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6451644B1 (en) * 1998-11-06 2002-09-17 Advanced Micro Devices, Inc. Method of providing a gate conductor with high dopant activation
US6228724B1 (en) * 1999-01-28 2001-05-08 Advanced Mirco Devices Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby
JP2000252462A (ja) * 1999-03-01 2000-09-14 Toshiba Corp Ｍｉｓ型半導体装置及びその製造方法
US6281559B1 (en) * 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6245692B1 (en) * 1999-11-23 2001-06-12 Agere Systems Guardian Corp. Method to selectively heat semiconductor wafers
US6365481B1 (en) * 2000-09-13 2002-04-02 Advanced Micro Devices, Inc. Isotropic resistor protect etch to aid in residue removal
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US6479383B1 (en) * 2002-02-05 2002-11-12 Chartered Semiconductor Manufacturing Ltd Method for selective removal of unreacted metal after silicidation
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
US6544829B1 (en) * 2002-09-20 2003-04-08 Lsi Logic Corporation Polysilicon gate salicidation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200116178A (ko) * 2019-03-08 2020-10-12 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US11948994B2 (en) 2019-03-08 2024-04-02 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
TWI270935B (en) 2007-01-11
US6599831B1 (en) 2003-07-29
CN102157362B (zh) 2012-05-16
CN102157362A (zh) 2011-08-17
US20030203609A1 (en) 2003-10-30
US6873030B2 (en) 2005-03-29
AU2003231119A1 (en) 2003-11-17
EP1502305A1 (en) 2005-02-02
JP2005524243A (ja) 2005-08-11
CN1729576A (zh) 2006-02-01
TW200403729A (en) 2004-03-01
WO2003094243A1 (en) 2003-11-13

Similar Documents

Publication Publication Date Title
KR20040102187A (ko) 실리사이드화를 이용한 금속 게이트 전극 및 그 형성 방법
US6921691B1 (en) Transistor with dopant-bearing metal in source and drain
KR100410574B1 (ko) 데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법
US9024384B2 (en) Indium, carbon and halogen doping for PMOS transistors
US6642119B1 (en) Silicide MOSFET architecture and method of manufacture
US5904517A (en) Ultra thin high K spacer material for use in transistor fabrication
KR19980029024A (ko) 모스펫 및 그 제조방법
JPH1079506A (ja) 半導体装置およびその製造方法
EP1068637A1 (en) Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6548363B1 (en) Method to reduce the gate induced drain leakage current in CMOS devices
US5844276A (en) CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
US5874343A (en) CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof
KR100574172B1 (ko) 반도체 소자의 제조방법
EP0535814A1 (en) Integrated circuit transistor structure and method
KR100333356B1 (ko) 반도체장치의 제조방법
KR100271801B1 (ko) 반도체장치의 제조방법
JP2003031683A (ja) 半導体装置およびその製造方法
US20030003620A1 (en) Semiconductor device and manufacturing method of the same
KR19980029591A (ko) 듀얼 게이트 씨모오스 트랜지스터의 제조방법
KR100588785B1 (ko) 반도체 소자 제조 방법
JP2001257343A (ja) 半導体集積回路装置
KR20000032450A (ko) 반도체 소자 제조방법
KR20020002879A (ko) 시모스(ｃｍｏｓ) 트랜지스터의 제조 방법
KR20040050117A (ko) 반도체 소자의 제조 방법
KR20050030996A (ko) 반도체 소자 제조 방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20041027

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
AMND Amendment
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20080428

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20100330

Patent event code: PE09021S01D

AMND Amendment
E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

Comment text: Final Notice of Reason for Refusal

Patent event date: 20101130

Patent event code: PE09021S02D

AMND Amendment
AMND Amendment
E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20111130

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20110916

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

Patent event date: 20101130

Comment text: Final Notice of Reason for Refusal

Patent event code: PE06011S02I

Patent event date: 20100330

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

Patent event date: 20120229

Comment text: Request for Trial against Decision on Refusal

Patent event code: PJ02012R01D

Patent event date: 20111130

Comment text: Decision to Refuse Application

Patent event code: PJ02011S01I

Appeal kind category: Appeal against decision to decline refusal

Decision date: 20130930

Appeal identifier: 2012101002218

Request date: 20120229

AMND Amendment
PB0901 Examination by re-examination before a trial

Comment text: Amendment to Specification, etc.

Patent event date: 20120330

Patent event code: PB09011R02I

Comment text: Request for Trial against Decision on Refusal

Patent event date: 20120229

Patent event code: PB09011R01I

Comment text: Amendment to Specification, etc.

Patent event date: 20111116

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20110331

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20100630

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20080428

Patent event code: PB09011R02I

B601 Maintenance of original decision after re-examination before a trial
PB0601 Maintenance of original decision after re-examination before a trial

Comment text: Report of Result of Re-examination before a Trial

Patent event code: PB06011S01D

Patent event date: 20120417

J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20120229

Effective date: 20130930

PJ1301 Trial decision

Patent event code: PJ13011S01D

Patent event date: 20130930

Comment text: Trial Decision on Objection to Decision on Refusal

Appeal kind category: Appeal against decision to decline refusal

Request date: 20120229

Decision date: 20130930

Appeal identifier: 2012101002218

J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

PJ2001 Appeal

Patent event date: 20130930

Comment text: Trial Decision on Objection to Decision on Refusal

Patent event code: PJ20011S01I

Appeal kind category: Appeal against decision to decline refusal

Decision date: 20140109

Appeal identifier: 2013201009539

Request date: 20131203

J122 Written withdrawal of action (patent court)
PJ1202 Withdrawal of action (patent court)

Patent event code: PJ12021R01D

Patent event date: 20140115

Comment text: Written Withdrawal of Action

Decision date: 20140109

Request date: 20131203

Appeal identifier: 2013201009539

Appeal kind category: Appeal against decision to decline refusal