KR102564880B1 - 다수의 리셋 레벨들을 갖는 동적 양자화기들 - Google Patents

다수의 리셋 레벨들을 갖는 동적 양자화기들 Download PDF

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KR102564880B1
KR102564880B1 KR1020197029140A KR20197029140A KR102564880B1 KR 102564880 B1 KR102564880 B1 KR 102564880B1 KR 1020197029140 A KR1020197029140 A KR 1020197029140A KR 20197029140 A KR20197029140 A KR 20197029140A KR 102564880 B1 KR102564880 B1 KR 102564880B1
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voltage
circuit
input
quantizer
signal
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KR20190123315A (ko
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제임스 허드너
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자일링크스 인코포레이티드
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
KR1020197029140A 2017-03-08 2018-02-14 다수의 리셋 레벨들을 갖는 동적 양자화기들 Active KR102564880B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/453,707 2017-03-08
US15/453,707 US9755655B1 (en) 2017-03-08 2017-03-08 Dynamic quantizers having multiple reset levels
PCT/US2018/018255 WO2018164818A1 (en) 2017-03-08 2018-02-14 Dynamic quantizers having multiple reset levels

Publications (2)

Publication Number Publication Date
KR20190123315A KR20190123315A (ko) 2019-10-31
KR102564880B1 true KR102564880B1 (ko) 2023-08-07

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US (1) US9755655B1 (enExample)
EP (1) EP3593452B1 (enExample)
JP (1) JP7274420B2 (enExample)
KR (1) KR102564880B1 (enExample)
CN (1) CN110521119B (enExample)
WO (1) WO2018164818A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102898523B1 (ko) 2024-11-19 2025-12-09 서강대학교산학협력단 아날로그-디지털 변환기

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107733432B (zh) * 2017-11-10 2019-09-03 中国电子科技集团公司第五十八研究所 高精度电荷域流水线adc共模电荷误差校准系统
CN107863964B (zh) * 2017-11-10 2019-09-24 中国电子科技集团公司第五十八研究所 可精确控制共模电荷量的全差分电荷传输电路
CN107863962B (zh) * 2017-11-10 2019-09-03 中国电子科技集团公司第五十八研究所 高精度电荷域流水线adc的电容适配误差校准系统
US10454463B1 (en) 2018-08-21 2019-10-22 Xilinx, Inc. Adaptable quantizers having dedicated supply voltage for tail device drivers
JPWO2021200415A1 (enExample) * 2020-03-30 2021-10-07
CN115885472A (zh) * 2020-07-24 2023-03-31 株式会社半导体能源研究所 半导体装置
US11670345B2 (en) 2021-02-05 2023-06-06 Samsung Electronics Co., Ltd. Sense amplifier including pre-amplifier circuit and memory device including same
KR20220139063A (ko) 2021-04-07 2022-10-14 에스케이하이닉스 주식회사 클럭 신호 처리 회로, 반도체 장치 및 반도체 시스템
US12348205B2 (en) 2021-04-23 2025-07-01 Samsung Electronics Co., Ltd. Amplifier circuit
US11973621B2 (en) 2021-12-17 2024-04-30 Samsung Display Co., Ltd. Power efficient slicer for decision feedback equalizer
US11664821B1 (en) * 2022-02-08 2023-05-30 SK Hynix Inc. Error floor performance of a bit flipping decoder through identifying unreliable check nodes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114970A (ja) * 1998-10-07 2000-04-21 Yozan Inc 比較回路およびアナログデジタル変換回路
WO2007072588A1 (ja) * 2005-12-20 2007-06-28 Matsushita Electric Industrial Co., Ltd. 比較器及びａ／ｄ変換器
JP2013187695A (ja) * 2012-03-07 2013-09-19 Sony Corp コンパレータおよびａｄ変換器

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821286A (en) * 1986-05-27 1989-04-11 American Telephone And Telegraph Company Quaternary signal regenerator
US6021172A (en) * 1994-01-28 2000-02-01 California Institute Of Technology Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter
JP2002076901A (ja) * 2000-08-30 2002-03-15 Matsushita Electric Ind Co Ltd Δ変調とδς変調を混合した方式の変調器，オーバーサンプリング型ｄ／ａ変換器およびａ／ｄ変換器
US6456215B1 (en) * 2000-11-29 2002-09-24 Raytheon Company Method and system for quantizing an input signal
US6392449B1 (en) * 2001-01-05 2002-05-21 National Semiconductor Corporation High-speed low-power low-offset hybrid comparator
US7288998B2 (en) * 2003-05-02 2007-10-30 Silicon Laboratories Inc. Voltage controlled clock synthesizer
US7420497B2 (en) * 2006-06-28 2008-09-02 Broadcom Corporation Low offset flash analog-to-digital converter
JP5412639B2 (ja) * 2008-10-31 2014-02-12 国立大学法人東京工業大学 比較器及びアナログデジタル変換器
TWI382669B (zh) * 2009-07-16 2013-01-11 Ralink Technology Corp 用於管線式類比數位轉換器之比較器及相關訊號取樣方法
US8040159B1 (en) * 2010-03-23 2011-10-18 Lattice Semiconductor Corporation Comparator with jitter mitigation
JP2011211371A (ja) * 2010-03-29 2011-10-20 Panasonic Corp 逐次比較型ａｄ変換器用クロック生成回路
TWI443969B (zh) * 2010-11-17 2014-07-01 Ind Tech Res Inst 以動態比較器為基礎的比較系統
JP2012227588A (ja) * 2011-04-15 2012-11-15 Fujitsu Semiconductor Ltd 比較回路及びアナログデジタル変換回路
US8692582B1 (en) * 2012-01-06 2014-04-08 Altera Corporation Latched comparator circuitry
JP5417470B2 (ja) * 2012-03-05 2014-02-12 株式会社半導体理工学研究センター ダイナミックコンパレータのためのオフセット電圧補正回路とそれを用いたダイナミックコンパレータ回路
CN102638268B (zh) * 2012-04-19 2015-02-18 北京工业大学 基于逐次比较量化器的三阶前馈Sigma-Delta调制器
US8730404B2 (en) * 2012-05-31 2014-05-20 Silicon Laboratories Inc. Providing a reset mechanism for a latch circuit
US9287862B2 (en) * 2013-12-26 2016-03-15 Texas Instruments Incorporated Bootstrapped sampling switch circuits and systems
CN104158545B (zh) * 2014-08-14 2017-04-05 电子科技大学 一种基于压控振荡器量化的逐次逼近寄存器型模数转换器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114970A (ja) * 1998-10-07 2000-04-21 Yozan Inc 比較回路およびアナログデジタル変換回路
WO2007072588A1 (ja) * 2005-12-20 2007-06-28 Matsushita Electric Industrial Co., Ltd. 比較器及びａ／ｄ変換器
JP2013187695A (ja) * 2012-03-07 2013-09-19 Sony Corp コンパレータおよびａｄ変換器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102898523B1 (ko) 2024-11-19 2025-12-09 서강대학교산학협력단 아날로그-디지털 변환기

Also Published As

Publication number Publication date
US9755655B1 (en) 2017-09-05
CN110521119B (zh) 2024-01-23
JP7274420B2 (ja) 2023-05-16
EP3593452B1 (en) 2021-03-31
JP2020510340A (ja) 2020-04-02
CN110521119A (zh) 2019-11-29
KR20190123315A (ko) 2019-10-31
WO2018164818A1 (en) 2018-09-13
EP3593452A1 (en) 2020-01-15

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