KR101846299B1 - 반도체 기판의 제조 방법 - Google Patents

반도체 기판의 제조 방법 Download PDF

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KR101846299B1
KR101846299B1 KR1020167003236A KR20167003236A KR101846299B1 KR 101846299 B1 KR101846299 B1 KR 101846299B1 KR 1020167003236 A KR1020167003236 A KR 1020167003236A KR 20167003236 A KR20167003236 A KR 20167003236A KR 101846299 B1 KR101846299 B1 KR 101846299B1
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amorphous layer
layer
substrate
amorphous
thickness
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KR20160040565A (ko
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코 이마오카
모토키 고바야시
히데츠구 우치다
쿠니아키 야기
타카미츠 가와하라
나오키 핫타
아키유키 미나미
토요카즈 사카타
토모아츠 마키노
히데키 다카기
유우이치 구라시마
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가부시키가이샤 사이콕스
고쿠리츠켄큐카이하츠호진 상교기쥬츠 소고켄큐쇼
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    • H01L21/2007
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H01L21/02065
    • H01L21/02167
    • H01L21/02592
    • H01L21/02598
    • H01L21/324
    • H01L29/1608
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/126Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
KR1020167003236A 2013-07-05 2014-07-03 반도체 기판의 제조 방법 Active KR101846299B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013142151A JP6061251B2 (ja) 2013-07-05 2013-07-05 半導体基板の製造方法
JPJP-P-2013-142151 2013-07-05
PCT/JP2014/067777 WO2015002266A1 (ja) 2013-07-05 2014-07-03 半導体基板の製造方法

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KR20160040565A KR20160040565A (ko) 2016-04-14
KR101846299B1 true KR101846299B1 (ko) 2018-05-18

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US (1) US9761479B2 (https=)
EP (1) EP3018696B8 (https=)
JP (1) JP6061251B2 (https=)
KR (1) KR101846299B1 (https=)
CN (1) CN105474354B (https=)
WO (1) WO2015002266A1 (https=)

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WO2015156381A1 (ja) 2014-04-10 2015-10-15 富士電機株式会社 半導体基板の処理方法及び該処理方法を用いる半導体装置の製造方法
JP2016139655A (ja) * 2015-01-26 2016-08-04 富士通株式会社 半導体装置及び半導体装置の製造方法
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JP6544166B2 (ja) * 2015-09-14 2019-07-17 信越化学工業株式会社 SiC複合基板の製造方法
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JP6582779B2 (ja) * 2015-09-15 2019-10-02 信越化学工業株式会社 SiC複合基板の製造方法
US10985204B2 (en) * 2016-02-16 2021-04-20 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces
JP6619874B2 (ja) 2016-04-05 2019-12-11 株式会社サイコックス 多結晶SiC基板およびその製造方法
CN107958839B (zh) * 2016-10-18 2020-09-29 上海新昇半导体科技有限公司 晶圆键合方法及其键合装置
EP3586356B1 (de) * 2017-02-21 2023-11-08 EV Group E. Thallner GmbH Verfahren zum bonden von substraten
WO2018159754A1 (ja) 2017-03-02 2018-09-07 信越化学工業株式会社 炭化珪素基板の製造方法及び炭化珪素基板
CN110495097B (zh) * 2017-03-27 2024-01-30 住友电气工业株式会社 层状体和saw器件
JP7061747B2 (ja) * 2017-07-10 2022-05-02 株式会社タムラ製作所 半導体基板、半導体素子、及び半導体基板の製造方法
US20190019472A1 (en) * 2017-07-13 2019-01-17 Vanguard International Semiconductor Corporation Display system and method for forming an output buffer of a source driver
JP6854516B2 (ja) * 2017-07-19 2021-04-07 株式会社テンシックス 化合物半導体基板及びその製造方法
KR102903523B1 (ko) * 2018-04-27 2025-12-23 도쿄엘렉트론가부시키가이샤 기판 처리 시스템 및 기판 처리 방법
JP2019210162A (ja) * 2018-05-31 2019-12-12 ローム株式会社 半導体基板構造体及びパワー半導体装置
JP2019210161A (ja) * 2018-05-31 2019-12-12 ローム株式会社 半導体基板構造体及びパワー半導体装置
JP7024668B2 (ja) * 2018-09-05 2022-02-24 株式会社Sumco Soiウェーハ及びその製造方法
DE102018132447B4 (de) * 2018-12-17 2022-10-13 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung
CN109986191A (zh) * 2019-04-15 2019-07-09 上海交通大学 一种应用于金属/高分子连接的表面处理方法
JP6737378B2 (ja) * 2019-05-09 2020-08-05 信越化学工業株式会社 SiC複合基板
CN114008871A (zh) * 2019-06-18 2022-02-01 大学共同利用机关法人自然科学研究机构 光学元件的制造方法及光学元件
WO2021245724A1 (ja) 2020-06-01 2021-12-09 三菱電機株式会社 複合基板、複合基板の製造方法、半導体装置および半導体装置の製造方法
JP7625248B2 (ja) * 2021-01-20 2025-02-03 国立研究開発法人理化学研究所 接合体の製造方法および接合体
JP2023061509A (ja) 2021-10-20 2023-05-02 株式会社サイコックス 多結晶炭化珪素基板の製造方法
JP2023068782A (ja) * 2021-11-04 2023-05-18 株式会社サイコックス 半導体基板とその製造方法
FR3134228B1 (fr) 2022-03-30 2025-05-02 Mersen France Gennevilliers Procede de fabrication de carbure de silicium polycristallin utilisable pour la fabrication de substrats de circuits integres, et carbure de silicium ainsi obtenu
JP2023178892A (ja) * 2022-06-06 2023-12-18 株式会社サイコックス 陰極、高速原子ビーム線源、接合基板の製造方法、および、陰極の再生方法
JP2024025064A (ja) 2022-08-10 2024-02-26 株式会社サイコックス SiC単結晶転写用複合基板、SiC単結晶転写用複合基板の製造方法、およびSiC接合基板の製造方法
JP2024073797A (ja) 2022-11-18 2024-05-30 株式会社サイコックス 研磨組成物
FR3146237A1 (fr) 2023-02-24 2024-08-30 Mersen France Gennevilliers Plaque en SiC polycristallin dopé à planéité et conductivité électrique améliorées, et procédé de fabrication d’une telle plaque
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JP2024169169A (ja) 2023-05-25 2024-12-05 住友金属鉱山株式会社 SiC半導体装置用基板、SiC接合基板、SiC多結晶基板およびSiC多結晶基板の製造方法
US20250308953A1 (en) * 2024-03-26 2025-10-02 Applied Materials, Inc. In-Line Validation of Substrate Bonding Surface

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091176A (ja) 1998-09-10 2000-03-31 Toyota Central Res & Dev Lab Inc 基板張り合わせ方法
US20030008475A1 (en) 1999-01-08 2003-01-09 Nathan W. Cheung Method for fabricating multi-layered substrates
JP2004503942A (ja) * 2000-06-16 2004-02-05 エス オー イ テク シリコン オン インシュレータ テクノロジース 基板製造方法及び該方法によって得られた基板
JP2005252550A (ja) * 2004-03-03 2005-09-15 Fujitsu Media Device Kk 接合基板、弾性表面波素子および弾性表面波デバイス
JP2009117533A (ja) * 2007-11-05 2009-05-28 Shin Etsu Chem Co Ltd 炭化珪素基板の製造方法
JP2010541230A (ja) 2007-09-27 2010-12-24 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ 基板とその一方の面上に堆積させた層とを含む構造体の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH05251292A (ja) * 1992-03-06 1993-09-28 Nec Corp 半導体装置の製造方法
JP2791429B2 (ja) 1996-09-18 1998-08-27 工業技術院長 シリコンウェハーの常温接合法
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
JP4450126B2 (ja) * 2000-01-21 2010-04-14 日新電機株式会社 シリコン系結晶薄膜の形成方法
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6497763B2 (en) * 2001-01-19 2002-12-24 The United States Of America As Represented By The Secretary Of The Navy Electronic device with composite substrate
AU2002307578A1 (en) * 2002-04-30 2003-12-02 Agency For Science Technology And Research A method of wafer/substrate bonding
JP4556158B2 (ja) * 2002-10-22 2010-10-06 株式会社Sumco 貼り合わせsoi基板の製造方法および半導体装置
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
JP4934966B2 (ja) * 2005-02-04 2012-05-23 株式会社Sumco Soi基板の製造方法
US7462552B2 (en) * 2005-05-23 2008-12-09 Ziptronix, Inc. Method of detachable direct bonding at low temperatures
JP2008263087A (ja) * 2007-04-12 2008-10-30 Shin Etsu Chem Co Ltd Soi基板の製造方法
US8871610B2 (en) * 2008-10-02 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
KR20120052160A (ko) * 2010-11-15 2012-05-23 엔지케이 인슐레이터 엘티디 복합 기판 및 복합 기판의 제조 방법
JP5712100B2 (ja) * 2011-09-29 2015-05-07 富士フイルム株式会社 反射防止フィルムの製造方法、反射防止フィルム、塗布組成物
JP5835344B2 (ja) * 2011-11-24 2015-12-24 コニカミノルタ株式会社 ガスバリアーフィルム及び電子機器
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
US9496279B2 (en) * 2012-02-29 2016-11-15 Kyocera Corporation Composite substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091176A (ja) 1998-09-10 2000-03-31 Toyota Central Res & Dev Lab Inc 基板張り合わせ方法
US20030008475A1 (en) 1999-01-08 2003-01-09 Nathan W. Cheung Method for fabricating multi-layered substrates
JP2004503942A (ja) * 2000-06-16 2004-02-05 エス オー イ テク シリコン オン インシュレータ テクノロジース 基板製造方法及び該方法によって得られた基板
JP2005252550A (ja) * 2004-03-03 2005-09-15 Fujitsu Media Device Kk 接合基板、弾性表面波素子および弾性表面波デバイス
JP2010541230A (ja) 2007-09-27 2010-12-24 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ 基板とその一方の面上に堆積させた層とを含む構造体の製造方法
JP2009117533A (ja) * 2007-11-05 2009-05-28 Shin Etsu Chem Co Ltd 炭化珪素基板の製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J. Appl. Phys. 113권(20호), p. 203512(2013.5.)*
Jap. J. Appl. Phys. 38(3A), pp. 1589-1594(1999.3.)

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US20160204023A1 (en) 2016-07-14
EP3018696B8 (en) 2022-02-23
CN105474354B (zh) 2018-04-17
US9761479B2 (en) 2017-09-12
EP3018696A1 (en) 2016-05-11
EP3018696A4 (en) 2017-03-15
KR20160040565A (ko) 2016-04-14
CN105474354A (zh) 2016-04-06
WO2015002266A1 (ja) 2015-01-08
JP6061251B2 (ja) 2017-01-18
EP3018696B1 (en) 2021-11-17
JP2015015401A (ja) 2015-01-22

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