KR101496920B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR101496920B1
KR101496920B1 KR20080125595A KR20080125595A KR101496920B1 KR 101496920 B1 KR101496920 B1 KR 101496920B1 KR 20080125595 A KR20080125595 A KR 20080125595A KR 20080125595 A KR20080125595 A KR 20080125595A KR 101496920 B1 KR101496920 B1 KR 101496920B1
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KR
South Korea
Prior art keywords
wiring
pad
wiring board
semiconductor element
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
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KR20080125595A
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English (en)
Korean (ko)
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KR20090064314A (ko
Inventor
히토시 사토
Original Assignee
신꼬오덴기 고교 가부시키가이샤
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Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20090064314A publication Critical patent/KR20090064314A/ko
Application granted granted Critical
Publication of KR101496920B1 publication Critical patent/KR101496920B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR20080125595A 2007-12-14 2008-12-11 반도체 장치 Active KR101496920B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2007-323744 2007-12-14
JP2007323744A JP5265183B2 (ja) 2007-12-14 2007-12-14 半導体装置

Publications (2)

Publication Number Publication Date
KR20090064314A KR20090064314A (ko) 2009-06-18
KR101496920B1 true KR101496920B1 (ko) 2015-02-27

Family

ID=40752110

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20080125595A Active KR101496920B1 (ko) 2007-12-14 2008-12-11 반도체 장치

Country Status (5)

Country Link
US (1) US8022524B2 (https=)
JP (1) JP5265183B2 (https=)
KR (1) KR101496920B1 (https=)
CN (1) CN101459156B (https=)
TW (1) TWI434395B (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5709386B2 (ja) * 2010-02-19 2015-04-30 キヤノン株式会社 半導体装置の製造方法及び積層型半導体装置の製造方法
US8339231B1 (en) * 2010-03-22 2012-12-25 Flextronics Ap, Llc Leadframe based magnetics package
JP5666366B2 (ja) * 2011-03-31 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
JP2013219170A (ja) * 2012-04-09 2013-10-24 Yokogawa Electric Corp 基板装置
US10115671B2 (en) * 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US8969730B2 (en) * 2012-08-16 2015-03-03 Apple Inc. Printed circuit solder connections
US9443758B2 (en) 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
KR102287396B1 (ko) * 2014-10-21 2021-08-06 삼성전자주식회사 시스템 온 패키지 모듈과 이를 포함하는 모바일 컴퓨팅 장치
JP6691762B2 (ja) * 2015-11-03 2020-05-13 日本特殊陶業株式会社 検査用配線基板
KR102192569B1 (ko) * 2015-11-06 2020-12-17 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
FR3044864B1 (fr) * 2015-12-02 2018-01-12 Valeo Systemes De Controle Moteur Dispositif electrique et procede d'assemblage d'un tel dispositif electrique
CN116017847A (zh) * 2023-02-24 2023-04-25 合肥维信诺科技有限公司 电路板及电子设备
CN117976660B (zh) * 2024-03-27 2024-06-21 湖北江城实验室 一种半导体结构及其热测试方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096334A1 (en) 2005-10-27 2007-05-03 Takeshi Kawabata Stacked semiconductor module
JP2007281129A (ja) 2006-04-05 2007-10-25 Toshiba Corp 積層型半導体装置
US20080258278A1 (en) 2002-04-29 2008-10-23 Mary Jean Ramos Partially patterned lead frames and methods of making and using the same in semiconductor packaging

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2806357B2 (ja) * 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
JPH1117058A (ja) * 1997-06-26 1999-01-22 Nec Corp Ｂｇａパッケージ、その試験用ソケットおよびｂｇａパッケージの試験方法
JP2000101245A (ja) * 1998-09-24 2000-04-07 Ngk Spark Plug Co Ltd 積層樹脂配線基板及びその製造方法
US7102892B2 (en) * 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US20030234660A1 (en) * 2002-06-24 2003-12-25 Jain Sunil K. Direct landing technology for wafer probe
JP4086657B2 (ja) * 2002-12-27 2008-05-14 富士通株式会社 積層型半導体装置
US7271581B2 (en) * 2003-04-02 2007-09-18 Micron Technology, Inc. Integrated circuit characterization printed circuit board, test equipment including same, method of fabrication thereof and method of characterizing an integrated circuit device
JP2005150443A (ja) * 2003-11-17 2005-06-09 Sharp Corp 積層型半導体装置およびその製造方法
JP4583850B2 (ja) * 2004-09-16 2010-11-17 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2006120935A (ja) * 2004-10-22 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2006351565A (ja) 2005-06-13 2006-12-28 Shinko Electric Ind Co Ltd 積層型半導体パッケージ
JP4473807B2 (ja) * 2005-10-27 2010-06-02 パナソニック株式会社 積層半導体装置及び積層半導体装置の下層モジュール
JP2007183164A (ja) * 2006-01-06 2007-07-19 Fujitsu Ltd 半導体集積回路装置及びその試験方法
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258278A1 (en) 2002-04-29 2008-10-23 Mary Jean Ramos Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20070096334A1 (en) 2005-10-27 2007-05-03 Takeshi Kawabata Stacked semiconductor module
JP2007123520A (ja) 2005-10-27 2007-05-17 Matsushita Electric Ind Co Ltd 積層型半導体モジュール
JP2007281129A (ja) 2006-04-05 2007-10-25 Toshiba Corp 積層型半導体装置

Also Published As

Publication number Publication date
TW200935587A (en) 2009-08-16
JP5265183B2 (ja) 2013-08-14
CN101459156B (zh) 2012-11-14
TWI434395B (zh) 2014-04-11
US20090152693A1 (en) 2009-06-18
US8022524B2 (en) 2011-09-20
KR20090064314A (ko) 2009-06-18
CN101459156A (zh) 2009-06-17
JP2009147165A (ja) 2009-07-02

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