KR101484492B1 - 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 - Google Patents

반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 Download PDF

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Publication number
KR101484492B1
KR101484492B1 KR20080099869A KR20080099869A KR101484492B1 KR 101484492 B1 KR101484492 B1 KR 101484492B1 KR 20080099869 A KR20080099869 A KR 20080099869A KR 20080099869 A KR20080099869 A KR 20080099869A KR 101484492 B1 KR101484492 B1 KR 101484492B1
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South Korea
Prior art keywords
single crystal
crystal semiconductor
layer
semiconductor layer
substrate
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Expired - Fee Related
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KR20080099869A
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Korean (ko)
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KR20090037365A (ko
Inventor
순페이 야마자키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
KR20080099869A 2007-10-10 2008-10-10 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 Expired - Fee Related KR101484492B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2007264900 2007-10-10
JPJP-P-2007-264900 2007-10-10
JP2007267273 2007-10-12
JPJP-P-2007-267273 2007-10-12
JP2007275831 2007-10-23
JPJP-P-2007-275831 2007-10-23

Publications (2)

Publication Number Publication Date
KR20090037365A KR20090037365A (ko) 2009-04-15
KR101484492B1 true KR101484492B1 (ko) 2015-01-20

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US (2) US7799658B2 (enExample)
JP (1) JP5383143B2 (enExample)
KR (1) KR101484492B1 (enExample)

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JP5548356B2 (ja) * 2007-11-05 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5464843B2 (ja) * 2007-12-03 2014-04-09 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5404064B2 (ja) 2008-01-16 2014-01-29 株式会社半導体エネルギー研究所 レーザ処理装置、および半導体基板の作製方法
US7943414B2 (en) * 2008-08-01 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
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US8278187B2 (en) * 2009-06-24 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP5713603B2 (ja) * 2009-09-02 2015-05-07 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
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JP6005401B2 (ja) * 2011-06-10 2016-10-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
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FR2978604B1 (fr) * 2011-07-28 2018-09-14 Soitec Procede de guerison de defauts dans une couche semi-conductrice
US9041147B2 (en) * 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus
JP6032963B2 (ja) 2012-06-20 2016-11-30 キヤノン株式会社 Ｓｏｉ基板、ｓｏｉ基板の製造方法および半導体装置の製造方法
JP6066672B2 (ja) * 2012-11-05 2017-01-25 株式会社ディスコ ウエーハの加工方法
JP2014093444A (ja) 2012-11-05 2014-05-19 Disco Abrasive Syst Ltd ウエーハの加工方法
JP6066673B2 (ja) * 2012-11-05 2017-01-25 株式会社ディスコ ウエーハの加工方法
DE102012110971B4 (de) * 2012-11-14 2025-03-20 Schott Ag Verfahren zur Herstellung von linienförmig aufgereihten Schädigungsstellen in einem transparenten Werkstück sowie Verfahren und Vorrichtung zum Trennen eines Werkstücks
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JP5383143B2 (ja) 2014-01-08
US8314012B2 (en) 2012-11-20
JP2009124117A (ja) 2009-06-04
KR20090037365A (ko) 2009-04-15
US7799658B2 (en) 2010-09-21
US20090098710A1 (en) 2009-04-16
US20110003461A1 (en) 2011-01-06

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