KR101392570B1 - 삼중층 레지스트 유기층 에칭 - Google Patents

삼중층 레지스트 유기층 에칭 Download PDF

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KR101392570B1
KR101392570B1 KR1020070084189A KR20070084189A KR101392570B1 KR 101392570 B1 KR101392570 B1 KR 101392570B1 KR 1020070084189 A KR1020070084189 A KR 1020070084189A KR 20070084189 A KR20070084189 A KR 20070084189A KR 101392570 B1 KR101392570 B1 KR 101392570B1
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South Korea
Prior art keywords
etching
layer
organic planarization
gas
planarization layer
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Korean (ko)
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KR20080017287A (ko
Inventor
션 에스 강
상준 조
톰 최
태준 한
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램 리써치 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
KR1020070084189A 2006-08-21 2007-08-21 삼중층 레지스트 유기층 에칭 Active KR101392570B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/507,862 2006-08-21
US11/507,862 US8124516B2 (en) 2006-08-21 2006-08-21 Trilayer resist organic layer etch

Publications (2)

Publication Number Publication Date
KR20080017287A KR20080017287A (ko) 2008-02-26
KR101392570B1 true KR101392570B1 (ko) 2014-05-08

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ID=39101865

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KR1020070084189A Active KR101392570B1 (ko) 2006-08-21 2007-08-21 삼중층 레지스트 유기층 에칭

Country Status (7)

Country Link
US (1) US8124516B2 (https=)
JP (1) JP5165306B2 (https=)
KR (1) KR101392570B1 (https=)
CN (1) CN101131928B (https=)
MY (1) MY150187A (https=)
SG (1) SG140537A1 (https=)
TW (1) TWI427696B (https=)

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US7595005B2 (en) * 2006-12-11 2009-09-29 Tokyo Electron Limited Method and apparatus for ashing a substrate using carbon dioxide
US8435895B2 (en) 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US8003488B2 (en) * 2007-09-26 2011-08-23 International Business Machines Corporation Shallow trench isolation structure compatible with SOI embedded DRAM
WO2009085672A2 (en) 2007-12-21 2009-07-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
KR101791685B1 (ko) * 2008-10-14 2017-11-20 노벨러스 시스템즈, 인코포레이티드 수소 이용 화학 반응으로 고용량 주입 스트립(ｈｄｉｓ) 방법 및 장치
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
CN101958277B (zh) * 2009-07-16 2013-01-23 中芯国际集成电路制造(上海)有限公司 金属布线沟槽的形成方法
US7637269B1 (en) 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
JP5532826B2 (ja) * 2009-11-04 2014-06-25 富士通セミコンダクター株式会社 半導体素子の製造方法
US20110143548A1 (en) * 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
US8721797B2 (en) 2009-12-11 2014-05-13 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
CN102208333A (zh) * 2011-05-27 2011-10-05 中微半导体设备(上海)有限公司 等离子体刻蚀方法
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
CN102364670B (zh) * 2011-09-15 2013-06-12 上海华力微电子有限公司 金属铜大马士革互联结构的制造方法
US9666414B2 (en) 2011-10-27 2017-05-30 Applied Materials, Inc. Process chamber for etching low k and other dielectric films
CN103227108B (zh) * 2012-01-31 2016-01-06 中微半导体设备(上海)有限公司 一种有机物层刻蚀方法
CN102915959B (zh) * 2012-10-08 2015-06-17 上海华力微电子有限公司 一种简化存储器中字线介电质膜刻蚀成型工艺的方法
US9385000B2 (en) * 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films

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KR100483838B1 (ko) 2003-02-28 2005-04-15 삼성전자주식회사 금속배선의 듀얼 다마신 방법
JP2005251901A (ja) 2004-03-03 2005-09-15 Ulvac Japan Ltd 層間絶縁膜のドライエッチング方法
US20060024968A1 (en) 2004-08-02 2006-02-02 Lam Research Corporation Method for stripping photoresist from etched wafer

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US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4659426A (en) * 1985-05-03 1987-04-21 Texas Instruments Incorporated Plasma etching of refractory metals and their silicides
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US5874201A (en) 1995-06-05 1999-02-23 International Business Machines Corporation Dual damascene process having tapered vias
US6037266A (en) * 1998-09-28 2000-03-14 Taiwan Semiconductor Manufacturing Company Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher
US6258732B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
JP3803528B2 (ja) * 2000-03-31 2006-08-02 株式会社東芝 半導体装置の製造方法及び半導体装置
US6794293B2 (en) * 2001-10-05 2004-09-21 Lam Research Corporation Trench etch process for low-k dielectrics
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JP2004253659A (ja) * 2003-02-20 2004-09-09 Renesas Technology Corp 半導体装置の製造方法
JP4681217B2 (ja) * 2003-08-28 2011-05-11 株式会社アルバック 層間絶縁膜のドライエッチング方法
CN1282237C (zh) * 2003-08-29 2006-10-25 华邦电子股份有限公司 双镶嵌式开口结构的制作方法
JP2006128543A (ja) * 2004-11-01 2006-05-18 Nec Electronics Corp 電子デバイスの製造方法
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US20070134917A1 (en) * 2005-12-13 2007-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Partial-via-first dual-damascene process with tri-layer resist approach
JP4940722B2 (ja) * 2006-03-24 2012-05-30 東京エレクトロン株式会社 半導体装置の製造方法及びプラズマ処理装置並びに記憶媒体
US7695897B2 (en) * 2006-05-08 2010-04-13 International Business Machines Corporation Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
KR100483838B1 (ko) 2003-02-28 2005-04-15 삼성전자주식회사 금속배선의 듀얼 다마신 방법
JP2005079192A (ja) 2003-08-28 2005-03-24 Ulvac Japan Ltd 有機膜のドライエッチング方法
JP2005251901A (ja) 2004-03-03 2005-09-15 Ulvac Japan Ltd 層間絶縁膜のドライエッチング方法
US20060024968A1 (en) 2004-08-02 2006-02-02 Lam Research Corporation Method for stripping photoresist from etched wafer

Also Published As

Publication number Publication date
US8124516B2 (en) 2012-02-28
JP2008060565A (ja) 2008-03-13
JP5165306B2 (ja) 2013-03-21
SG140537A1 (en) 2008-03-28
CN101131928A (zh) 2008-02-27
CN101131928B (zh) 2011-11-02
TW200830405A (en) 2008-07-16
US20080044995A1 (en) 2008-02-21
MY150187A (en) 2013-12-13
TWI427696B (zh) 2014-02-21
KR20080017287A (ko) 2008-02-26

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