KR101005028B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
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- KR101005028B1 KR101005028B1 KR1020087017279A KR20087017279A KR101005028B1 KR 101005028 B1 KR101005028 B1 KR 101005028B1 KR 1020087017279 A KR1020087017279 A KR 1020087017279A KR 20087017279 A KR20087017279 A KR 20087017279A KR 101005028 B1 KR101005028 B1 KR 101005028B1
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Abstract
Description
도 2m에 나타낸 바와 같이, 알루미나막(22) 위에, 예를 들어 TEOS를 소스로 한 산화 실리콘막(23)을 두께 2600㎚ 정도 CVD에 의해 성막하고, 표면을 평탄화하하고, 상술한 바와 같은 플라스마 어닐링에 의해 표면을 질화한다. 또한, TEOS를 소스로 한 산화 실리콘막(24)을 두께 100㎚ 정도 CVD에 의해 형성한다. 이 산화 실리콘막(24)의 표면을 질화하기 위해 플라스마 어닐링을 더 행한다. 이와 같이 하여 제 1 층간절연막을 형성한 후 레지스트 패턴을 형성하고, 제 1 메탈 배선(M1W)과 제 2 메탈 배선을 접속하기 위한 콘택트 홀(CH)을 에칭한다.
Claims (20)
- 반도체 기판과,상기 반도체 기판에 형성된 복수의 반도체 소자를 포함하는 회로부와,상기 회로부를 덮어, 상기 반도체 기판 상에 형성된 절연 적층과,상기 절연 적층 중에 형성되고, 배선 패턴과 비아(via) 도전체를 포함하는 다층 배선 구조와,상기 반도체 기판 상방에 형성되고, 상기 다층 배선 구조에 접속된 패드 전극 구조로서, 복수층의 패드용 배선 패턴과, 상기 패드용 배선 패턴 사이를 접속하는 패드용 비아 도전체를 포함하고, 적어도 최상층의 패드용 배선 패턴은 패드 패턴과 상기 패드 패턴으로부터 거리를 두고, 루프(loop) 형상으로 둘러싸는 실(seal) 패턴을 포함하고, 최상층 이외의 패드용 배선 패턴 중 적어도 하나는 연속된, 상기 실 패턴에 대응하는 크기의 확대 패드 패턴을 갖고, 상기 패드용 비아 도전체는 상기 패드 패턴에 대응하여 배치된 복수의 기둥 형상 비아 도전체와 상기 실 패턴에 대응하여 배치된 루프 형상 벽부를 포함하고, 상기 패드용 배선 패턴의 패드 패턴 또는 상기 확대 패드 패턴과 상기 기둥 형상 비아 도전체가 적층 본딩 패드를 구성하고, 상기 확대 패드 패턴과 상기 실 패턴 및 상기 루프 형상 벽부가 상기 적층 본딩 패드를 둘러싸며, 수분, 수소를 차폐하는 기능을 갖는 컵(cup) 형상 내습(耐濕) 구조를 형성하는 패드 전극 구조를 갖는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,최하층의 상기 패드용 배선 패턴은 상기 확대 패드 패턴을 갖고, 상기 내습 링과 상기 최하층의 패드용 배선 패턴은 바닥이 닫힌 루프 형상 벽부를 구성하는 것을 특징으로 하는 반도체 장치.
- 제 2 항에 있어서,최상층, 최하층 이외의 상기 패드용 배선 패턴 중 적어도 하나가 상기 확대 패드 패턴을 갖는 것을 특징으로 하는 반도체 장치.
- 제 2 항에 있어서,최하층 이외의 상기 패드용 배선 패턴이 상기 패드 패턴과 상기 실 패턴을 갖는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,최상층 이외의 상기 패드용 배선 패턴은 상기 배선 패턴과 동일한 층에서 형성되고, 최상층 이외의 상기 패드용 비아 도전체는 상기 비아 도전체와 동일한 층에서 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,최상층의 상기 패드용 배선 패턴은 알루미늄을 사용하여 형성되고, 상기 비아 도전체 및 상기 패드용 비아 도전체는 텅스텐을 사용하여 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 반도체 기판의 외주(外周)를 따라, 상기 패드 전극 구조 외측에서, 상기 절연 적층을 관통하여 형성된 외측 칩 내습 링을 더 갖는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 절연 적층은 상기 반도체 소자를 덮어 상기 반도체 기판 상에 형성된 질화 실리콘 또는 산화 질화 실리콘의 하부 보호막을 포함하고,상기 반도체 소자에 접속되고, 상기 하부 보호막을 관통하여 상방으로 연장되는 하부 비아 도전체와,최하층의 상기 패드용 배선 패턴의 주변부 하면(下面)의 루프 형상 영역에 접속되고, 하방으로 연장되며, 상기 하부 보호막에 도달하는 하부 루프 형상 벽부를 더 갖는 것을 특징으로 하는 반도체 장치.
- 제 8 항에 있어서,상기 하부 비아 도전체와 상기 하부 루프 형상 벽부가 동일한 층에서 형성되 어 있는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 반도체 기판 상방에 형성되고, 하부 전극과, 산화물 강유전체막과, 상부 전극을 포함하는 강유전체 커패시터를 더 갖고, 상기 다층 배선 구조는 상기 강유전체 커패시터 상방에 배치되어 있는 것을 특징으로 하는 반도체 장치.
- 제 10 항에 있어서,상기 절연 적층이 상기 강유전체 커패시터의 아래에, 수분, 수소를 차폐하는 기능을 갖는 하지 보호막을 포함하는 것을 특징으로 하는 반도체 장치.
- 제 11 항에 있어서,상기 하지 보호막이 산화 알루미늄, 산화 티탄 중 어느 하나를 사용하여 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 절연 적층이 상기 기둥 형상 비아 도전체와 교차하는 제 1 레벨에 배치되고, 수분, 수소를 차폐하는 기능을 갖는 제 1 절연 배리어층을 포함하는 것을 특징으로 하는 반도체 장치.
- 제 13 항에 있어서,상기 절연 적층이 상기 제 1 레벨과 상이한 제 2 레벨에 배치되고, 상기 기둥 형상 비아 도전체와 교차하는 수분, 수소를 차폐하는 기능을 갖는 제 2 절연 배리어층을 더 포함하는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 절연 적층이 최상층의 상기 패드용 배선 패턴 상면에 접하는 수분, 수소를 차폐하는 기능을 갖는 제 3 절연 배리어층을 포함하는 것을 특징으로 하는 반도체 장치.
- 제 13 항에 있어서,상기 절연 배리어층이 산화 알루미늄, 산화 티탄 중 어느 하나를 사용하여 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제 16 항에 있어서,상기 절연 배리어층의 두께가 20∼100㎚의 범위 내인 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 패드용 배선 패턴 중 적어도 하나는 상기 패드 패턴과 상기 실 패턴과 접속하는 제 1 배선부와, 상기 실 패턴으로부터 더 외측으로 연장되는 제 2 배선부, 또는 상기 확대 패드 패턴으로부터 외측으로 연장되는 제 3 배선부를 더 갖는 것을 특징으로 하는 반도체 장치.
- 제 18 항에 있어서,상기 패드 전극 구조보다 내측에서, 상기 절연 적층을 관통하여 루프 형상으로 형성되고, 상기 제 2 또는 제 3 배선부와 교차하는 부분에서 노치되어 있는 내측 칩 내습 링을 더 갖는 것을 특징으로 하는 반도체 장치.
- 복수의 칩 영역을 포함하는 반도체 기판의 각 칩 영역에 복수의 반도체 소자를 형성하는 공정과,상기 복수의 반도체 소자를 덮어, 상기 반도체 기판 상에 하부 층간절연막을 형성하는 공정과,상기 하부 층간절연막 상에, 강유전체 커패시터를 형성하는 공정과,상기 강유전체 커패시터를 덮어, 상기 하부 층간절연막 상에 절연 적층을 형성하는 공정과,상기 절연 적층 중에 배치된 다층 배선 구조를 형성하는 공정과,상기 반도체 기판 상방에 배치되고, 상기 다층 배선 구조에 접속된 패드 전극 구조를 형성하는 공정으로서, 상기 절연 적층 중에 복수의 패드용 배선 패턴과, 상기 패드용 배선 패턴 사이를 접속하는 패드용 비아 도전체를 포함하고, 적어도 최상층의 패드용 배선 패턴은 패드 패턴과 상기 패드 패턴을 거리를 두고 둘러싸는 실 패턴을 포함하고, 최상층 이외의 패드용 배선 패턴 중 적어도 하나는 연속된, 상기 실 패턴에 대응하는 크기의 확대 패드 패턴을 갖고, 상기 패드용 비아 도전체는 상기 패드 패턴에 대응하여 배치된 복수의 기둥 형상 비아 도전체와 상기 실 패턴에 대응하여 배치된 루프 형상 벽부를 포함하고, 상기 패드용 배선 패턴의 패드 패턴 또는 상기 확대 패드 패턴과 상기 기둥 형상 비아 도전체가 적층 본딩 패드를 구성하고, 상기 실 패턴 및 상기 확대 패드 패턴의 가장자리부와 상기 루프 형상 벽부가 상기 적층 본딩 패드를 둘러싸며, 수분, 수소를 차폐하는 기능을 갖는 내습 링을 형성하는 패드 전극 구조를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
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Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008016638A (ja) * | 2006-07-06 | 2008-01-24 | Sony Corp | 半導体装置 |
CN101617399B (zh) * | 2007-02-27 | 2011-05-18 | 富士通半导体股份有限公司 | 半导体存储器件及其制造、测试方法、封装树脂形成方法 |
KR100995558B1 (ko) * | 2007-03-22 | 2010-11-22 | 후지쯔 세미컨덕터 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
JP2009231445A (ja) * | 2008-03-21 | 2009-10-08 | Toshiba Corp | 半導体記憶装置 |
JP5407422B2 (ja) | 2009-02-27 | 2014-02-05 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8654539B2 (en) * | 2009-12-15 | 2014-02-18 | Ngk Spark Plug Co., Ltd. | Capacitor-incorporated substrate and component-incorporated wiring substrate |
JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
JP2011199186A (ja) | 2010-03-23 | 2011-10-06 | Toshiba Corp | 不揮発性記憶装置およびその製造方法 |
KR101184375B1 (ko) | 2010-05-10 | 2012-09-20 | 매그나칩 반도체 유한회사 | 패드 영역의 크랙 발생을 방지하는 반도체 장치 및 그 제조 방법 |
JP6342033B2 (ja) * | 2010-06-30 | 2018-06-13 | キヤノン株式会社 | 固体撮像装置 |
US8652855B2 (en) * | 2011-03-29 | 2014-02-18 | Texas Instruments Incorporated | Low resistance stacked annular contact |
US9048019B2 (en) * | 2011-09-27 | 2015-06-02 | Infineon Technologies Ag | Semiconductor structure including guard ring |
JP5802534B2 (ja) * | 2011-12-06 | 2015-10-28 | 株式会社東芝 | 半導体装置 |
US8629559B2 (en) | 2012-02-09 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus with an inverted cup-shaped layer |
JP6157100B2 (ja) | 2012-12-13 | 2017-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6133611B2 (ja) * | 2013-02-06 | 2017-05-24 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
JP6319028B2 (ja) * | 2014-10-03 | 2018-05-09 | 三菱電機株式会社 | 半導体装置 |
JP2016139711A (ja) * | 2015-01-28 | 2016-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10355139B2 (en) | 2016-06-28 | 2019-07-16 | Sandisk Technologies Llc | Three-dimensional memory device with amorphous barrier layer and method of making thereof |
US10361213B2 (en) | 2016-06-28 | 2019-07-23 | Sandisk Technologies Llc | Three dimensional memory device containing multilayer wordline barrier films and method of making thereof |
US10217707B2 (en) * | 2016-09-16 | 2019-02-26 | International Business Machines Corporation | Trench contact resistance reduction |
US9929114B1 (en) * | 2016-11-02 | 2018-03-27 | Vanguard International Semiconductor Corporation | Bonding pad structure having island portions and method for manufacturing the same |
US10115735B2 (en) | 2017-02-24 | 2018-10-30 | Sandisk Technologies Llc | Semiconductor device containing multilayer titanium nitride diffusion barrier and method of making thereof |
DE102018125018A1 (de) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Zweidimensionale Durchkontaktierungssäulenstrukturen |
KR102546684B1 (ko) * | 2017-11-29 | 2023-06-23 | 삼성전자주식회사 | 반도체 소자 및 이를 포함하는 반도체 웨이퍼, 그리고 반도체 패키지 |
US10229931B1 (en) | 2017-12-05 | 2019-03-12 | Sandisk Technologies Llc | Three-dimensional memory device containing fluorine-free tungsten—word lines and methods of manufacturing the same |
US11217532B2 (en) | 2018-03-14 | 2022-01-04 | Sandisk Technologies Llc | Three-dimensional memory device containing compositionally graded word line diffusion barrier layer for and methods of forming the same |
US11217547B2 (en) * | 2019-09-03 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure with reduced step height and increased electrical isolation |
US11088141B2 (en) * | 2019-10-03 | 2021-08-10 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
JP7459490B2 (ja) | 2019-11-28 | 2024-04-02 | 株式会社ソシオネクスト | 半導体ウェハ及び半導体装置 |
US11127700B1 (en) * | 2020-05-28 | 2021-09-21 | United Microelectronics Corp. | Integrated circuit device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289689A (ja) | 2001-03-28 | 2002-10-04 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2005142553A (ja) | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
JP2005175204A (ja) | 2003-12-11 | 2005-06-30 | Fujitsu Ltd | 半導体装置およびその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015696A (ja) * | 1999-06-29 | 2001-01-19 | Nec Corp | 水素バリヤ層及び半導体装置 |
US6492222B1 (en) * | 1999-12-22 | 2002-12-10 | Texas Instruments Incorporated | Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices |
JP4118029B2 (ja) | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
JP4011334B2 (ja) | 2001-12-04 | 2007-11-21 | 富士通株式会社 | 強誘電体キャパシタの製造方法およびターゲット |
JP2004134450A (ja) | 2002-10-08 | 2004-04-30 | Fujitsu Ltd | 半導体集積回路 |
JP4502173B2 (ja) | 2003-02-03 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
WO2004095578A1 (ja) * | 2003-04-24 | 2004-11-04 | Fujitsu Limited | 半導体装置及びその製造方法 |
US7049701B2 (en) * | 2003-10-15 | 2006-05-23 | Kabushiki Kaisha Toshiba | Semiconductor device using insulating film of low dielectric constant as interlayer insulating film |
WO2005106957A1 (ja) * | 2004-04-30 | 2005-11-10 | Fujitsu Limited | 半導体装置及びその製造方法 |
-
2005
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289689A (ja) | 2001-03-28 | 2002-10-04 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2005142553A (ja) | 2003-10-15 | 2005-06-02 | Toshiba Corp | 半導体装置 |
JP2005175204A (ja) | 2003-12-11 | 2005-06-30 | Fujitsu Ltd | 半導体装置およびその製造方法 |
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