KR100961404B1 - 집적 회로 장치 및 그 형성 방법 - Google Patents

집적 회로 장치 및 그 형성 방법 Download PDF

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Publication number
KR100961404B1
KR100961404B1 KR1020047014786A KR20047014786A KR100961404B1 KR 100961404 B1 KR100961404 B1 KR 100961404B1 KR 1020047014786 A KR1020047014786 A KR 1020047014786A KR 20047014786 A KR20047014786 A KR 20047014786A KR 100961404 B1 KR100961404 B1 KR 100961404B1
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South Korea
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sidewall
layer
forming
delete delete
gate
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Expired - Fee Related
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KR1020047014786A
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Korean (ko)
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KR20040097188A (ko
Inventor
조프리 씨-에프 옙
스리니바스 잘레팔리
전용주
제임스 다비드 버네트
라나 피. 싱
폴 에이. 그루도스키
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프리스케일 세미컨덕터, 인크.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Non-Volatile Memory (AREA)
KR1020047014786A 2002-03-19 2003-03-14 집적 회로 장치 및 그 형성 방법 Expired - Fee Related KR100961404B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/101,298 US6753242B2 (en) 2002-03-19 2002-03-19 Integrated circuit device and method therefor
US10/101,298 2002-03-19
PCT/US2003/007835 WO2003081660A1 (en) 2002-03-19 2003-03-14 Integrated circuit device and method therefor

Publications (2)

Publication Number Publication Date
KR20040097188A KR20040097188A (ko) 2004-11-17
KR100961404B1 true KR100961404B1 (ko) 2010-06-09

Family

ID=28039985

Family Applications (1)

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KR1020047014786A Expired - Fee Related KR100961404B1 (ko) 2002-03-19 2003-03-14 집적 회로 장치 및 그 형성 방법

Country Status (8)

Country Link
US (2) US6753242B2 (https=)
EP (1) EP1485948A1 (https=)
JP (1) JP2005531919A (https=)
KR (1) KR100961404B1 (https=)
CN (1) CN100339961C (https=)
AU (1) AU2003225792A1 (https=)
TW (1) TWI283029B (https=)
WO (1) WO2003081660A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010608A (zh) * 2017-11-30 2019-07-12 台湾积体电路制造股份有限公司 存储器件及其形成方法

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KR100488099B1 (ko) * 2002-11-18 2005-05-06 한국전자통신연구원 쇼오트 채널 모오스 트랜지스터 및 그 제조 방법
US6884712B2 (en) * 2003-02-07 2005-04-26 Chartered Semiconductor Manufacturing, Ltd. Method of manufacturing semiconductor local interconnect and contact
US6913980B2 (en) * 2003-06-30 2005-07-05 Texas Instruments Incorporated Process method of source drain spacer engineering to improve transistor capacitance
JP2005109381A (ja) * 2003-10-02 2005-04-21 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US7229885B2 (en) * 2004-01-06 2007-06-12 International Business Machines Corporation Formation of a disposable spacer to post dope a gate conductor
US7064396B2 (en) * 2004-03-01 2006-06-20 Freescale Semiconductor, Inc. Integrated circuit with multiple spacer insulating region widths
US8896048B1 (en) * 2004-06-04 2014-11-25 Spansion Llc Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7170130B2 (en) * 2004-08-11 2007-01-30 Spansion Llc Memory cell with reduced DIBL and Vss resistance
KR100668954B1 (ko) * 2004-12-15 2007-01-12 동부일렉트로닉스 주식회사 박막트랜지스터 제조 방법
KR100685575B1 (ko) * 2004-12-28 2007-02-22 주식회사 하이닉스반도체 반도체 소자의 스텝 채널 형성 방법
US7544553B2 (en) * 2005-03-30 2009-06-09 Infineon Technologies Ag Integration scheme for fully silicided gate
US20070007578A1 (en) * 2005-07-07 2007-01-11 Li Chi N B Sub zero spacer for shallow MDD junction to improve BVDSS in NVM bitcell
US8159030B2 (en) * 2005-11-30 2012-04-17 Globalfoundries Inc. Strained MOS device and methods for its fabrication
KR100741908B1 (ko) * 2005-12-30 2007-07-24 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7317222B2 (en) * 2006-01-27 2008-01-08 Freescale Semiconductor, Inc. Memory cell using a dielectric having non-uniform thickness
JP4799217B2 (ja) * 2006-03-03 2011-10-26 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2008098567A (ja) * 2006-10-16 2008-04-24 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US7700473B2 (en) * 2007-04-09 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Gated semiconductor device and method of fabricating same
US7745344B2 (en) * 2007-10-29 2010-06-29 Freescale Semiconductor, Inc. Method for integrating NVM circuitry with logic circuitry
KR101815527B1 (ko) 2010-10-07 2018-01-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN102420116B (zh) * 2011-06-07 2013-12-04 上海华力微电子有限公司 消除栅极凹形缺陷的方法
JP5715551B2 (ja) * 2011-11-25 2015-05-07 株式会社東芝 半導体装置およびその製造方法
CN104752223B (zh) * 2013-12-31 2017-12-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9647116B1 (en) 2015-10-28 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating self-aligned contact in a semiconductor device
CN114121788A (zh) * 2021-11-24 2022-03-01 华虹半导体(无锡)有限公司 或非闪存器件的制作方法

Citations (4)

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US5902125A (en) 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US5972762A (en) 1998-01-05 1999-10-26 Texas Instruments--Acer Incorporated Method of forming mosfets with recessed self-aligned silicide gradual S/D junction
US6066567A (en) 1997-12-18 2000-05-23 Advanced Micro Devices, Inc. Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
US6087271A (en) 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. Methods for removal of an anti-reflective coating following a resist protect etching process

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US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US6245682B1 (en) 1999-03-11 2001-06-12 Taiwan Semiconductor Manufacturing Company Removal of SiON ARC film after poly photo and etch
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
WO2001050504A2 (en) 1999-12-30 2001-07-12 Koninklijke Philips Electronics N.V. An improved method for buried anti-reflective coating removal
US6156126A (en) 2000-01-18 2000-12-05 United Microelectronics Corp. Method for reducing or avoiding the formation of a silicon recess in SDE junction regions
US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US6368947B1 (en) * 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6555865B2 (en) * 2001-07-10 2003-04-29 Samsung Electronics Co. Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US6818504B2 (en) * 2001-08-10 2004-11-16 Hynix Semiconductor America, Inc. Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications
US6812515B2 (en) * 2001-11-26 2004-11-02 Hynix Semiconductor, Inc. Polysilicon layers structure and method of forming same

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Publication number Priority date Publication date Assignee Title
US6066567A (en) 1997-12-18 2000-05-23 Advanced Micro Devices, Inc. Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
US6087271A (en) 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. Methods for removal of an anti-reflective coating following a resist protect etching process
US5902125A (en) 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US5972762A (en) 1998-01-05 1999-10-26 Texas Instruments--Acer Incorporated Method of forming mosfets with recessed self-aligned silicide gradual S/D junction

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010608A (zh) * 2017-11-30 2019-07-12 台湾积体电路制造股份有限公司 存储器件及其形成方法
US11653498B2 (en) 2017-11-30 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention
US12543317B2 (en) 2017-11-30 2026-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention

Also Published As

Publication number Publication date
AU2003225792A1 (en) 2003-10-08
CN100339961C (zh) 2007-09-26
US20040124450A1 (en) 2004-07-01
TWI283029B (en) 2007-06-21
WO2003081660A1 (en) 2003-10-02
TW200305954A (en) 2003-11-01
US20030181028A1 (en) 2003-09-25
JP2005531919A (ja) 2005-10-20
EP1485948A1 (en) 2004-12-15
CN1643671A (zh) 2005-07-20
US6753242B2 (en) 2004-06-22
US6846716B2 (en) 2005-01-25
KR20040097188A (ko) 2004-11-17

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