TWI283029B - Integrated circuit device and method therefor - Google Patents

Integrated circuit device and method therefor Download PDF

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TWI283029B
TWI283029B TW092105907A TW92105907A TWI283029B TW I283029 B TWI283029 B TW I283029B TW 092105907 A TW092105907 A TW 092105907A TW 92105907 A TW92105907 A TW 92105907A TW I283029 B TWI283029 B TW I283029B
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layer
patterned
sidewall
adjacent
semiconductor substrate
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TW200305954A (en
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Geoffrey C-F Yeap
Srinivas Jallepalli
Yongjoo Jeon
James David Burnett
Rana P Singh
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Freescale Semiconductor Inc
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Description

1283029 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡軍說明） 先前申請春老_ 本專利申請案已於2002年3月19曰提出美國專利申請，專 利申請案號為10/101，298。 技術領| 本發明係關於積體電路，具體而言，係關於在基板中且 具有一凹陷的積體電路。 先前拮術 、在製造積體電路方面’隨著積體電路尺寸愈來愈小而變 成更重要的問題之-是，在正常處理過程中會在基板中發 生凹陷。在基板中發生凹陷的主要原因為，當姓刻去除基 板上之材料層一部份時會使基板曝露。在已去除被敍刻的 層期間及/或之後’蚀刻劑被塗佈在基板上達一段時間。舉 例而言’在開始蚀刻位於不同位置的另一種材料時會曝露 基板的情況。另-項實例是’在蝕刻位於其他位置的材料 期間會钮刻一位'於基板上的薄層’以便透過钱刻位於其他 位置的材料之方式使基板曝露。另一項實例是，-位於美 板上的薄層被钱刻，並且在曝露基板後，繼續㈣作㈣ 於確保徹底去除所要去除之層的過度姓刻。希望所選擇的 u不β顯著姓刻半導體基板，但是就實際而言，此類 名虫刻劑難以運用。於暑合 、 $用於疋’會错由不會對半導體基板（通常是 夕w成姓刻作用的餘刻劑來去除所要去除的層係。圖α 圖9顯tf此類製程。 圖1顯示適用於製造積體電路的半導體裝置1G，其包括一 1283029
(2) 基板12、一多晶矽閘極14及一介於該基板12與該閘極“之 間的薄氧化物。為了去除氮化物抗反射塗層（ARC)16，會使 用一蝕刻劑，例如，如氟和氯之類的鹵素基材料。這些蝕 刻劑也會#刻石夕，但餘刻速度不會和蝕刻氮化物一樣快。 圖2顯示去除抗反射塗層（ARC)16的結果是一凹陷表面22。 圖3顯示有形成一側壁間隔24的裝置10。側壁間隔以係由氧 化物所形成，並且係由於塗佈一相當保角層並且後續使用 一各向異性#刻來姓刻这的結果而形成，如所熟知。這會 造成沿著該側壁間隔24該基板12中形成一進一步凹陷。圖I 顯示使用該側壁間隔24當做遮罩來形成源極/汲極區％及 源極/汲極區28。這項植入通常被稱為擴充植入，並且具有 比一後績而量源極/沒極植入相對低的摻雜濃产。 圖5顯示沈積一氧化物襯墊30和一氮化物層32之後的裝 置1〇。接著將氮化物層32回餘，以當做用於產生側壁間隔 34和襯墊部份38的襯墊30。在這項製程期間，源極/汲極區 26和28擴散，而使源極/汲極區26和28面積擴大。圖7顯示 使用違側壁間隔3 4當做遮罩以高濃度植入而構成高濃度植 摻雜的區域40和42之後的裝置1〇。圖8顯示由於標準製程導 致源極/汲極區26和28及區域40和42繼續擴大。 圖9顯示形成矽化物區48和50(在區域4〇和42下方擴大） 之後的裝置10。圖中還呈現出區域49和5 1(這是源極/汲極區 26和28的剩餘部份）完全擴散。這些區域不會全部擴大至閘 極氧化物20。由於區域49和5 1不會完全擴大而接觸到閘極 氧化物20，所以在閘極44與區域49和51間形成的通道之間 1283029
(3) 會有某額外空間’以至於在區域49和5 1之間通過的電流小 於這等區域擴散而更接近閘極20情況下所通過的電流。這 是一項缺點，並且是由於鄰接閘極44之基板12的凹陷而導 致擴散必須行進之額外距離的直接結果。矽化物區46也會 在閘極14上方形成，並且會消耗大量閘極14，而留下一屬 於多晶石夕區44和石夕化物區46之組合的閘極。 因此’品要一種在標準製程期間降低基板中所發生的凹 fe的負面效應。隨時尺寸遞減及電壓遞減，這項問題會更 糟。這能夠徹底反轉通道，並且如果源極與汲極沒有適當 重疊於閘極時，會影響在源極與汲極之間提供理想電流。 發明内容 種半導體裝置（10)，在去除咚反射塗層（anti_reflective coating ; ARC)(16)期間該半導體裝置具有形成於基板（12) 中的凹陷（22)，這是因為在|虫刻該抗反射塗層（ARC)(16)期 間會暴露該等凹陷位置（22)。雖然蝕刻劑被選擇以在該抗反 射塗層（ARC)材料（16)與該基板材料（12)之間選擇，但是這 項逛擇性被限制以便形成凹陷（22)。與形成該等凹陷相關的 一項問題為，源極/汲極（26,28)必須進一步擴散而變成重疊 於閘極（14)。結果是電晶體會降低電流驅動。解決該問題的 方式為’等待執行抗反射塗層（ARC)去除，至少直接在閘極 (64)四周形成一側壁間隔（70)之後。因此後續凹陷形成進一 步攸该閘極（64)發生，因而減少或排除凹陷對所要延伸以重 $於该閘極（64)之源極/汲極（72,74)擴散的阻礙。 實施方式 -10- (4) 1283029
克服基板令有凹陷之問題的方式為，-直等待直到去除 氮化物抗反射塗層(ARC)之後’促使所發生的凹陷較不合， 響到移動中的源極和汲極，使源極和㈣非常接近間極介 電亚且重疊於閘極。-種達成此目的之方式為，在去料 化物抗反射塗層（规）之#，先等待直到用於遮罩高漠度源 極/汲極區植入的側壁間隔堆疊適當定位。在替代方案中，
在用於源極/汲極延伸植入的側壁間隔形式之後去除氮化
物抗反射塗層(ARC)，並且在此情況下使用濕式蝕刻去除氮 化物抗反射塗層（ARC)。 A 圖10顯示已形成一側壁間隔70的裝置60，這是圖2所示之 結構的替代方案。圖10所示的結構採用圖丨所示的裝置結構 。裝置60包含一基板62、一閘極64(可能係以多晶矽為材料 所製成，並且屬於圖案化傳導層類型）、一閘極氧化物6/、 一抗反射塗層（ARC)16(可能是氮化物）及一側壁間隔7〇。較 佳方式為，基板62之材料是矽，並且側壁間隔7〇之材料是 氧化物。抗反射塗層（ARC)16也可能屬於非氮化物的其他= 效抗反射材料。閘極64也可能是非多晶矽之材料。側壁間 隔70係從各向異性蝕刻之相對保角的氧化物層所產生。這 項各向異性餘刻的結果是基板62中的凹陷7 1。這是必然的 過度姓刻以確保除要形成侧壁間隔的位置外去除用於形成 側壁間隔的所有層的後果。由於只會在過度蝕刻時間才會 曝露基板，所以凹陷相對較小。圖Η顯示在源極/汲極延伸 植入以形成源極/没極區72和源極/汲極區74以鄰接環繞閑 極64的側壁間隔70之後的裝置60。 -11- 1283029
(5) 圖12顯不形成襯墊76、一層78及一層8〇之後的裝置6〇。 層76、78和80通常都是介電材料。最佳方式為，層％是氧 化物，層78是氮化物，而層8〇是氧化物，而不是可能是非 曰曰石夕的典型介電材料。圖13顯示使用各向異性蝕刻從層80 所形成的側壁間隔82。這會曝露位於鄰接側壁間隔82之區 域中的氮化物層78及當做一襯墊之層76之一部份，其中側 土間隔82包含一位於閘極64和抗反射塗層（arc)68上方的 區域。圖14顯示已執行氮化物蝕刻以便去除未被覆蓋之層 78—部份而留下閘極64之氮化物部份抖之後的裝置。這 也具有去除位於抗反射塗層（ARC)68上方之層76部份而留 下層76之部份86的作用。在這項製程期間，區域”和往 對方方向擴散，並且往閘極64方向擴散。由於基板62的凹 陷量相當小，所以擴散製程有效克服該小量凹陷。繼續去 除氮化物，直到已去除抗反射塗層（ARC)68，這也會減少側 j間隔84的咼度而留下側壁間隔88。側壁間隔88稍微低於 多晶矽64，這是由於確信已去除所有抗反射塗層（arc)68 所需的過度蝕刻的結果。在基板62中沿著該侧壁間隔”的 相對大凹陷主要發生於蝕刻抗反射塗層（A R c) 6 8期間。這項 蝕刻較佳為乾式蝕刻，這是因為乾式蝕刻的缺陷特性優於 :式蝕刻的缺陷特性。如果已使用濕式蝕刻，則乾式蝕刻 ^在基板62中產生較大的凹陷。然而在此情況下，相對差 異不是材料，這是因為會從對源極/汲極區72和74變成重疊 於閘極64之能力造成負面影響的區域大量去除凹陷。且 圖16顯不使用高濃度源極/汲極植入以沿著當做植入遮 1283029
頌不為由於形成侧壁間隔122和124所發生的電晶體，類似 於圖10。因此，圖19中將基板112表面中的凹陷標示為134 和136。该凹陷係在形成側壁間隔丨22時過度蝕刻所造成。 圖20頦示已使用濕式蝕刻去除抗反射塗層（arc) 126和夏μ 之後的裝置結構11 〇。藉由使用濕式蝕刻，圖2〇中所示的凹 13 4和13 6顯著小於使用乾式餘刻的造成的凹陷。典型的 濕式蝕刻化學作用是磷酸。適用於氮化物的典型乾式蝕刻 疋CF4+HBO。在此情況下適用使用濕式|虫刻，這是因為 側土間隔122會保護層間介電120。在沒有側壁間隔122保護 層間介電120情況卞使用濕式蝕刻時，將會使層間介電12〇 降級，並且會造成儲存元件114與控制閘極118之間的問題 。在儲存元件Π 4(圖中描繪成浮動閘極）與控制閘極1丨8之間 的沒有洩漏電流極為重要。在側壁間隔122保護之下，濕式 蝕刻不會損壞層間介電12〇。這也呈現出已去除抗反射塗層 (ARC) 128所產生的電晶體in。 圖21顯示使用側壁間隔122當做遮罩及使用側壁間隔124 當做遮罩進行延伸植入之後的裝置結構11〇。產生的源極/ 汲極延伸區138、140、142和144被形成。圖22顯示沈積一 襯墊146和一氮化物層148之後的裝置結構110。接著以各向 異性方式姓刻氮化物層14 8 ’以構成側壁間隔1 5 〇和側壁間 隔152。在形成侧壁間隔150和152過程中去除氮化物層148 而曝露的襯墊146區域實質上被去除（如果不徹底去除）。圖 24顯示使用侧壁間隔150和152當做光罩以高濃度植入而構 成高濃度植摻雜的區域1 5 4、15 6、1 5 8和1 6 0之後的裝置会士 -14- 1283029 ⑻ 構 110 〇 圖25顯示石夕化物形成以形成矽化物區170、172、174和176 之後的裝置結構110。因此，源極/汲極區142和144已被矽 化物區170、172、174和176大量消耗。同樣地，閘極區1 μ 矛116已刀別被石夕化物區1 & 4和16 8消耗一些。這會留下電晶 體111的多晶矽部份167及電晶體113的多晶矽部份166。源 極/汲極部份178、180、182和184擴大並擴散而足以重疊於 閘極區167和166，雖然需要克服因去除抗反射塗層（ARC) 所U成的凹卩曰。由於係藉由濕式蝕刻來去除抗反射塗層 (ARC)，所以凹陷量顯著小於乾式蝕刻的凹陷。雖然乾式蝕 刻較適σ，但疋與標準電晶體相比，充分重疊對非揮發性 d憶體而言更為重要。因此’為了使源極/沒極區適當重疊 ，洋動閘極（已儲存電荷的區域）之間重疊更加重要。再者， 與圖1至圖9所示之在形成側壁間隔之前去除抗反射塗層 (ARC)的情況相比，藉由在形成侧壁間隔122之後去除抗反 射塗層（ARC)，EJ陷位置的影響較不嚴重。就圖i至圖9而言 ’去除抗反射塗層（ARC)之後才會形成側壁間隔24。 圖1到圖9顯示根據先前技術之半導體裝置的連續斷面 圖； 圖10到圖18顯示根據本發明的一 J項具體貫施例之半導體 裝置的連續斷面圖；以及 圖19到圖25顯示根據本發明的ψ 乃的另一項具體實施例之半導 體裝置的連續斷面圖。 ’ -15- 1283029 (9) 發明說_ 麵 圖式代表符號說明 10,60,110 12,62，112 16,68，126，128 22,134,136 26,28,72,74,90， 92，142，144，100， 102，154，156，158, 160，178，180，182, 184 半導體裝置 基板 抗反射塗層（ARC) 凹陷 源極/没極區 14,44,64，114，116 閘極 24,34,70,82,84， 側壁間隔. 885122，124，150， 152 氧化物概墊 襯墊 氮化物層 襯墊部份 區域 矽化物區
30 146 32,148 38 40,42,49,51 48,46,50,94,961, 172，174，176，164, 168 20,66,130,132 閘極氧化物 111 非揮發性記憶體（NVM)電晶體 -16- 1283029 (10) 113 標準電晶體 114 浮動閘極（儲存元件） 120 層間介電 118 控制閘極 138,140,142,144 源極/汲極延伸區 166,167 多晶矽部份 -17-

Claims (1)

1283029 莎年jljij (日修(擎正替換頁 第〇921〇5907號專利申請案 中文申請專利範圍替換本(95年12月） 拾、申請專利範圍 1. 2. 一種用以形成一積體電路裝置的方法，包括： 提供一半導體基板； 在該半導體基板上形成一圖案化介電層； 在該圖案化介電層上形成一圖案化導電層； 在該圖案化導電層上形成一抗反射塗層（arc); 在該圖案化介電層及該圖案化導電層上形成一第一介 電層； 在該第一介電層上形成一第二介電層； 在該第二介電層上形成一第一層； 去除該第一層之部份以構成一第一圖案化層，其中該 第一圖案化層鄰接於該圖案化導電層及該圖案化介電 層； 去除該第二介電層之部份以構成鄰接於該第一圖宰化 層的第一介電區； ¥ :除該第一介電層之部份以構成鄰接於該第區 的弟二介電區；以及 去除該第一介電層之部份之後去除抗反射塗層障)。 申凊專利範圍第1項之方法，進一步包括： 在該第一層上形成一第二層； 對該第一層選擇性去除哕 接於該第一Η^μ g Μ第一層之一部份，以構成鄰 U第圖案化層的第 如申請專利_第2項之方^之^圖案化部份。 (ARC)是一乾式製程。凌，其中去除該抗反射塗層 3. 1283029
4·如申請專利範圍第2項之方法，复 ，該第-層是一氮化物 ：第-層疋-乳化物 第-介電層是-氧化物。，1電層是-氧化物及該 5. 如申請專利範圍第4項 # ^ 方去進一步包括去除該第二層 之口Ρ伤’其中該第二層是非晶矽。 6. 如申請專利範圍第丨項之方 i 化物，該第二介電声是亥弟一介電層是-氧 物。 疋―"化物，及該第-層是-氧化 其中去除該抗反射塗層
7·如申請專利範圍第6項之方法 (ARC)是一濕式製程。 8. —種積體電路裝置，包括·· 一半導體基板； 一堆疊，包括： 一形成在該半導體基板上的圖案化介電層； 一形成在該圖案化介電層上的圖案化導電層，· 一第一側壁；以及
一第二側壁，其中該第二側壁係鄰接於該第一侧壁，· 一第一電極區，其位於該半導體基板内並且鄰接於該 第一側壁； 、w 一第二電極區，其位於該半導體基板内並且鄰接於該 第二側壁； 、以 一通道區，其介於該第一電極區與該第二電極區之間 ，並且位於該堆疊下方； 氧化物間隔，其鄰接於該第一側壁及該第二側壁，其 -2- 1283029
T该寺氧化物間隔具有印⑺叹， 絕緣層，其鄰接於該等氧化物間隔，並且位於一 電極區與該第二電極區上方；以及 ^ 一 氮化物間隔，其鄰接於該等氧化物間隔 化物間隔具有_第_古序外性亥#虱 弟一间度，该第二高度小於該第一高度 9· 一種積體電路裝置，包括·· 一具有一頂面之半導體基板； 一形成於該半導體基板上之堆疊，包括： 一第一層； 一形成在該第一層上之第二層； 一第一側壁； 一與該第一側壁相對之第二側壁； 門隔4鄰接於該第一側壁及該第二側壁，#中該半 導體基板頂面之_第_部份位於該等間隔下方，一第二 部份位於該堆疊下方，且該第一部份實質上與該第二部 份共面； 一絕緣層’其鄰接於該等間隔，其中該基板頂面之一第 三部份位於該等絕緣層下方，並且相關於該基板之第一 部份及第二部份而凹入； 一第一摻雜區，其位於該半導體基板内，並且鄰接於 該第一側壁； 第一摻雜區，其位於該半導體基板内，並且鄰接於 該第二側壁；及 1283029
一通道區，其位於該第一摻雜區與該第二摻雜區之間 ’並且位於該半導體基板内。
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100488099B1 (ko) * 2002-11-18 2005-05-06 한국전자통신연구원 쇼오트 채널 모오스 트랜지스터 및 그 제조 방법
US6884712B2 (en) * 2003-02-07 2005-04-26 Chartered Semiconductor Manufacturing, Ltd. Method of manufacturing semiconductor local interconnect and contact
US6913980B2 (en) * 2003-06-30 2005-07-05 Texas Instruments Incorporated Process method of source drain spacer engineering to improve transistor capacitance
JP2005109381A (ja) * 2003-10-02 2005-04-21 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US7229885B2 (en) * 2004-01-06 2007-06-12 International Business Machines Corporation Formation of a disposable spacer to post dope a gate conductor
US7064396B2 (en) * 2004-03-01 2006-06-20 Freescale Semiconductor, Inc. Integrated circuit with multiple spacer insulating region widths
US8896048B1 (en) * 2004-06-04 2014-11-25 Spansion Llc Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7170130B2 (en) * 2004-08-11 2007-01-30 Spansion Llc Memory cell with reduced DIBL and Vss resistance
KR100668954B1 (ko) * 2004-12-15 2007-01-12 동부일렉트로닉스 주식회사 박막트랜지스터 제조 방법
KR100685575B1 (ko) * 2004-12-28 2007-02-22 주식회사 하이닉스반도체 반도체 소자의 스텝 채널 형성 방법
US7544553B2 (en) * 2005-03-30 2009-06-09 Infineon Technologies Ag Integration scheme for fully silicided gate
US20070007578A1 (en) * 2005-07-07 2007-01-11 Li Chi N B Sub zero spacer for shallow MDD junction to improve BVDSS in NVM bitcell
US8159030B2 (en) * 2005-11-30 2012-04-17 Globalfoundries Inc. Strained MOS device and methods for its fabrication
KR100741908B1 (ko) * 2005-12-30 2007-07-24 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7317222B2 (en) * 2006-01-27 2008-01-08 Freescale Semiconductor, Inc. Memory cell using a dielectric having non-uniform thickness
JP4799217B2 (ja) * 2006-03-03 2011-10-26 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2008098567A (ja) * 2006-10-16 2008-04-24 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US7745344B2 (en) * 2007-10-29 2010-06-29 Freescale Semiconductor, Inc. Method for integrating NVM circuitry with logic circuitry
KR101815527B1 (ko) * 2010-10-07 2018-01-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN102420116B (zh) * 2011-06-07 2013-12-04 上海华力微电子有限公司 消除栅极凹形缺陷的方法
JP5715551B2 (ja) * 2011-11-25 2015-05-07 株式会社東芝 半導体装置およびその製造方法
CN104752223B (zh) * 2013-12-31 2017-12-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9647116B1 (en) * 2015-10-28 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating self-aligned contact in a semiconductor device
US11653498B2 (en) * 2017-11-30 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US6066567A (en) 1997-12-18 2000-05-23 Advanced Micro Devices, Inc. Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
US6087271A (en) 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. Methods for removal of an anti-reflective coating following a resist protect etching process
US5902125A (en) 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US5972762A (en) 1998-01-05 1999-10-26 Texas Instruments--Acer Incorporated Method of forming mosfets with recessed self-aligned silicide gradual S/D junction
US6245682B1 (en) 1999-03-11 2001-06-12 Taiwan Semiconductor Manufacturing Company Removal of SiON ARC film after poly photo and etch
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
JP2003519910A (ja) 1999-12-30 2003-06-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 埋れ反射防止膜を除去するための改良された方法
US6156126A (en) 2000-01-18 2000-12-05 United Microelectronics Corp. Method for reducing or avoiding the formation of a silicon recess in SDE junction regions
US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US6368947B1 (en) * 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6555865B2 (en) * 2001-07-10 2003-04-29 Samsung Electronics Co. Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US6818504B2 (en) * 2001-08-10 2004-11-16 Hynix Semiconductor America, Inc. Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications
US6812515B2 (en) * 2001-11-26 2004-11-02 Hynix Semiconductor, Inc. Polysilicon layers structure and method of forming same

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AU2003225792A1 (en) 2003-10-08
JP2005531919A (ja) 2005-10-20
US6753242B2 (en) 2004-06-22
EP1485948A1 (en) 2004-12-15
US20030181028A1 (en) 2003-09-25
US6846716B2 (en) 2005-01-25
CN1643671A (zh) 2005-07-20
TW200305954A (en) 2003-11-01
WO2003081660A1 (en) 2003-10-02
CN100339961C (zh) 2007-09-26
US20040124450A1 (en) 2004-07-01
KR20040097188A (ko) 2004-11-17

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