KR100716075B1 - 반도체 집적 회로 장치의 제조 방법 - Google Patents

반도체 집적 회로 장치의 제조 방법 Download PDF

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Publication number
KR100716075B1
KR100716075B1 KR1020010003154A KR20010003154A KR100716075B1 KR 100716075 B1 KR100716075 B1 KR 100716075B1 KR 1020010003154 A KR1020010003154 A KR 1020010003154A KR 20010003154 A KR20010003154 A KR 20010003154A KR 100716075 B1 KR100716075 B1 KR 100716075B1
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South Korea
Prior art keywords
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insulating film
film
isolation trench
semiconductor substrate
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Expired - Fee Related
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KR1020010003154A
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English (en)
Korean (ko)
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KR20010076387A (ko
Inventor
사또우히데노리
스즈끼노리오
다까마쯔아끼라
마루야마히로유끼
사이까와다께시
호쯔따가쯔히꼬
이나조에히로유끼
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
가부시기가이샤 히다치초엘에스아이시스템즈
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Publication of KR20010076387A publication Critical patent/KR20010076387A/ko
Application granted granted Critical
Publication of KR100716075B1 publication Critical patent/KR100716075B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H10D89/105—Integrated device layouts adapted for thermal considerations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
KR1020010003154A 2000-01-20 2001-01-19 반도체 집적 회로 장치의 제조 방법 Expired - Fee Related KR100716075B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000012026A JP2001203263A (ja) 2000-01-20 2000-01-20 半導体集積回路装置の製造方法および半導体集積回路装置
JP2000-012026 2000-01-20

Related Child Applications (2)

Application Number Title Priority Date Filing Date
KR1020060080347A Division KR100719015B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법
KR1020060080350A Division KR100719429B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법

Publications (2)

Publication Number Publication Date
KR20010076387A KR20010076387A (ko) 2001-08-11
KR100716075B1 true KR100716075B1 (ko) 2007-05-08

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Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020010003154A Expired - Fee Related KR100716075B1 (ko) 2000-01-20 2001-01-19 반도체 집적 회로 장치의 제조 방법
KR1020060080350A Expired - Fee Related KR100719429B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법
KR1020060080347A Expired - Fee Related KR100719015B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법

Family Applications After (2)

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KR1020060080350A Expired - Fee Related KR100719429B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법
KR1020060080347A Expired - Fee Related KR100719015B1 (ko) 2000-01-20 2006-08-24 반도체 집적 회로 장치의 제조 방법

Country Status (4)

Country Link
US (5) US6693008B1 (enExample)
JP (1) JP2001203263A (enExample)
KR (3) KR100716075B1 (enExample)
TW (1) TW477061B (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096065A (ja) * 2002-07-08 2004-03-25 Renesas Technology Corp 半導体記憶装置およびその製造方法
DE10261807A1 (de) 2002-12-19 2004-07-01 Turicum Drug Development Ag Deuterierte Catecholaminderivate sowie diese Verbindungen enthaltende Arzneimittel
US7214595B2 (en) * 2003-06-27 2007-05-08 Kabushiki Kaisha Toshiba Method of producing semiconductor devices
JP2005166700A (ja) 2003-11-28 2005-06-23 Toshiba Corp 半導体装置及びその製造方法
US7037840B2 (en) * 2004-01-26 2006-05-02 Micron Technology, Inc. Methods of forming planarized surfaces over semiconductor substrates
JP2005332885A (ja) 2004-05-18 2005-12-02 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP2006196843A (ja) * 2005-01-17 2006-07-27 Toshiba Corp 半導体装置およびその製造方法
JP2006286720A (ja) * 2005-03-31 2006-10-19 Toshiba Corp 半導体装置およびその製造方法
JP4955222B2 (ja) 2005-05-20 2012-06-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2006351694A (ja) * 2005-06-14 2006-12-28 Fujitsu Ltd 半導体装置およびその製造方法
US7811935B2 (en) * 2006-03-07 2010-10-12 Micron Technology, Inc. Isolation regions and their formation
JP2007335807A (ja) * 2006-06-19 2007-12-27 Toshiba Corp 半導体装置の製造方法
KR100816749B1 (ko) * 2006-07-12 2008-03-27 삼성전자주식회사 소자분리막, 상기 소자분리막을 구비하는 비휘발성 메모리소자, 그리고 상기 소자분리막 및 비휘발성 메모리 소자형성 방법들
US7696057B2 (en) * 2007-01-02 2010-04-13 International Business Machines Corporation Method for co-alignment of mixed optical and electron beam lithographic fabrication levels
US8129816B2 (en) * 2007-06-20 2012-03-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20090004839A1 (en) * 2007-06-28 2009-01-01 Hynix Semiconductor Inc. Method for fabricating an interlayer dielectric in a semiconductor device
WO2009079460A1 (en) * 2007-12-14 2009-06-25 University Of Florida Research Foundation, Inc. Electrothermal microactuator for large vertical displacement without tilt or lateral shift
JP4823248B2 (ja) * 2008-02-15 2011-11-24 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5841306B2 (ja) 2009-05-08 2016-01-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TWI396259B (zh) * 2009-08-28 2013-05-11 Inotera Memories Inc 動態隨機存取記憶體之凹溝渠通道之自我對準方法
CN102822959B (zh) 2010-03-30 2015-01-28 瑞萨电子株式会社 半导体器件及其制造方法
KR101177996B1 (ko) * 2010-10-15 2012-08-28 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
JP5859758B2 (ja) * 2011-07-05 2016-02-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9121237B2 (en) 2011-07-28 2015-09-01 Baker Hughes Incorporated Methods of coating wellbore tools and components having such coatings
US8697537B2 (en) * 2012-02-01 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning for a semiconductor device
US8603895B1 (en) * 2012-09-11 2013-12-10 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence
CN105765703B (zh) * 2013-12-23 2021-02-23 英特尔公司 在多个鳍状物间距结构当中的笔直、高和一致的鳍状物的蚀刻技术
US9559184B2 (en) 2015-06-15 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Devices including gate spacer with gap or void and methods of forming the same
KR102404642B1 (ko) * 2015-07-17 2022-06-03 삼성전자주식회사 반도체 소자 및 이의 제조방법
US9847245B1 (en) * 2016-06-16 2017-12-19 Samsung Electronics Co., Ltd. Filling processes
CN108281354B (zh) * 2017-01-06 2022-07-12 联华电子股份有限公司 平坦化方法
CN109390338B (zh) * 2017-08-08 2021-06-22 联华电子股份有限公司 互补式金属氧化物半导体元件及其制作方法
CN109817521B (zh) * 2017-11-21 2022-04-12 联华电子股份有限公司 用来改善平坦化负载效应的半导体制作工艺
JP2022094651A (ja) * 2020-12-15 2022-06-27 キオクシア株式会社 半導体装置および半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0165462B1 (ko) * 1995-10-28 1999-02-01 김광호 트렌치 소자 분리 방법

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US182798A (en) * 1876-10-03 Improvement in machines for winding spiral studs
JPS6020530A (ja) * 1983-07-14 1985-02-01 Nec Corp 素子分離領域の形成方法
JPS62133733A (ja) * 1985-12-05 1987-06-16 Nec Corp 半導体集積回路装置
EP0232748A1 (de) * 1986-01-22 1987-08-19 Siemens Aktiengesellschaft Verfahren zur Auffüllung von Isolationsgräben in integrierten Halbleiterschaltungen
US4994231A (en) 1990-03-22 1991-02-19 The Babcock & Wilcox Company Apparatus for blending constituents of varying densities
US5098856A (en) * 1991-06-18 1992-03-24 International Business Machines Corporation Air-filled isolation trench with chemically vapor deposited silicon dioxide cap
JPH05114646A (ja) 1991-10-24 1993-05-07 Fujitsu Ltd 半導体装置の製造方法
US5270264A (en) * 1991-12-20 1993-12-14 Intel Corporation Process for filling submicron spaces with dielectric
JPH05235157A (ja) 1992-02-26 1993-09-10 Fujitsu Ltd 半導体装置の製造方法
JPH064776A (ja) 1992-06-19 1994-01-14 Omron Corp 電子式キャッシュレジスタ
KR950009888B1 (ko) 1992-08-14 1995-09-01 삼성전자 주식회사 반도체장치의 제조방법
US5292689A (en) 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
JPH07326659A (ja) 1994-06-02 1995-12-12 Hitachi Ltd 半導体集積回路装置の製造方法
JP2671828B2 (ja) 1994-10-28 1997-11-05 日本電気株式会社 半導体装置の製造方法
JPH08148559A (ja) * 1994-11-15 1996-06-07 Fujitsu Ltd 絶縁膜を有する半導体装置の製造方法
US5960300A (en) * 1994-12-20 1999-09-28 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
KR0155874B1 (ko) * 1995-08-31 1998-12-01 김광호 반도체장치의 평탄화방법 및 이를 이용한 소자분리방법
US5827782A (en) * 1996-06-03 1998-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple etch method for optimizing Inter-Metal Dielectric (IMD) spacer layer profile
US6060352A (en) * 1996-08-09 2000-05-09 Hitachi, Ltd. Method of manufacturing semiconductor device with increased focus margin
EP0851463A1 (en) 1996-12-24 1998-07-01 STMicroelectronics S.r.l. Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices
JPH10209266A (ja) * 1997-01-27 1998-08-07 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5854125A (en) * 1997-02-24 1998-12-29 Vlsi Technology, Inc. Dummy fill patterns to improve interconnect planarity
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
TW454339B (en) * 1997-06-20 2001-09-11 Hitachi Ltd Semiconductor integrated circuit apparatus and its fabricating method
JP3519579B2 (ja) * 1997-09-09 2004-04-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP3309783B2 (ja) * 1997-10-31 2002-07-29 日本電気株式会社 半導体装置の製造方法
JP3718034B2 (ja) 1997-11-11 2005-11-16 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3697044B2 (ja) * 1997-12-19 2005-09-21 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP3686248B2 (ja) * 1998-01-26 2005-08-24 株式会社日立製作所 半導体集積回路装置およびその製造方法
US6111086A (en) * 1998-02-27 2000-08-29 Scaringe; Stephen A. Orthoester protecting groups
JP3718058B2 (ja) * 1998-06-17 2005-11-16 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
KR100319185B1 (ko) * 1998-07-31 2002-01-04 윤종용 반도체 장치의 절연막 형성 방법
TW408432B (en) * 1998-08-25 2000-10-11 United Microelectronics Corp The manufacture method of shallow trench isolation
JP2000156480A (ja) 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
EP0996145A3 (en) * 1998-09-04 2000-11-08 Canon Kabushiki Kaisha Process for producing semiconductor substrate
JP2000114362A (ja) * 1998-10-02 2000-04-21 Nec Corp 半導体装置の製造方法
JP2000183150A (ja) * 1998-12-11 2000-06-30 Matsushita Electronics Industry Corp 半導体装置の製造方法
US6133105A (en) * 1999-04-27 2000-10-17 United Microelectronics Corp. Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure
US6255649B1 (en) * 1999-07-29 2001-07-03 Xerox Corporation Charging device with grid tensioning shafts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0165462B1 (ko) * 1995-10-28 1999-02-01 김광호 트렌치 소자 분리 방법

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US20050237603A1 (en) 2005-10-27
US20050239257A1 (en) 2005-10-27
KR100719015B1 (ko) 2007-05-16
KR20060096975A (ko) 2006-09-13
KR100719429B1 (ko) 2007-05-18
JP2001203263A (ja) 2001-07-27
US7208391B2 (en) 2007-04-24
US6693008B1 (en) 2004-02-17
US7060589B2 (en) 2006-06-13
TW477061B (en) 2002-02-21
KR20060097096A (ko) 2006-09-13
US7074691B2 (en) 2006-07-11
US20040106292A1 (en) 2004-06-03
US20050148155A1 (en) 2005-07-07
KR20010076387A (ko) 2001-08-11

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