KR100474626B1 - 불휘발성 반도체 기억 장치의 프로그램 방법 - Google Patents

불휘발성 반도체 기억 장치의 프로그램 방법 Download PDF

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Publication number
KR100474626B1
KR100474626B1 KR10-2002-0024957A KR20020024957A KR100474626B1 KR 100474626 B1 KR100474626 B1 KR 100474626B1 KR 20020024957 A KR20020024957 A KR 20020024957A KR 100474626 B1 KR100474626 B1 KR 100474626B1
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KR
South Korea
Prior art keywords
memory cell
twin
voltage
control gate
bit line
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Expired - Fee Related
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KR10-2002-0024957A
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English (en)
Korean (ko)
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KR20030009119A (ko
Inventor
가나이마사히로
가메이데루히꼬
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세이코 엡슨 가부시키가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR10-2002-0024957A 2001-05-11 2002-05-07 불휘발성 반도체 기억 장치의 프로그램 방법 Expired - Fee Related KR100474626B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001141616A JP2002334588A (ja) 2001-05-11 2001-05-11 不揮発性半導体記憶装置のプログラム方法
JPJP-P-2001-00141616 2001-05-11

Publications (2)

Publication Number Publication Date
KR20030009119A KR20030009119A (ko) 2003-01-29
KR100474626B1 true KR100474626B1 (ko) 2005-03-08

Family

ID=18988043

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0024957A Expired - Fee Related KR100474626B1 (ko) 2001-05-11 2002-05-07 불휘발성 반도체 기억 장치의 프로그램 방법

Country Status (5)

Country Link
US (1) US6587380B2 (enExample)
EP (1) EP1256959A3 (enExample)
JP (1) JP2002334588A (enExample)
KR (1) KR100474626B1 (enExample)
CN (1) CN1228784C (enExample)

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JP3716914B2 (ja) 2001-05-31 2005-11-16 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3843869B2 (ja) 2002-03-15 2006-11-08 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3821032B2 (ja) * 2002-03-20 2006-09-13 セイコーエプソン株式会社 ファイルストレージ型不揮発性半導体記憶装置
JP3867624B2 (ja) 2002-06-06 2007-01-10 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3815381B2 (ja) * 2002-06-06 2006-08-30 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
KR100475119B1 (ko) * 2002-11-26 2005-03-10 삼성전자주식회사 Ｓｏｎｏｓ 셀이 채용된 ｎｏｒ 형 플래시 메모리 소자의동작 방법
JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
JP3587842B2 (ja) 2002-12-17 2004-11-10 沖電気工業株式会社 データ書き換え装置およびデータ書き換え方法ならびにフラッシュメモリ装置
JP3985689B2 (ja) * 2003-02-21 2007-10-03 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004265508A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 不揮発性半導体記憶装置
JP3786095B2 (ja) * 2003-02-28 2006-06-14 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3873908B2 (ja) * 2003-02-28 2007-01-31 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
JP4426868B2 (ja) * 2003-04-04 2010-03-03 株式会社ルネサステクノロジ 不揮発性半導体記憶装置および半導体集積回路装置
US6982892B2 (en) * 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
JP3767588B2 (ja) * 2003-08-29 2006-04-19 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
JP4196191B2 (ja) * 2003-09-09 2008-12-17 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
US7447077B2 (en) * 2005-08-05 2008-11-04 Halo Lsi, Inc. Referencing scheme for trap memory
US8138540B2 (en) * 2005-10-24 2012-03-20 Macronix International Co., Ltd. Trench type non-volatile memory having three storage locations in one memory cell
JP5311784B2 (ja) * 2006-10-11 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
KR101618677B1 (ko) * 2008-07-01 2016-05-09 엘에스아이 코포레이션 플래시 메모리 제어기와 플래시 메모리 어레이 사이의 인터페이싱 방법 및 인터페이스
US8611169B2 (en) * 2011-12-09 2013-12-17 International Business Machines Corporation Fine granularity power gating
CN103778948A (zh) * 2014-01-09 2014-05-07 上海华虹宏力半导体制造有限公司 存储器阵列的控制方法
US9881683B1 (en) 2016-12-13 2018-01-30 Cypress Semiconductor Corporation Suppression of program disturb with bit line and select gate voltage regulation
JP2019057335A (ja) * 2017-09-19 2019-04-11 東芝メモリ株式会社 半導体記憶装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5364806A (en) * 1991-08-29 1994-11-15 Hyundai Electronics Industries Co., Ltd. Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell
KR19990061327A (ko) * 1997-12-31 1999-07-26 윤종용 듀얼비트 게이트 분리형 플래쉬 메모리소자 및 그의구동방법
KR20010004269A (ko) * 1999-06-28 2001-01-15 김영환 플래쉬 메모리 셀 어레이 구조 및 데이터 기록 방법
KR20010036298A (ko) * 1999-10-07 2001-05-07 김영환 비휘발성 메모리소자와 그의 셀어레이 및 그의 데이타 센싱방법

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US4723225A (en) * 1985-10-15 1988-02-02 Texas Instruments Incorporated Programming current controller
JPH07161851A (ja) 1993-12-10 1995-06-23 Sony Corp 半導体不揮発性記憶装置およびその製造方法
US5408115A (en) 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
US5422504A (en) 1994-05-02 1995-06-06 Motorola Inc. EEPROM memory device having a sidewall spacer floating gate electrode and process
US5870335A (en) * 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells
JPH118324A (ja) * 1997-04-23 1999-01-12 Sanyo Electric Co Ltd トランジスタ、トランジスタアレイおよび不揮発性半導体メモリ
JPH1131393A (ja) * 1997-05-15 1999-02-02 Sanyo Electric Co Ltd 不揮発性半導体記憶装置
US5969383A (en) 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
US5851881A (en) * 1997-10-06 1998-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making monos flash memory for multi-level logic
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6255166B1 (en) 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP4058219B2 (ja) * 1999-09-17 2008-03-05 株式会社ルネサステクノロジ 半導体集積回路
US6177318B1 (en) 1999-10-18 2001-01-23 Halo Lsi Design & Device Technology, Inc. Integration method for sidewall split gate monos transistor
US6248633B1 (en) 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
JP2001357681A (ja) * 2000-06-12 2001-12-26 Sony Corp 半導体記憶装置およびその駆動方法
JP2001357682A (ja) * 2000-06-12 2001-12-26 Sony Corp メモリシステムおよびそのプログラム方法
DE60133619T2 (de) * 2000-12-05 2009-06-10 Halo Lsi Design And Device Technology Inc. Programmier- und Löschverfahren in Zwilling-MONOS-Zellenspeichern
ATE458249T1 (de) * 2001-03-15 2010-03-15 Halo Inc Doppelbit monos speicherzellgebrauch für breite programbandbreite
JP4715024B2 (ja) * 2001-05-08 2011-07-06 セイコーエプソン株式会社 不揮発性半導体記憶装置のプログラム方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5364806A (en) * 1991-08-29 1994-11-15 Hyundai Electronics Industries Co., Ltd. Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell
KR19990061327A (ko) * 1997-12-31 1999-07-26 윤종용 듀얼비트 게이트 분리형 플래쉬 메모리소자 및 그의구동방법
KR20010004269A (ko) * 1999-06-28 2001-01-15 김영환 플래쉬 메모리 셀 어레이 구조 및 데이터 기록 방법
KR20010036298A (ko) * 1999-10-07 2001-05-07 김영환 비휘발성 메모리소자와 그의 셀어레이 및 그의 데이타 센싱방법

Also Published As

Publication number Publication date
US20030002343A1 (en) 2003-01-02
US6587380B2 (en) 2003-07-01
JP2002334588A (ja) 2002-11-22
CN1228784C (zh) 2005-11-23
CN1391231A (zh) 2003-01-15
EP1256959A3 (en) 2003-10-01
KR20030009119A (ko) 2003-01-29
EP1256959A2 (en) 2002-11-13

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