KR100329243B1 - 집적 회로 장치 - Google Patents
집적 회로 장치 Download PDFInfo
- Publication number
- KR100329243B1 KR100329243B1 KR1019990017075A KR19990017075A KR100329243B1 KR 100329243 B1 KR100329243 B1 KR 100329243B1 KR 1019990017075 A KR1019990017075 A KR 1019990017075A KR 19990017075 A KR19990017075 A KR 19990017075A KR 100329243 B1 KR100329243 B1 KR 100329243B1
- Authority
- KR
- South Korea
- Prior art keywords
- clock signal
- signal
- circuit
- clock
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP98-184483 | 1998-06-30 | ||
| JP18448398A JP4178225B2 (ja) | 1998-06-30 | 1998-06-30 | 集積回路装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000005652A KR20000005652A (ko) | 2000-01-25 |
| KR100329243B1 true KR100329243B1 (ko) | 2002-03-18 |
Family
ID=16153974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990017075A Expired - Lifetime KR100329243B1 (ko) | 1998-06-30 | 1999-05-13 | 집적 회로 장치 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6266294B1 (enExample) |
| JP (1) | JP4178225B2 (enExample) |
| KR (1) | KR100329243B1 (enExample) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4489231B2 (ja) * | 2000-02-23 | 2010-06-23 | 富士通マイクロエレクトロニクス株式会社 | 遅延時間調整方法と遅延時間調整回路 |
| JP4649081B2 (ja) * | 2000-10-02 | 2011-03-09 | キヤノン株式会社 | 周辺機器、その制御方法、プログラムおよび記憶媒体 |
| US6480439B2 (en) * | 2000-10-03 | 2002-11-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6898683B2 (en) * | 2000-12-19 | 2005-05-24 | Fujitsu Limited | Clock synchronized dynamic memory and clock synchronized integrated circuit |
| KR100413758B1 (ko) * | 2001-03-26 | 2003-12-31 | 삼성전자주식회사 | 지연 동기 루프를 구비하는 반도체 메모리 장치 |
| KR100422572B1 (ko) * | 2001-06-30 | 2004-03-12 | 주식회사 하이닉스반도체 | 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자 |
| US6832327B1 (en) * | 2001-10-02 | 2004-12-14 | Advanced Micro Devices, Inc. | Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system |
| US6678205B2 (en) * | 2001-12-26 | 2004-01-13 | Micron Technology, Inc. | Multi-mode synchronous memory device and method of operating and testing same |
| JP2003228982A (ja) | 2002-01-29 | 2003-08-15 | Hitachi Ltd | 半導体集積回路装置 |
| KR100470995B1 (ko) * | 2002-04-23 | 2005-03-08 | 삼성전자주식회사 | 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법 |
| US6765433B1 (en) * | 2003-03-20 | 2004-07-20 | Atmel Corporation | Low power implementation for input signals of integrated circuits |
| KR100560297B1 (ko) * | 2003-10-29 | 2006-03-10 | 주식회사 하이닉스반도체 | 지연고정루프용 전원 공급 회로를 구비한 반도체 소자 |
| KR100540487B1 (ko) * | 2003-10-31 | 2006-01-10 | 주식회사 하이닉스반도체 | 데이터 출력제어회로 |
| KR100571651B1 (ko) * | 2003-12-29 | 2006-04-17 | 주식회사 하이닉스반도체 | 파워다운 모드의 안정적인 탈출을 위한 제어회로 |
| KR100808052B1 (ko) * | 2005-09-28 | 2008-03-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| US7429871B2 (en) * | 2005-09-29 | 2008-09-30 | Hynix Semiconductor Inc. | Device for controlling on die termination |
| JP4524662B2 (ja) * | 2005-10-21 | 2010-08-18 | エルピーダメモリ株式会社 | 半導体メモリチップ |
| KR100702766B1 (ko) * | 2005-12-07 | 2007-04-03 | 주식회사 하이닉스반도체 | 안정적인 dll용 내부 전압을 생성하는 내부 전압발생기와 이를 포함하는 내부 클록 발생기 및 그 내부 전압발생 방법 |
| KR100680975B1 (ko) * | 2006-01-13 | 2007-02-09 | 주식회사 하이닉스반도체 | 파워다운 모드 제어 회로 |
| KR100776906B1 (ko) | 2006-02-16 | 2007-11-19 | 주식회사 하이닉스반도체 | 파워다운 모드 동안 주기적으로 락킹 동작을 실행하는기능을 가지는 dll 및 그 락킹 동작 방법 |
| US7613064B1 (en) * | 2006-12-19 | 2009-11-03 | Nvidia Corporation | Power management modes for memory devices |
| KR100896182B1 (ko) * | 2007-02-22 | 2009-05-12 | 삼성전자주식회사 | 지연 동기 회로의 파워 다운 모드를 제어하는 장치 및 그제어 방법 |
| US20080228950A1 (en) * | 2007-03-14 | 2008-09-18 | Qimonda North America Corp. | Memory power down mode exit method and system |
| JP2009140322A (ja) * | 2007-12-07 | 2009-06-25 | Elpida Memory Inc | タイミング制御回路および半導体記憶装置 |
| KR100902058B1 (ko) * | 2008-01-07 | 2009-06-09 | 주식회사 하이닉스반도체 | 반도체 집적 회로 및 그의 제어 방법 |
| US7728638B2 (en) * | 2008-04-25 | 2010-06-01 | Qimonda North America Corp. | Electronic system that adjusts DLL lock state acquisition time |
| JP5654196B2 (ja) * | 2008-05-22 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Dll回路ユニット及び半導体メモリ |
| KR100996176B1 (ko) | 2008-12-09 | 2010-11-24 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그에 구비되는 지연 고정 루프의 제어 방법 |
| KR101497777B1 (ko) | 2009-12-30 | 2015-03-02 | 마이크론 테크놀로지, 인크. | 클록 입력 버퍼 제어 |
| KR101175244B1 (ko) | 2010-04-29 | 2012-08-22 | 에스케이하이닉스 주식회사 | 반도체장치 및 이의 동작방법, 메모리 시스템 |
| KR101136985B1 (ko) | 2010-08-18 | 2012-04-19 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 데이터 출력 회로 |
| US20140115358A1 (en) * | 2011-05-27 | 2014-04-24 | Freescale Semiconductor, Inc. | Integrated circuit device and method for controlling an operating mode of an on-die memory |
| JP2015035241A (ja) * | 2013-08-09 | 2015-02-19 | マイクロン テクノロジー, インク. | 半導体装置 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3429977B2 (ja) * | 1997-05-16 | 2003-07-28 | 富士通株式会社 | スキュー低減回路及び半導体装置 |
| JP3832932B2 (ja) * | 1997-07-11 | 2006-10-11 | 富士通株式会社 | 半導体集積回路および半導体集積回路システム |
| JP4031859B2 (ja) * | 1998-02-03 | 2008-01-09 | 富士通株式会社 | 半導体装置 |
-
1998
- 1998-06-30 JP JP18448398A patent/JP4178225B2/ja not_active Expired - Lifetime
-
1999
- 1999-05-04 US US09/304,516 patent/US6266294B1/en not_active Expired - Lifetime
- 1999-05-13 KR KR1019990017075A patent/KR100329243B1/ko not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000021165A (ja) | 2000-01-21 |
| KR20000005652A (ko) | 2000-01-25 |
| JP4178225B2 (ja) | 2008-11-12 |
| US6266294B1 (en) | 2001-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100329243B1 (ko) | 집적 회로 장치 | |
| US6768690B2 (en) | Register controlled DLL for reducing current consumption | |
| US7196966B2 (en) | On die termination mode transfer circuit in semiconductor memory device and its method | |
| US7843745B2 (en) | Delay locked operation in semiconductor memory device | |
| JP3549751B2 (ja) | 半導体集積回路装置 | |
| JP3717289B2 (ja) | 集積回路装置 | |
| US7489172B2 (en) | DLL driver control circuit | |
| US7340632B2 (en) | Domain crossing device | |
| KR20020075572A (ko) | 지연동기루프의 전류소모를 감소시키기 위한스탠바이모드를 구비하는 반도체 메모리 장치 | |
| KR100510490B1 (ko) | 부분적으로 제어되는 지연 동기 루프를 구비하는 반도체메모리 장치 | |
| US6519188B2 (en) | Circuit and method for controlling buffers in semiconductor memory device | |
| KR100486922B1 (ko) | 반도체 기억 장치 | |
| KR100507874B1 (ko) | 클럭 동기화 회로를 구비한 동기식 반도체 메모리 장치 및클럭 동기화 회로의 클럭 트리 온/오프 제어회로 | |
| USRE46141E1 (en) | Semiconductor device and timing control method for the same | |
| JP3880206B2 (ja) | 集積回路装置 | |
| USRE44590E1 (en) | Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption | |
| KR20060054575A (ko) | 반도체 메모리 장치의 명령 디코더 | |
| JP3868126B2 (ja) | 集積回路装置 | |
| JP2002135237A (ja) | 半導体装置 | |
| KR101026378B1 (ko) | 지연고정루프회로의 클럭트리 회로 | |
| KR100436033B1 (ko) | 단위 동기 지연 라인 회로를 내장하는 반도체 메모리장치의 내부 클럭 신호 발생 회로 | |
| KR20020002540A (ko) | 리드 동작 시에 지연고정루프의 록킹 위치를 고정시키는쉬프트활성화신호 발생 장치를 갖는 지연고정루프 | |
| KR100856062B1 (ko) | 반도체 메모리 장치 및 그 구동방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19990513 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20010428 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20020208 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20020307 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20020308 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20050225 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20060223 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20070223 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20080225 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20090225 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100223 Start annual number: 9 End annual number: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20110222 Start annual number: 10 End annual number: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20120223 Start annual number: 11 End annual number: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20130227 Year of fee payment: 12 |
|
| PR1001 | Payment of annual fee |
Payment date: 20130227 Start annual number: 12 End annual number: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20140220 Year of fee payment: 13 |
|
| PR1001 | Payment of annual fee |
Payment date: 20140220 Start annual number: 13 End annual number: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20150224 Year of fee payment: 14 |
|
| PR1001 | Payment of annual fee |
Payment date: 20150224 Start annual number: 14 End annual number: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20160218 Year of fee payment: 15 |
|
| PR1001 | Payment of annual fee |
Payment date: 20160218 Start annual number: 15 End annual number: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20170220 Year of fee payment: 16 |
|
| PR1001 | Payment of annual fee |
Payment date: 20170220 Start annual number: 16 End annual number: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20180219 Year of fee payment: 17 |
|
| PR1001 | Payment of annual fee |
Payment date: 20180219 Start annual number: 17 End annual number: 17 |
|
| EXPY | Expiration of term | ||
| PC1801 | Expiration of term |
Termination date: 20191113 Termination category: Expiration of duration |