USRE44590E1 - Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption - Google Patents

Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption Download PDF

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USRE44590E1
USRE44590E1 US13/369,988 US201213369988A USRE44590E US RE44590 E1 USRE44590 E1 US RE44590E1 US 201213369988 A US201213369988 A US 201213369988A US RE44590 E USRE44590 E US RE44590E
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clock
active
signal
flip
address
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Chang-Ho Do
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Mosaid Technologies Inc
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658868 N B Inc
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Priority claimed from KR1020050117137A external-priority patent/KR100798766B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Definitions

  • the present invention relates to a clock control device; and more particularly, to a technology capable of decreasing current consumption by toggling an internal clock in a precharge/standby state of a semiconductor memory.
  • a semiconductor memory is processed in synchronism with a clock.
  • a need has existed for high speed operational memory to elevate the performance of a memory system.
  • attempts have made to reduce the number of external clock oscillations while increasing internal clock transitions.
  • current consumption is increased due to clock transitions within the semiconductor memory. Therefore, memory characteristics are needed that enable high speed operation but consume low power.
  • FIG. 1 is a diagram of a conventional common clock control device configuration.
  • the common clock control device includes a set circuit 10 and a shift register 20 .
  • the set circuit 10 sets an input address Ai depending on a Column Address Strobe (CAS) signal CASP to provide an address AYi.
  • the shift register 20 is provided with a plurality of D flip-flops DFF 1 to DFF 4 connected in series. The D flip-flops DFF 1 to DFF 4 sequentially perform a flip-flop operation of the address AYi in synchronism with an internal clock iCLK to output an address AYI_x.
  • the conventional clock control device as configured above allows a signal input in synchronism with an external clock to be recognized in synchronism with the internal clock iCLK in a semiconductor memory that operates by a low frequency external clock.
  • An interval between an input timing of a signal synchronization with the external clock and a recognition timing of the signal synchronization with the internal clock iCLK is defined as an internal latency.
  • DDR3 SD AM Double Data Rate Synchronous Dynamic Random Access Memory
  • a write command WT is input synchronously by the next clock CLK after an active command ACT and then data is input after a certain time delay. After the data input, a write operation is conducted in a core region of an actual DRAM.
  • address data corresponding to the internal latency must be fed to recognize address data input upon input of the write command WT at the initial time of write operation in the core region of the actual DRAM.
  • the address AYi is output by triggering an external input address Ai in response to the CAS signal CASP synchronized with the clock CLK upon input of the write command WT.
  • the D flip-flops DFF 1 to DFF 4 sequentially conduct a flip-flop operation of the address AYi triggered in synchronism with the internal clock iCLK, thereby outputting the address AYI_x. That is, they sequentially conduct the flip-flop operation of the address AYi according to the CAS signal CASP_WT, enabled synchronously by the clock CLK at which the write operation is done in the core region of the DRAM.
  • the general clock control device as structured above is operated by applying the internal clock iCLK to the D flip-flop DFF constantly, regardless of the current state of the chip. For the above reason, current consumption is increased as the internal clock iCLK is periodically transitioned.
  • a primary object of the present invention to provide a technology capable of decreasing current consumption by toggling an internal clock in a precharge/standby state by controlling the clock to toggle only in an active state in a semiconductor memory that allows command signals and addresses externally input to be applied to a core after an internal latency.
  • a clock control device including: a set circuit for triggering an input address in response to an internal command signal to output a first address; a shift register including a plurality of flip-flops connected in series, wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address; an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal; and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
  • a clock control device including: a set circuit for triggering an input address in response to an internal command signal to output a first address; a shift register including a plurality of flip-flops coupled in series, wherein some of the flip-flops conduct a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially perform a flip-flop operation of the second address in synchronism with a synchronous clock to produce an inner address; an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal; a flip-flop for carrying out a flip-flop operation of the active signal in synchronism with the internal clock to provide a delayed active signal; and a clock generator for generating the synchronous clock depending on the internal clock and the delayed active signal.
  • FIG. 1 is a block diagram of a configuration of a common clock control device
  • FIG. 2 is an operational timing diagram of a common clock control device
  • FIG. 3 is a block diagram illustrating a configuration of a clock control device in accordance with an embodiment of the present invention
  • FIG. 4 is a detailed circuit diagram of the set circuit shown in FIG. 3 ;
  • FIG. 5 is a detailed circuit diagram of the shift register shown in FIG. 3 ;
  • FIG. 6 is a detailed circuit diagram of the active signal generator depicted in FIG. 3 ;
  • FIG. 7 is a detailed circuit diagram of the clock generator shown in FIG. 3 ;
  • FIG. 8 is an operational timing diagram of the clock generator in accordance with the embodiment of the present invention.
  • FIG. 9 is a block diagram of a clock control device in accordance with another embodiment of the invention.
  • FIG. 3 is a block diagram illustrating a configuration of a clock control device in accordance with the present invention.
  • the clock control device of the invention comprises a set circuit 100 , a shift register 200 , an active signal generator 300 and a clock generator 400 .
  • the set circuit 100 triggers an input address Ai in response to a CAS signal CASP to provide an address AYi.
  • the shift register 200 includes a plurality of D flip-flops DFF 1 to DFF 4 coupled in series.
  • the D flip-flop DFF 1 conducts a flip-flop operation of the address AYi in synchronism with an internal clock iCLK to output an address Ayi_a.
  • the D flip-flop DFF 2 performs a flip-flop operation of an address Ayi_a in synchronism with the internal clock iCLK to provide an address Ayi_b.
  • the D flip-flops DFF 3 and DFF 4 carry out a flip-flop operation of the internal address Ayi_b in synchronism with a synchronous clock SCLK to produce an internal address AYI_x.
  • the active signal generator 300 generates an active signal RATVD based on an active signal ACTP ⁇ 0:i> and a precharge control signal PCGP ⁇ 0:i>, in which the active signal indicates that memory is in an active state.
  • the clock generator 400 creates the synchronous clock SCLK depending on the internal clock iCLK and the active signal RATVD.
  • FIG. 4 is a detailed circuit diagram of the set circuit 100 shown in FIG. 3 .
  • the set circuit 100 is provided with a transmission gate T 1 and a multiplicity of inverters IV 1 to IV 5 .
  • the transmission gate T 1 serves to selectively output the input address Ai on the basis of the CAS signal CASP and a CAS signal CASP inverted by the inverter IV 1 .
  • the inverters IV 3 and IV 4 latch the output signal of the transmission gate T 1 for a preset time.
  • the inverter IV 5 inverts the output of the latch composed of the inverters IV 3 and IV 4 to produce an internal address AYi.
  • FIG. 5 presents a detailed circuit diagram of the shift register 200 shown in FIG. 3 .
  • Each D flip-flop DFF includes transmission gates T 2 and T 3 and plural inverters IV 6 to IV 10 .
  • the transmission gate T 2 selectively outputs the internal address AYi in response to the internal clock iCLK and an internal clock iCLK inverted by the inverter IV 6 .
  • the inverters IV 7 and IV 8 latch the output signal of the transmission gate T 2 for a predetermined time.
  • the transmission gate T 3 is operated contemporarily with the transmission gate T 2 based on the internal clock iCLK and the internal clock iCLK inverted by the inverter IV 6 to selectively control the output of the latch composed of the inverters IV 7 and IV 8 .
  • a latch, composed of the inverters IV 9 and IV 10 latches the output of the transmission gate T 3 to provide an output signal OUT.
  • FIG. 6 provides a detailed circuit diagram of the active signal generator 300 depicted in FIG. 3 .
  • the active signal generator 300 includes a plurality of active controllers 310 to 330 and a logical operator 340 .
  • Each of the active controllers 310 to 330 logically operates an active control signal ACTP ⁇ 0:i> and a precharge control signal PCGP ⁇ 0:i>, respectively.
  • the plurality of active controllers 310 to 330 has the same configuration; and thus, only a controller 310 will be described below in detail.
  • the active controller 310 is provided with an inverter IV 11 and NAND gates ND 1 and ND 2 .
  • the NAND gate ND 1 does a NAND operation of an active control signal ACTP ⁇ 0> inverted by the inverter IV 11 and an output of the NAND gate ND 1 .
  • NAND gate ND 2 performs a NAND operation of the precharge control signal PCGP ⁇ 0> and the output of the NAND gate ND 1 .
  • the logical operator 340 includes a NOR gate NOR 1 and an inverter IV 12 .
  • the NOR gate NOR 1 NOR-operates the outputs of the plurality of active controllers 310 to 330 .
  • the inverter IV 12 inverts the output of the NOR gate NOR 1 to produce an active signal RATVD.
  • FIG. 7 is a detailed circuit diagram of the clock generator 400 shown in FIG. 3 .
  • the clock generator 400 is equipped with a NAND gate ND 3 and an inverter IV 13 .
  • the NAND gate ND 3 acts a NAND operation of the internal clock iCLK and the active signal RATVD.
  • the inverter IV 13 inverts the output of the NAND gate ND 3 to provide the synchronous clock SCLK.
  • FIGS. 3 to 7 Operation of the invention as configured above will be explained in detail referring to FIGS. 3 to 7 in parallel with an operational timing diagram shown in FIG. 8 .
  • the set circuit 100 latches the input address Ai input synchronously by a clock signal CLK upon activation of the CAS signal CASP to output the address AYi.
  • the external input address Ai is sensed by the CAS signal CASP created by an internal command signal, write or read command.
  • the shift register 200 conducts a flip-flop operation of the address AYi in synchronism with the internal clock iCLK to output the internal address Ayi_b and sequentially acts a flip-flop operation of the address Ayi_b in synchronism with the synchronous clock SCLK to provide the internal address AYI_x.
  • the active signal generator 300 is provided with the plurality of active controllers 310 to 330 for controlling active status data of each of the banks.
  • This active signal generator 300 logically operates each of the active signal ACTP ⁇ 0:i> and the precharge control signal PCGP ⁇ 0:i> to provide the active signal RATVD indicating that memory is in an active state. Therefore, the active signal RATVD is of logic low if all the banks are in a precharge state and is activated to logic high if any one of them is in an active state.
  • the clock generator 400 generates the synchronous clock SCLK based on the clock signal RATVD and the internal clock iCLK. In other words, if the active signal RATVD is in an activation state, the synchronous clock SCLK is output synchronously by the internal clock iCLK.
  • This invention controls the operation of the shift register 200 depending on both of the internal clock iCLK and the synchronous clock SCLK. That is, the active signal RATVD is activated by the active control signal ACTP denoting the external active command. Therefore, upon high speed operation, an internal delay time from a clock CLK at which the active control signal ACTP is input extends to a prolonged clock tA.
  • the synchronous clock SCLK that is operated only when chip is in an active state is generated only after that time. If all the D flip-flops DFF 1 to DFF 4 of the shift register 200 are controlled by synchronizing with the synchronous clock SCLK, the first D flip-flop DFF 1 senses the internal address AYi that is the output of the set circuit 100 by the synchronous clock SCLK generated after the delayed time tA. In this case, the transfer of valid information becomes substantially slower than a time at which it should be resynchronized, thereby causing a malfunctioning.
  • the invention controls the operation of the shift register 200 by separating the internal clock iCLK and the synchronous clock SCLK in order to assure the high speed operation.
  • the delayed time tA is varied relying upon Process, Voltage and Temperature (PVT); and thus, the internal clock iCLK and the synchronous clock SCLK are distributed by considering circumstances by which the synchronous clock SCLK is produced after the delayed time.
  • PVT Process, Voltage and Temperature
  • the invention properly can properly control a clock excessively operated in the precharge state during the high speed operation, thereby decreasing current consumption (in SDRAM, average current consumption is defined by IDD 2 N) in the precharge state.
  • FIG. 9 is a block diagram of a clock control device in accordance with another embodiment of the invention.
  • the embodiment of FIG. 9 comprises a set circuit 100 , a shift register 200 , an active signal generator 300 , a clock generator 400 and a D flip-flop 500 .
  • the embodiment of FIG. 9 as structured above further comprises a D flip-flop 500 , compared to the structure of FIG. 3 .
  • the D flip-flop 500 performs a flip-flop operation of the active signal RATVD output from the active signal generator 300 to provide a delayed active signal RATVD.
  • the synchronous clock SCLK can be created more stably by allowing the active signal RATVD applied to the clock generator 400 to be synchronized at a falling edge of the internal clock iCLK.
  • the active signal RATVD is synchronized with the internal clock iCLK
  • the active signal RATVD is a signal delayed by the internal delay
  • the internal clock iCLK is an internal clock signal interworking depending on an external clock. Therefore, there may be a state where the internal clock iCLK becomes logic high at the time when the active signal RATVD is activated to logic high.
  • the synchronous clock SCLK may be created as a glitch signal with incomplete pulse width.
  • the embodiment of FIG. 9 can prevent the malfunctioning by the synchronous clock with glitch component by separating the D flip-flop 500 synchronized with the internal clock iCLK from the D flip-flop DFF of the shift register 200 synchronized with the synchronous clock SCLK.
  • the input signal may be address, control signal, or data in the invention, without limiting thereto.
  • the invention can decrease current consumption by toggling of an internal clock in a precharge/standby state by toggling it only in an active state in a semiconductor memory that allows command signals and addresses inputted from outside to be applied to a core after an internal latency.
  • the present application contains subject matter related to Korean patent application No. 2005-91673 and No. 2005-117137, filed with the Korean Intellectual Property Office on Sep. 29, 2005 and on Dec. 02, 2005, the entire contents of which are incorporated herein by reference.

Abstract

A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.

Description

FIELD OF THE INVENTION
The present invention relates to a clock control device; and more particularly, to a technology capable of decreasing current consumption by toggling an internal clock in a precharge/standby state of a semiconductor memory.
DESCRIPTION OF RELATED ART
Generally, a semiconductor memory is processed in synchronism with a clock. A need has existed for high speed operational memory to elevate the performance of a memory system. For such high speed operation, attempts have made to reduce the number of external clock oscillations while increasing internal clock transitions. However, current consumption is increased due to clock transitions within the semiconductor memory. Therefore, memory characteristics are needed that enable high speed operation but consume low power.
FIG. 1 is a diagram of a conventional common clock control device configuration.
The common clock control device includes a set circuit 10 and a shift register 20. The set circuit 10 sets an input address Ai depending on a Column Address Strobe (CAS) signal CASP to provide an address AYi. The shift register 20 is provided with a plurality of D flip-flops DFF1 to DFF4 connected in series. The D flip-flops DFF1 to DFF4 sequentially perform a flip-flop operation of the address AYi in synchronism with an internal clock iCLK to output an address AYI_x.
The conventional clock control device as configured above allows a signal input in synchronism with an external clock to be recognized in synchronism with the internal clock iCLK in a semiconductor memory that operates by a low frequency external clock. An interval between an input timing of a signal synchronization with the external clock and a recognition timing of the signal synchronization with the internal clock iCLK is defined as an internal latency.
In particular, in memories such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR3 SD AM), the user can properly program and employ the internal latency depending on a clock period.
As shown in an operational timing chart of FIG. 2, in DDR3 SRAM, a write command WT is input synchronously by the next clock CLK after an active command ACT and then data is input after a certain time delay. After the data input, a write operation is conducted in a core region of an actual DRAM.
In this case, address data corresponding to the internal latency must be fed to recognize address data input upon input of the write command WT at the initial time of write operation in the core region of the actual DRAM.
For this purpose, the address AYi is output by triggering an external input address Ai in response to the CAS signal CASP synchronized with the clock CLK upon input of the write command WT. Next, the D flip-flops DFF1 to DFF4 sequentially conduct a flip-flop operation of the address AYi triggered in synchronism with the internal clock iCLK, thereby outputting the address AYI_x. That is, they sequentially conduct the flip-flop operation of the address AYi according to the CAS signal CASP_WT, enabled synchronously by the clock CLK at which the write operation is done in the core region of the DRAM.
However, the general clock control device as structured above is operated by applying the internal clock iCLK to the D flip-flop DFF constantly, regardless of the current state of the chip. For the above reason, current consumption is increased as the internal clock iCLK is periodically transitioned.
Where only one shift register 20 is operated as shown in FIG. 1, a current consumption amount is slight. However, since the actual DRAM should process plural addresses and command signals simultaneously, there exist a considerable number of circuits of such configuration as depicted in FIG. 1 within the DRAM. Consequently, a drawback of the conventional device is that current consumption increases as the speed of memories.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a technology capable of decreasing current consumption by toggling an internal clock in a precharge/standby state by controlling the clock to toggle only in an active state in a semiconductor memory that allows command signals and addresses externally input to be applied to a core after an internal latency.
In accordance with one aspect of the present invention, there is provided a clock control device including: a set circuit for triggering an input address in response to an internal command signal to output a first address; a shift register including a plurality of flip-flops connected in series, wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address; an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal; and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
In accordance with another aspect of the present invention, there is provided a clock control device including: a set circuit for triggering an input address in response to an internal command signal to output a first address; a shift register including a plurality of flip-flops coupled in series, wherein some of the flip-flops conduct a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially perform a flip-flop operation of the second address in synchronism with a synchronous clock to produce an inner address; an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal; a flip-flop for carrying out a flip-flop operation of the active signal in synchronism with the internal clock to provide a delayed active signal; and a clock generator for generating the synchronous clock depending on the internal clock and the delayed active signal.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a configuration of a common clock control device;
FIG. 2 is an operational timing diagram of a common clock control device;
FIG. 3 is a block diagram illustrating a configuration of a clock control device in accordance with an embodiment of the present invention;
FIG. 4 is a detailed circuit diagram of the set circuit shown in FIG. 3;
FIG. 5 is a detailed circuit diagram of the shift register shown in FIG. 3;
FIG. 6 is a detailed circuit diagram of the active signal generator depicted in FIG. 3;
FIG. 7 is a detailed circuit diagram of the clock generator shown in FIG. 3;
FIG. 8 is an operational timing diagram of the clock generator in accordance with the embodiment of the present invention; and
FIG. 9 is a block diagram of a clock control device in accordance with another embodiment of the invention.
 DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be set forth in detail with reference to the accompanying drawings.
FIG. 3 is a block diagram illustrating a configuration of a clock control device in accordance with the present invention.
The clock control device of the invention comprises a set circuit 100, a shift register 200, an active signal generator 300 and a clock generator 400.
Specifically, the set circuit 100 triggers an input address Ai in response to a CAS signal CASP to provide an address AYi. The shift register 200 includes a plurality of D flip-flops DFF1 to DFF4 coupled in series.
Among the plurality of D flip-flops DFF1 to DFF4, the D flip-flop DFF1 conducts a flip-flop operation of the address AYi in synchronism with an internal clock iCLK to output an address Ayi_a. The D flip-flop DFF2 performs a flip-flop operation of an address Ayi_a in synchronism with the internal clock iCLK to provide an address Ayi_b. And the D flip-flops DFF3 and DFF4 carry out a flip-flop operation of the internal address Ayi_b in synchronism with a synchronous clock SCLK to produce an internal address AYI_x.
The active signal generator 300 generates an active signal RATVD based on an active signal ACTP<0:i> and a precharge control signal PCGP<0:i>, in which the active signal indicates that memory is in an active state. The clock generator 400 creates the synchronous clock SCLK depending on the internal clock iCLK and the active signal RATVD.
FIG. 4 is a detailed circuit diagram of the set circuit 100 shown in FIG. 3.
As provided therein, the set circuit 100 is provided with a transmission gate T1 and a multiplicity of inverters IV1 to IV5. Specifically, the transmission gate T1 serves to selectively output the input address Ai on the basis of the CAS signal CASP and a CAS signal CASP inverted by the inverter IV1. The inverters IV3 and IV4 latch the output signal of the transmission gate T1 for a preset time. The inverter IV5 inverts the output of the latch composed of the inverters IV3 and IV4 to produce an internal address AYi.
FIG. 5 presents a detailed circuit diagram of the shift register 200 shown in FIG. 3.
Each D flip-flop DFF includes transmission gates T2 and T3 and plural inverters IV6 to IV10. The transmission gate T2 selectively outputs the internal address AYi in response to the internal clock iCLK and an internal clock iCLK inverted by the inverter IV6. The inverters IV7 and IV8 latch the output signal of the transmission gate T2 for a predetermined time.
The transmission gate T3 is operated contemporarily with the transmission gate T2 based on the internal clock iCLK and the internal clock iCLK inverted by the inverter IV6 to selectively control the output of the latch composed of the inverters IV7 and IV8. A latch, composed of the inverters IV9 and IV10, latches the output of the transmission gate T3 to provide an output signal OUT.
FIG. 6 provides a detailed circuit diagram of the active signal generator 300 depicted in FIG. 3.
The active signal generator 300 includes a plurality of active controllers 310 to 330 and a logical operator 340. Each of the active controllers 310 to 330 logically operates an active control signal ACTP<0:i> and a precharge control signal PCGP<0:i>, respectively. The plurality of active controllers 310 to 330 has the same configuration; and thus, only a controller 310 will be described below in detail.
As shown in FIG. 6, the active controller 310 is provided with an inverter IV11 and NAND gates ND1 and ND2. The NAND gate ND1 does a NAND operation of an active control signal ACTP<0> inverted by the inverter IV11 and an output of the NAND gate ND1. NAND gate ND2 performs a NAND operation of the precharge control signal PCGP<0> and the output of the NAND gate ND1.
The logical operator 340 includes a NOR gate NOR1 and an inverter IV12. The NOR gate NOR1 NOR-operates the outputs of the plurality of active controllers 310 to 330. The inverter IV12 inverts the output of the NOR gate NOR1 to produce an active signal RATVD.
FIG. 7 is a detailed circuit diagram of the clock generator 400 shown in FIG. 3.
As shown therein, the clock generator 400 is equipped with a NAND gate ND3 and an inverter IV13. The NAND gate ND3 acts a NAND operation of the internal clock iCLK and the active signal RATVD. The inverter IV13 inverts the output of the NAND gate ND3 to provide the synchronous clock SCLK.
Operation of the invention as configured above will be explained in detail referring to FIGS. 3 to 7 in parallel with an operational timing diagram shown in FIG. 8.
First, the set circuit 100 latches the input address Ai input synchronously by a clock signal CLK upon activation of the CAS signal CASP to output the address AYi. The external input address Ai is sensed by the CAS signal CASP created by an internal command signal, write or read command.
Next, the shift register 200 conducts a flip-flop operation of the address AYi in synchronism with the internal clock iCLK to output the internal address Ayi_b and sequentially acts a flip-flop operation of the address Ayi_b in synchronism with the synchronous clock SCLK to provide the internal address AYI_x.
In a multiple bank DRAM, an active operation may be done for each bank. Therefore, the active signal generator 300 is provided with the plurality of active controllers 310 to 330 for controlling active status data of each of the banks.
This active signal generator 300 logically operates each of the active signal ACTP<0:i> and the precharge control signal PCGP<0:i> to provide the active signal RATVD indicating that memory is in an active state. Therefore, the active signal RATVD is of logic low if all the banks are in a precharge state and is activated to logic high if any one of them is in an active state.
Next, the clock generator 400 generates the synchronous clock SCLK based on the clock signal RATVD and the internal clock iCLK. In other words, if the active signal RATVD is in an activation state, the synchronous clock SCLK is output synchronously by the internal clock iCLK.
This invention controls the operation of the shift register 200 depending on both of the internal clock iCLK and the synchronous clock SCLK. That is, the active signal RATVD is activated by the active control signal ACTP denoting the external active command. Therefore, upon high speed operation, an internal delay time from a clock CLK at which the active control signal ACTP is input extends to a prolonged clock tA.
Accordingly, to decrease current consumption, the synchronous clock SCLK that is operated only when chip is in an active state is generated only after that time. If all the D flip-flops DFF1 to DFF4 of the shift register 200 are controlled by synchronizing with the synchronous clock SCLK, the first D flip-flop DFF1 senses the internal address AYi that is the output of the set circuit 100 by the synchronous clock SCLK generated after the delayed time tA. In this case, the transfer of valid information becomes substantially slower than a time at which it should be resynchronized, thereby causing a malfunctioning.
Therefore, the invention controls the operation of the shift register 200 by separating the internal clock iCLK and the synchronous clock SCLK in order to assure the high speed operation. At this time, the delayed time tA is varied relying upon Process, Voltage and Temperature (PVT); and thus, the internal clock iCLK and the synchronous clock SCLK are distributed by considering circumstances by which the synchronous clock SCLK is produced after the delayed time.
As a result, the invention properly can properly control a clock excessively operated in the precharge state during the high speed operation, thereby decreasing current consumption (in SDRAM, average current consumption is defined by IDD2N) in the precharge state.
FIG. 9 is a block diagram of a clock control device in accordance with another embodiment of the invention.
The embodiment of FIG. 9 comprises a set circuit 100, a shift register 200, an active signal generator 300, a clock generator 400 and a D flip-flop 500.
The embodiment of FIG. 9 as structured above further comprises a D flip-flop 500, compared to the structure of FIG. 3. The D flip-flop 500 performs a flip-flop operation of the active signal RATVD output from the active signal generator 300 to provide a delayed active signal RATVD. By doing so, the synchronous clock SCLK can be created more stably by allowing the active signal RATVD applied to the clock generator 400 to be synchronized at a falling edge of the internal clock iCLK.
In other words, where the active signal RATVD is synchronized with the internal clock iCLK, the active signal RATVD is a signal delayed by the internal delay and the internal clock iCLK is an internal clock signal interworking depending on an external clock. Therefore, there may be a state where the internal clock iCLK becomes logic high at the time when the active signal RATVD is activated to logic high. In this case, the synchronous clock SCLK may be created as a glitch signal with incomplete pulse width.
Accordingly, the embodiment of FIG. 9 can prevent the malfunctioning by the synchronous clock with glitch component by separating the D flip-flop 500 synchronized with the internal clock iCLK from the D flip-flop DFF of the shift register 200 synchronized with the synchronous clock SCLK.
Although there is described with respect to the address Ai as the input signal in the embodiments of the invention, it should be noted that the input signal may be address, control signal, or data in the invention, without limiting thereto.
As explained above, the invention can decrease current consumption by toggling of an internal clock in a precharge/standby state by toggling it only in an active state in a semiconductor memory that allows command signals and addresses inputted from outside to be applied to a core after an internal latency.
The present application contains subject matter related to Korean patent application No. 2005-91673 and No. 2005-117137, filed with the Korean Intellectual Property Office on Sep. 29, 2005 and on Dec. 02, 2005, the entire contents of which are incorporated herein by reference.
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (23)

What is claimed is:
1. A clock control device, comprising:
a set circuit for triggering an input address in response to an internal command signal to output a first address;
a shift register including a plurality of flip-flops connected in series, wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address;
an active signal generator for outputting an active signal, based on an a plurality of active control signal signals indicating whether or not each a corresponding bank of a plurality of memory banks is activated, and a plurality of precharge control signal signals indicating whether or not a corresponding bank of the plurality of memory banks is precharged; and
a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
2. The clock control device as recited in claim 1, wherein the set circuit includes:
a first transmission gate for selectively outputting the input address based on an activation state of the internal command signal;
a latch for latching the output of the first transmission gate; and
a first inverter for inverting the output of the latch to provide the first address.
3. The clock control device as recited in claim 1, wherein the plurality of flip-flops are D flip-flops.
4. The clock control device as recited in claim 1, wherein the active signal generator outputs the active signal of logic low if the plurality of memory banks are all in a precharge state and the active signal of logic high if at least one of the plurality of memory banks is in an active state.
5. The clock control device as recited in claim 4, wherein the active signal generator includes:
a plurality of active controllers for logically combining the respective active control signal signals with the respective precharge control signal signals; and
a logical operator for logically operating the outputs of the plurality of active controllers to provide the active signal.
6. The clock control device as recited in claim 5, wherein the number of active controllers corresponds to the number of the memory banks.
7. The clock control device as recited in claim 5, wherein each of the plurality of active controllers includes:
a second inverter for inverting the a respective active control signal;
a first NAND gate for carrying out a NAND operation of the output of the second inverter and a first signal to output a second signal; and
a second NAND gate for acting a NAND operation of the a respective precharge control signal and the second signal to produce the first signal.
8. The clock control device as recited in claim 5, wherein the logical operator includes:
a NOR gate for NOR-operating the outputs of the plurality of active controllers; and
a third inverter for inverting the output of the NOR gate to output the active signal.
9. The clock control device as recited in claim 1, wherein the clock generator outputs the synchronous clock in synchronism with the internal clock if the active signal is in an activation state.
10. The clock control device as recited in claim 9, wherein the clock generator includes:
a third NAND gate for NAND-operating the internal clock and the active signal; and
a fourth inverter for inverting the output of the third NAND gate to output the synchronous clock.
11. A clock control device comprising:
a set circuit for triggering an input address in response to an internal command signal to output a first address;
a shift register including a plurality of flip-flops coupled in series, wherein some of the flip-flops conduct a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially perform a flip-flop operation of the second address in synchronism with a synchronous clock to produce an inner address;
an active signal generator for outputting an active signal, based on an a plurality of active control signal signals indicating whether or not each memory a corresponding bank of a plurality of memory banks is activated and a plurality of precharge control signal signals indicating whether or not a corresponding bank of the plurality of memory banks is precharged;
a flip-flop for carrying out a flip-flop operation of the active signal in synchronism with the internal clock to provide a delayed active signal; and
a clock generator for generating the synchronous clock depending on the internal clock and the delayed active signal.
12. The clock control device as recited in claim 11, wherein the flip-flop is a D flip-flop.
13. A clock control device, comprising:
a set circuit for triggering an input address in response to an internal command signal to output a first address;
a shift register including a plurality of flip-flops connected in series and configured to generate an internal address in response to an internal clock and a synchronous clock;
an active signal generator for outputting an active signal, based on an a plurality of active control signal signals indicating whether or not each a corresponding bank of a plurality of memory banks is activated, and a plurality of precharge control signal signals indicating whether or not a corresponding bank of the plurality of memory banks is precharged; and
a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
14. The clock control device as recited in claim 13, wherein some of the flip-flops in the shift register perform a flip-flop operation of the first address in synchronism with the internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with the synchronous clock to produce the internal address.
15. The clock control device as recited in claim 14, wherein the set circuit includes:
a first transmission gate for selectively outputting the input address based on an activation state of the internal command signal;
a latch for latching the output of the first transmission gate; and
a first inverter for inverting the output of the latch to provide the first address.
16. The clock control device as recited in claim 14, wherein the plurality of flip-flops are D flip-flops.
17. The clock control device as recited in claim 14, wherein the active signal generator outputs the active signal of logic low if the plurality of memory banks are all in a precharge state and the active signal of logic high if at least one of the plurality of memory banks is in an active state.
18. The clock control device as recited in claim 17, wherein the active signal generator includes:
a plurality of active controllers for logically combining the respective active control signal signals with the respective precharge control signal signals; and
a logical operator for logically operating the outputs of the plurality of active controllers to provide the active signal.
19. The clock control device as recited in claim 18, wherein the number of active controllers corresponds to the number of the memory banks.
20. The clock control device as recited in claim 18, wherein each of the plurality of active controllers includes:
a second inverter for inverting the a respective active control signal;
a first NAND gate for carrying out a NAND operation of the output of the second inverter and a first signal to output a second signal; and
a second NAND gate for acting a NAND operation of the a respective precharge control signal and the second signal to produce the first signal.
21. The clock control device as recited in claim 18, wherein the logical operator includes:
a NOR gate for NOR-operating the outputs of the plurality of active controllers; and
a third inverter for inverting the output of the NOR gate to output the active signal.
22. The clock control device as recited in claim 14, wherein the clock generator outputs the synchronous clock in synchronism with the internal clock if the active signal is in an activation state.
23. The clock control device as recited in claim 22, wherein the clock generator includes:
a third NAND gate for NAND-operating the internal clock and the active signal; and
a fourth inverter for inverting the output of the third NAND gate to output the synchronous clock.
US13/369,988 2005-09-29 2012-02-09 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption Active USRE44590E1 (en)

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US11/476,597 US7307913B2 (en) 2005-09-29 2006-06-29 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
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