KR20030050181A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to perform stably a data sensing operation in comparison with a refresh operation by setting up differently a row active time according to each operation. CONSTITUTION: A semiconductor memory device includes a command decoder(10) and a delay control portion(30). The command decoder receives a row active command including an internal precharge operation and outputs a flag signal corresponding to the inputted command. The delay control portion receives a row active signal and an output of the command decoder and outputs the row active signals of different delay. The row active command including the internal precharge operation includes a read with auto precharge command, a test mode command, an auto refresh command, and a self refresh command.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device. In particular, when performing various commands involving a row active operation in a synchronous DRAM (DRAM) or a DDR SDRAM using tRAS, a different row active time (row) The present invention relates to a semiconductor memory device using an active time.

Among semiconductor memory devices, DRAM can be configured by using one transistor and one capacitor, which has the advantage that the integration is much higher than other memory devices. Various technologies have been proposed to meet the demands of high-speed operation. A lot of speed has been improved.

Among conventional semiconductor DRAM devices, a DRAM device using a RAS (Raw Address Strobe) signal has a read with auto precharge operation, an auto refresh operation, or a self refresh operation in its operation. ) The same minimum tRAS (tRAS minimum) is used in the operation, and tRAS means the time when the row is active.

In the simple read operation of the DRAM operation mode, after performing the read operation, the precharge operation is performed according to the precharge command input from the DRAM controller.In this case, the low value is deactivated after the tRAS time according to the product specification and the precharge operation is performed. Perform.

However, in the case of the lead with auto precharge command, after performing the read operation, the precharge operation is performed according to the internal internal precharge command instead of the precharge command from the DRAM controller. In this case, it is necessary to secure the minimum time that the row is activated. This is called tRAS lock out function and is applied in the lead with auto precharge operation and the light with auto precharge operation.

1 to 3 are described with reference to the timing diagram of each operation.

First, FIG. 1 is a timing diagram of a read with auto precharge operation in a conventional DRAM device. Referring to this, an operation of activating a row address of a bank A in synchronization with a rising edge of a clock CLK is described. TRAS is started. Subsequently, when a command for the lead with auto precharge operation is input, the minimum tRAS (minimun tRAS) is observed, and the bank A is precharged to wait for the next active signal.

As such, the reason for complying with the minimum tRAS (minimun tRAS) is that the time required for the sense amplifier to sense and amplify the data stored in the bank's row address and re-enter the data into the memory cell (Rewright or Restore). This is because the sum of the time required is the minimum tRAS (tRAS minimum), so that the precharge command can be given to the bank after the minimum tRAS is observed.

In FIG. 1, tRP is a time required for precharging a low path circuit such as a row address buffer, a low decoder, or a sense amplifier in advance, and tRC is a sum of tRAS and tRP, which is also referred to as a RAS cycle time. Although different for each memory device, tRC is typically about 60n sec in the embodiment of the present invention.

FIG. 2 is a timing diagram when an auto refresh operation is performed in a conventional DRAM device. An auto refresh operation is a process of writing data back to a memory cell by an auto refresh command applied externally before data written to the memory cell is volatilized. wright) to preserve data.

tRFC is also called auto refresh instruction cycle and means the time between auto refresh operation and auto refresh operation. Since the auto refresh operation is a type of writing data to the memory cell, the low active operation is performed and the bank is precharged during the time (tRFC) during the auto refresh operation.

That is, after tRAS is activated, row addresses in various banks are activated, a refresh operation is performed, and a minimum tRAS (minimun tRAS) is observed, the banks are precharged during tRP according to an internal precharge command. The precharge performed in the auto refresh operation is also not performed by a command input from an external controller but by a command inside the DRAM.

The timing diagram of FIG. 2 shows precharging all banks during tRP before performing an auto refresh operation. This is an operation of precharging all banks before the auto refresh operation is performed in order to prevent the row address from being activated twice during the auto refresh operation.

However, since the auto refresh operation is applied to all banks, the time interval is longer than that of the leadweed auto precharge operation applied to only one bank. That is, tRFC is longer than tRC. However, in the related art, the minimum tRAS (tRAS minimum) that is internally observed during the tRFC period uses tRAS minimum (tRAS minimum) equal to the minimum tRAS (tRAS minimum) during the leadweed auto precharge operation shown in FIG. 1.

3 is a diagram illustrating a timing of a self refresh operation. The self refresh operation does not perform a refresh operation by an externally applied instruction, but internally generates an instruction necessary for refreshing at a predetermined cycle or when a predetermined condition is satisfied. Refresh operation.

Since the self refresh operation is similar to the operation of writing data into the memory cell, the internal refresh operation is performed after the internal compliance with the minimum tRSA (tRAS minimum), followed by internally precharging the banks during the tRP.

Since the self-refresh operation can be arbitrarily determined, the minimum tRAS (tRAS minimum) observed in the self-refresh operation is the minimum tRAS (tRAS minimum) used for the leaded auto precharge operation or the minimum used for the auto refresh operation. It is also possible to use a minimum tRAS (tRAS minimum) delay different from tRAS (tRAS minimum), but the same minimum tRAS (tRAS minimum) was used.

The timing diagram of FIG. 3 illustrates precharging all banks during tRP before performing a self refresh operation. This is an operation performed for the same reason as precharging all the banks shown in Fig. 2 during tRP before the auto refresh operation.

The self refresh exit command is for exiting the self refresh operation. When this command is input, the next command is input after at least 200 clock cycles to stop the self refresh operation and wait for another command to be entered. have. In DDR SDRAM, delay lock loop (DLL) or clock buffer does not operate during self-refresh operation. Therefore, delay time of 200 clock cycles is considered in consideration of the time required for DLL to run again and output stable internal clock signal. I put it.

As described above, the same minimum tRAS (tRAS minimum) is used in both the lead with auto precharge operation, the light with auto precharge operation, the auto refresh operation, and the self refresh operation. There was this.

In the lead with auto precharge operation, only one bank needs to be active, but in the auto refresh operation or the self refresh operation, all the banks must be activated. In this case, if the same minimum tRAS (tRAS minimum) is used, the sensing margin of the sensing amplifier is reduced in the refresh operation.

In the test process performed after fabricating the semiconductor memory device, when comparing the wafer test and the package test, the frequency of the signal used in the package test is higher than the frequency of the signal used in the wafer test.

Considering the switching current of the MOS transistors constituting the memory device, since the operation at low frequency consumes less current than at high frequency, the voltage drop inside the memory element is also small at the time of wafer test using the low frequency. As a result, a device that normally operated during a wafer test may cause a malfunction during a package test. However, a device that malfunctions in a package test cannot be replaced with a repair cell, resulting in a decrease in device yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor memory device which improves the characteristics and yield of the memory device by adjusting a low active time in the memory device.

1 is a timing diagram of a lead with auto precharge operation;

2 is a timing diagram of an auto refresh operation;

3 is a timing diagram of a self refresh operation;

4 is a low active time control circuit according to an embodiment of the present invention;

5 is a low active time control circuit according to another embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

10: Command decoder

11: basic delay circuit

12: a1 delay circuit

13: a2 delay circuit

14: a3 delay circuit

15: a4 delay circuit

30: delay control unit

In accordance with another aspect of the present invention, a semiconductor memory device including a plurality of banks may be configured to receive a low active command having an internal precharge operation and to output a flag signal corresponding to the input command. Command decoder; And a delay adjuster configured to receive a low active signal and an output of the command decoder and output a low active signal having different delays.

The present invention improves the characteristics and the yield of a memory device by adjusting the low active time in the memory device and using different low active time in various operations.

In the operation of the memory device, the two operations are different from each other because the time required for the auto refresh operation that requires all banks to be activated is always larger than the time required for the lead with auto precharge operation that uses one bank to be active. minimum) can be used.

In addition, since the self-refresh operation can determine the period internally, a corresponding tRAS minimum (tRAS minimum) may be used. In one embodiment of the present invention, the minimum tRAS (tRAS minimum) used in the self refresh operation is set to the largest value. However, the operation of the device is not affected due to the delay time of 200 cycles after the self refresh ends as described above.

This will be described below. In the exemplary embodiment of the present invention, since the largest minimum tRAS (tRAS minimum) is used for the self-refresh operation, the long active time is the longest during the self-refresh operation, and all banks after the longest low active activation time Pre-charging is a self refresh operation.

Therefore, when the self refresh operation is performed immediately before the self refresh end command is input, the next command is input after the minimum tRAS (tRAS minimum) is observed and before all the banks are precharged. It is expected to occur, but it does not happen.

As described above, when the self-refresh end command is input, the next command is input after a delay period of 200 clock cycles, and thus, it is not possible to precharge all banks before the next command is input.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

4 is a diagram illustrating a low active time control circuit of a semiconductor memory device according to an embodiment of the present invention. Referring to the embodiment of the present invention, one embodiment of the present invention is a lead with auto precharge, a light with auto precharge, and an auto refresh. A command decoder 10 which receives a self refresh and a test mode command, determines which command the input command is, and outputs a flag corresponding thereto; The delay control unit 30 receives a delayed low active signal and the output of the command decoder 10 and outputs an internal precharge command.

In the case of asynchronous DRAM, control signals such as / RAS or / CAS signal that activates the row had to be kept 'high' or 'low' for a certain time, but operated in synchronization with the clock such as synchronous DRAM or DDR SDRAM. In DRAM, if the signal is given only for one clock cycle, the signal is stored in the internal register, so the input state is maintained as long as the contents of the register are not changed.

Therefore, the state of the chip is determined by the combination of several external signals inputted in synchronization with the clock. Thinking of this as programming, the synchronous DRAM uses the term command instead of the control signal.

When the low-active signal corresponding to the RAS signal of the asynchronous DRAM is input to the synchronous DRAM, the signal is delayed and used to generate another control signal. The low-active signal input to the delay controller 30 of FIGS. 4 to 5 is delayed. It is a signal.

The delay control unit 30 receives a delayed low active signal and delays it for a predetermined time, and then outputs an internal precharge command according to a flag signal which is an output of the basic delay circuit 11 and the command decoder 10. A1 delay circuits 12 to a4 delay circuits 15 and the basic delay circuits 11 and a1 delay circuits 12 to a4 delay circuits 15 are connected in series.

In an embodiment of the present invention, the minimum tRAS minimum tRAS used in the test mode is set to the smallest, which will be described later.

As shown in FIG. 4, when the command inputted to the command decoder 10 is a command regarding the test mode, the delayed active signal passing through the basic delay circuit 11 and the a1 delay circuit 12 is converted into an internal precharge command. do.

When a lead with auto precharge or a light with auto precharge command is input to the command decoder 10, a flag for this command is output from the command decoder 10, and the flag is input to the delay controller 30 so as to provide a basic delay. The delayed low active signal passing through the circuit 11, the a1 delay circuit 12, and the a2 delay circuit 13 becomes an internal precharge command.

Since the delay time is different for each operation, the minimum tRAS observed for each operation will be different. That is, in the case of lead with auto precharge, the low active signal passing through the basic delay circuit (11) + a1 delay circuit (12) + a2 delay circuit (13) becomes the internal precharge command, and the basic delay in the test mode. The low active signal passing through the circuit 11 and the a1 delay circuit 12 becomes an internal precharge command.

Similarly, when an auto refresh instruction is input to the instruction decoder 10, the instruction decoder outputs a flag corresponding to the auto refresh instruction and according to the flag, the basic delay circuit 11 + a1 delay circuit 12 + a2 delay circuit 13 ) + A3 The low active signal passing through the delay circuit 14 becomes an internal precharge command.

When the self-refresh command is inputted to the instruction decoder 10, the instruction decoder outputs a flag corresponding to the self refresh instruction, and according to the flag, the basic delay circuit 11 + a1 delay circuit 12 + a2 delay circuit 13 + The low active signal passing through the a3 delay circuit 14 + a4 delay circuit 15 becomes an internal precharge command.

FIG. 5 is a diagram illustrating another embodiment according to the present invention, in which a plurality of different delay circuits are provided and corresponding to a flag for each mode so that the minimum tRAS is observed for each mode.

Referring to FIG. 5, the low active time control circuit of a semiconductor device according to another embodiment of the present disclosure receives a variety of commands and determines which command the input command is and outputs a flag thereof. And a delay adjuster 30 that receives the delayed low active signal and the output of the command decoder 20 and outputs an internal precharge command.

The delay adjusting unit 30 receives a delayed low active signal and a test mode flag and delays the predetermined time to output an internal precharge command, and a delayed low active signal and a W / R with auto precharge flag. W / R with auto precharge delay circuit 22 that outputs an internal precharge command by delaying a predetermined time, and receives a low active signal and an auto refresh flag delayed for a predetermined time, and then outputs an internal precharge command. A refresh delay circuit 23 and a cell refresh delay circuit 24 for receiving an RAS signal and a cell refresh flag to output an internal precharge command.

When the test mode signal is input to the command decoder 20, the command decoder 20 outputs a test mode flag to the test mode delay circuit 21, and a low active signal passing through the test mode delay circuit 21 is internal. It becomes a precharge command and becomes the output of the test mode delay circuit 21.

When the lead with auto precharge command or the light with auto precharge command is input to the command decoder 20, the command decoder 20 outputs a W / R with auto precharge flag and a W / R with auto precharge delay circuit. The low active signal passing through 22 becomes an internal precharge command.

Similarly, even when an auto refresh command or a cell refresh command is input to the instruction decoder 20, a delayed low active signal input to each of the delay circuits 23 and 24 is output in accordance with the flag signal and used as an internal precharge command. .

In the present invention, the minimum tRAS (tRAS minimum) used in the test mode is set to be the smallest. As described above, the minimum tRAS means the time required to detect and amplify the data stored at the row address of the bank through the sense amplifier, and the time required to re-input (Rewright or Restore) data into the memory cell again. Therefore, the larger the tRAS is set, the longer the sensing amplifier operates, thereby improving the sensing margin.

In the semiconductor test, the wafer test uses a low frequency signal, so it is performed in less severe conditions than the package test, so it is less likely to fail. In the wafer test, a failed cell can be replaced by a repair cell. By using the dots, cells that are likely to fail can be reliably screened out during wafer testing and replaced with a repair cell. Then, if the package test is performed, a device that normally worked during the wafer test causes a malfunction in the package test. Can be reduced to improve yield.

To this end, setting the minimum tRAS used for wafer testing to a small value reduces the sensing margin, which makes the wafer test conditions harsh. In this case, cells that are likely to fail will not work, so replace them with repair cells, and then perform a package test to improve the yield.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied to a semiconductor memory device, the low active time can be set differently according to each operation to enable more stable data sensing than the refresh operation. Also, the test condition is adjusted in the test mode to improve the yield of the semiconductor device. It is effective to improve.

Claims (4)

In a semiconductor memory device comprising a plurality of banks, A command decoder configured to receive a low active command involving an internal precharge operation and to output a flag signal corresponding to the input command; And A delay adjuster which receives a low active signal and the output of the command decoder and outputs a low active signal having different delays Semiconductor memory device comprising a. The method of claim 1, The low active command accompanying the internal precharge operation A semiconductor memory device comprising a read with auto precharge command, a test mode command, an auto refresh command, and a self refresh command. The method of claim 2, The delay control unit A basic delay unit configured to receive a low active signal and delay the output for a predetermined time; A first delay unit receiving the output of the basic delay unit for a predetermined time and outputting the delayed signal according to a test mode flag signal which is an output of the command decoder; A second delay unit receiving the output of the first delay unit for a predetermined time and outputting the delayed signal according to a read with auto precharge flag signal which is an output of the command decoder; A third delay unit receiving the output of the second delay unit and delaying the output for a predetermined time and outputting the second delay unit according to an auto refresh flag signal which is an output of the command decoder; And A fourth delay unit which receives the output of the third delay unit and delays the output for a predetermined time and outputs the signal according to a cell refresh flag signal that is an output of the command decoder; Semiconductor memory device, characterized in that configured to include The method of claim 2, The delay control unit A first delay circuit receiving a low active signal and delaying the predetermined time for outputting the low active signal according to a test mode flag signal which is an output of the command decoder; A second delay circuit for receiving a low active signal and delaying the predetermined time and outputting the low active signal according to a read with auto precharge flag signal which is an output of the command decoder; A third delay circuit for receiving a low active signal and delaying the predetermined time and outputting the low active signal according to an auto refresh flag signal which is an output of the command decoder; And A fourth delay circuit configured to receive a low active signal for a predetermined time delay and output the low active signal according to a cell refresh flag signal that is an output of the command decoder; A semiconductor memory device, characterized in that comprising a.