KR100668750B1 - Data input circuit of semiconductor device - Google Patents

Abstract

A data input circuit of a semiconductor device is provided to reduce current consumption of a data input buffer by turning on the data input buffer only when a data mask signal is inputted, during a read process. A data input circuit of a semiconductor device includes a buffer off controller(250), a buffer on controller(260), a buffer controller(270), and a data input buffer(280). The buffer off controller receives a first control signal and a second control signal and outputs a first buffer control signal. The first control signal is disabled longer than a burst length during a read process. When a read command is inputted, the second control signal is enabled during a predetermined period. The first buffer control signal is used to turn off the data input buffer. The buffer on controller receives the first control signal and a third control signal, which is disabled when the read command is inputted, and outputs a second buffer control signal for turning on the data input buffer. The buffer controller receives the first and second buffer control signals and outputs a buffer enable signal. The data input buffer is enabled by the buffer enable signal and buffers the input data.

Description

Data input circuit of semiconductor device

1 shows a configuration of a data input circuit of a conventional semiconductor device.

2 illustrates a configuration of a static input buffer of a semiconductor device.

3 illustrates a configuration of a dynamic input buffer of a semiconductor device.

4 illustrates a configuration of a buffer control unit used in a conventional data input circuit.

5 is a timing diagram for each signal of a data input circuit of a conventional semiconductor device.

6 illustrates a configuration of a data input circuit of a semiconductor device according to an embodiment of the present invention.

7 shows the configuration of a buffer off controller used in the data input circuit according to the present embodiment.

8 shows the configuration of a buffer on controller used in the data input circuit according to the present embodiment.

9 shows the configuration of a buffer controller used in the data input circuit according to the present embodiment.

10A illustrates a timing diagram for each signal in the buffer off controller according to the present embodiment.

10B is a timing diagram for each signal in the buffer on controller according to the present embodiment.

Fig. 10C shows a timing diagram for each signal of the data input circuit of the semiconductor device according to this embodiment.

The present invention relates to a data input circuit of a semiconductor device, and more particularly, by turning off the data input buffer immediately when a read command is input, thereby reducing the current consumption of the data input buffer to reduce the overall current consumption of the semiconductor device. It relates to a data input circuit of a semiconductor device that can be made.

Dynamic random access memory (DRAM) is a volatile memory device that stores data in each cell having a structure of one transistor and one capacitor. The input / output operation of data, which is a basic function of a DRAM cell, This is achieved by turning on / off a word line that is a gate input of a transistor in a cell.

In a typical DRAM memory device, a memory cell area is divided into a plurality of banks. The read operation of the data stored in each cell is driven by a data transfer unit, in which cell data amplified by an input / output sense amplifier is a kind of driver, thereby providing a global data bus line. Bus line, Global DB line) is passed to the data receiver via the global data bus line and output through the output.

However, in a semiconductor device, in particular, an SDRAM, a data output buffer is turned on and a data input buffer is turned off during a read operation. However, in the conventional semiconductor device, even when the read operation mode is entered, the data input buffer is kept turned on until the data output buffer is turned on. As a result, the data output buffer is turned on even after the read command input. Until the on point, the data input buffer is continuously turned on, causing unnecessary current consumption. Hereinafter, the problems of the conventional semiconductor device will be described in more detail with reference to FIGS. 1 to 5.

1 shows a configuration of a data input circuit of a conventional semiconductor device. The command decoder 120 receives the external clocks CLK and CLKB, the clock enable signal CKE, the chip select signal CSB, the ras signal RASB, the cas signal CASB, and the write enable through the receiver 110. Receive the signal WEB. According to the JEDEC regulations, a mode register that receives a signal from the command decoder 120 when an active command (CSB = Low, RASB = Low, CASB = High, WEB = High, and Bank Address (BA0, BA1)) is received. The register 140 outputs a low level bank active signal bankA. Here, the bank active signal bankA is a signal that is enabled at a low level when any one of the plurality of banks is activated, and is disabled at a high level when none of the banks is active.

In addition, the mode register 140 outputs the control signal dqoff in accordance with the burst length BL determined by the addresses A0 to A2. Here, the control signal dqoff is a signal for guaranteeing a burst length during a read operation. The control signal dqoff is disabled during a period including at least a burst length during a read operation. Particularly, one clock clk after completing the CAS latency is completed. The signal is disabled at a low level from the previous time until the time when one clock clk elapses after the burst operation is completed.

The buffer controller 150 receives the bank active signal bankA, the control signal dqoff, and the data mask signal iDM and outputs a buffer enable signal controlling the data input buffer 160. That is, as shown in FIG. 4, first, the clock enable signal iCKE transitions to a high level in order for the DRAM to operate, and when the active command comes in later, the bank active signal bankA is enabled to a low level. As a result, the node A1 is in a high level state. When the write command is input, the control signal dqoff maintains the high level, so that the node A3 also becomes high regardless of the state of the data mask signal iDM. Therefore, at this time, the buffer enable signal is enabled at a high level. In response to the high-level buffer enable signal (enable), the data input buffer 160 shown in FIG. 2 or 3 is turned on to perform a buffering operation. As such, in the write operation mode, the data input buffer 160 is turned on and the semiconductor device can receive data from the outside.

Semiconductor devices such as SDR and DDR each have a DQ mask function, where DQ means input / output channels of data and mask means data. Accordingly, the data mask signal iDM is a signal that prevents the read or write operation from intercepting the progress of some data in the read operation or the write operation.

On the other hand, when a read command is input after the input of the active command, the control signal dqoff is displayed at a low level from one clock (clk) before the cascade latency is completed to one clock (clk) after the burst operation is completed. As a result, if the data mask signal iDM does not come in, the node A3 is at a low level, and the buffer enable signal is enabled at a low level. Therefore, the data input buffer 160 is turned off during this period.

By the way, in the SDR or the like, the data mask signal iDM can come in in the read command state. For example, according to the JEDEC regulations, the data mask command is always input in the case of the read by interrupted write command. When the data mask command is input, the data input buffer should always be turned on. Accordingly, in the conventional semiconductor device, even when a read command is input, the data input buffer is turned on until 1 clock (clk) before the cascade latency is completed. There was a problem that unnecessary current consumption continued to occur in the buffer.

Accordingly, a technical problem of the present invention is to turn off the data input buffer immediately when a read command is input in a semiconductor device, but turn on the data input buffer when a data mask signal is input even when a read operation is performed. The present invention provides a data input circuit of a semiconductor device capable of faithfully performing a mask operation and at the same time reducing current consumption of the data input buffer to reduce overall current consumption of the semiconductor device.

In order to achieve the above technical problem, the present invention receives a first control signal that is disabled during a period including at least a burst length during a read operation, and a second control signal that is enabled for a predetermined period when a read command is input to the data input buffer. A buffer off controller for outputting a first buffer control signal for controlling a turn-off related operation; A buffer on controller configured to receive a first control signal and a third control signal disabled for a predetermined period when the read command is input and output a second buffer control signal for controlling a turn-on related operation of a data input buffer; A buffer controller which receives the first buffer control signal and the second buffer control signal and outputs a buffer enable signal; The present invention provides a data input circuit of a semiconductor device including a data input buffer enabled by the buffer enable signal and buffering input data.

In the present invention, it is preferable that the buffer controller enables the buffer enable signal regardless of the first and second buffer control signals when a data mask signal is input.

In the present invention, when the read command is input, the buffer controller preferably disables the buffer enable signal.

In the present invention, the buffer control unit includes a first logic element and a second logic element connected in the form of a latch, wherein the first logic element receives the first buffer control signal to one input terminal and the second logic element is A latch unit configured to receive a second buffer control signal through one input terminal; A buffer for buffering the data mask signal; It is preferable to include a first logic unit for performing a logical operation of the latch unit and the output signal of the buffer.

In the present invention, it is preferable that the first logic element and the second logic element are NAND gates that perform negative logical operations.

In the present invention, the first logic unit preferably performs a negative logical operation.

In the present invention, the buffer control unit includes a second logic unit for performing a logic operation on the bank active signal and the clock enable signal and outputting a result thereof; Preferably, the apparatus further includes a third logic unit configured to logically output the output signals of the first logic unit and the second logic unit to output the buffer enable signal.

In the present invention, it is preferable that the second logic unit and the third logic unit perform an AND operation.

In the present invention, the buffer off control unit includes a delay unit for delaying the first control signal by a predetermined period; A buffer for buffering the output signal of the delayer; A first logic unit configured to logically operate the first control signal and an output signal of the buffer; And a second logic unit configured to logically operate the second control signal and the output signal of the first logic unit to output the first buffer control signal.

In the present invention, it is preferable that the first logic unit performs a negative logical product operation, and the second logic unit performs a logical product operation.

In the present invention, the buffer on control unit includes a delay unit for delaying the first control signal by a predetermined period; A buffer for buffering the output signal of the delayer; A first logic unit configured to logically operate the first control signal and an output signal of the buffer; It is preferable to include a second logic unit for performing a logical operation of the third control signal and the output signal of the first logic unit.

In the present invention, the buffer on control unit may further include a third logic unit configured to logically perform an output signal and a reset signal of the second logic unit.

In the present invention, it is preferable that the first logic unit performs a negative logical product operation, and the second logic unit performs a logical product operation.

In the present invention, the data input buffer is preferably a differential amplification type for amplifying the input data compared to a predetermined reference voltage.

In the present invention, the first control signal is characterized in that it is generated in a mode register.

In the present invention, the second control signal and the third control signal may be generated by a command decoder.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

6 illustrates a configuration of a data input circuit of a semiconductor device according to an embodiment of the present invention, and FIGS. 7 to 9 respectively show a buffer off controller and a buffer on controller used in the data input circuit according to the present embodiment. And a configuration of the buffer controller, the configuration of the data input circuit of the semiconductor device according to the present invention will be described below with reference to the configuration.

As shown in FIG. 6, the data input circuit of the semiconductor device according to the present exemplary embodiment includes a control signal dqoff disabled during a period including at least a burst length during a read operation and a predetermined period enabled when a read command is input. A buffer off controller 250 for receiving a control signal readS and outputting a first buffer control signal bufoff for controlling a turn-off related operation of the data input buffer 280; Receiving a control signal dqoff and a control signal writeS disabled for a predetermined period when a read command is input, and outputting a second buffer control signal bufon for controlling a turn-on related operation of the data input buffer 280. A buffer on controller 260; A buffer controller 270 which receives the first buffer control signal bufoff and the second buffer control signal bufon and outputs a buffer enable signal; And a data input buffer 280 enabled by the buffer enable signal (enable) to buffer the input data DQ.

The buffer controller 270 includes a NAND gate ND42 and a NAND gate ND43 connected in a latch form, and the NAND gate ND42 receives a first buffer control signal bufoff to one input terminal and receives the NAND gate ND43. ) Is a latch unit 271 for receiving a second buffer control signal bufon to one input terminal; An inverter IV43 that inverts and buffers the data mask signal iDM; A NAND gate (ND44) for performing a negative logic operation on the output signal of the latch unit 271 and the inverter IV43; A logic unit 272 for performing an AND operation on the inverted signal of the bank active signal bankA and the clock enable signal iCKE and outputting a result thereof; And a logic unit 273 for performing an AND operation on the output signals of the NAND gate ND44 and the logic unit 272 to output the buffer enable signal.

The buffer off control unit 250 includes a delay unit 251 for delaying the inversion signal of the control signal dqoff by a predetermined period; An inverter IV22 that inverts and buffers the output signal of the delay unit 251; A NAND gate ND21 for performing a negative logic operation on the inverted signal of the control signal dqoff and the output signal of the inverter IV22; And a logic unit 252 for outputting the first buffer control signal bufoff by performing an AND operation on the inversion signal of the control signal readS and the output signal of the NAND gate ND21.

The buffer on control unit 260 includes a delay unit 261 for delaying a control signal dqoff by a predetermined period; An inverter IV33 that inverts and buffers the output signal of the delay unit 261; A NAND gate ND31 for performing a negative logic operation on the control signal dqoff and the output signal of the inverter IV33; A logic unit 262 for performing an AND operation on the inverted signal of the control signal writeS and the output signal of the NAND gate ND31; And a logic unit 263 for performing an AND operation on the output signal of the logic unit 262 and the inverted signal of the reset signal rst.

The operation of this embodiment configured as described above will be described in detail with reference to FIGS. 6 to 10.

First, each of the signals input to the buffer controller 270 that generates the buffer enable signal (enable) and controls the operation of the data input buffer 280 will be described in FIG. 6. When a read command (CSB = Low, RASB = High, CASB = Low, WEB = High) is externally received, the command decoder 220 outputs a control signal readS. The control signal readS is a pulse signal which is normally at a low level and is enabled at a high level for a certain period when a read command is input. On the other hand, when a write command (CSB = Low, RASB = High, CASB = Low, WEB = Low) is received from the outside, the command decoder 220 outputs a control signal writeS. The control signal writeS is a signal that transitions to a low level when a read command is input and is enabled to a high level for a certain period when a write command is input. In addition, the first buffer control signal bufoff is a signal generated by the buffer off controller 250 to control the turn-off related operation of the data input buffer 280, and the second buffer control signal bufon is The signal generated by the buffer on controller 260 is a signal for controlling the turn-on related operation of the data input buffer 280.

The clock enable signal iCKE, the bank active signal bankA and the data mask signal iDM are the same as those used in the conventional data input circuit. That is, the bank active signal bankA is a signal that is enabled at a low level when any one of a plurality of banks is active, and is disabled at a high level when none of the banks is active, and the data mask signal iDM is a signal for a read operation or a write operation. Therefore, it is a signal that blocks the progress of some data and prevents it from being read or written. Meanwhile, the control signal dqoff generated by the mode register 240 and input to the buffer off controller 250 and the buffer on controller 260 is disabled during a read operation including at least a burst length. In particular, the cas latency (CAS latency) A signal that is disabled at a low level from one clock (clk) before completion to one clock (clk) after the burst operation is completed.

Referring to the operation of the data input circuit according to the present embodiment, first, a power supply is applied to a DRAM chip or a mode register set (CSB = Low, RASB = Low, CASB = Low, WEB = Low) in accordance with JEDEC regulations. When the reset signal rst input to the buffer on controller 260 generates a high level pulse to initialize the circuit, the reset signal rst transitions to the low level again. Accordingly, the second buffer control signal bufon in FIG. 8 becomes low level, and the signal input to one terminal of the NAND gate ND42 in FIG. 9 is initialized to high level.

After the circuit is initialized and before the read command is input, since the control signal dqoff is at the high level and the control signal readS is at the low level, the NAND gate is controlled by the buffer off controller 250 of FIG. 7. The signal of the node B1 which is the output of ND21 becomes high level, and the output of inverter IV23 also becomes high level. As a result, the first buffer control signal bufoff, which is an output signal of the logic unit 252, becomes high. At this time, since the control signal writeS is at the high level, the signal of the node B2, which is the output of the NAND gate ND31 in the buffer on controller 260 of FIG. 8, is at the high level and the output of the inverter IV34 is high. Goes low level. Accordingly, the logic unit 262 outputs a low level signal and the second buffer control signal bufon becomes low level.

Next, referring to the operation of the buffer control unit 270 of FIG. 9, even if the clock enable signal iCKE is at the high level, the bank active signal bankA is at the high level and the logic unit 272 is at the high level. Since the low level signal is output, the buffer enable signal (enable) output from the logic unit 273 is disabled to the low level. Therefore, the data input buffer 280 does not operate at this time.

When the active command is input, the bank active signal bankA transitions from the high level to the low level, so that the signal of the node B3, which is the output of the logic unit 272, becomes a high level, so that the buffer enable signal is enabled. The state of is determined according to node B6. If the data mask function is not used at this time, the data mask signal iDM is at the low level and the node B5 is at the high level, so that the state of the buffer enable signal is enabled. ) Is determined by the level.

However, before the read command is input, as illustrated in FIGS. 10A and 10B, since the first buffer control signal bufoff is high level and the second buffer control signal bufon is low level, the latch unit 271 is used. The signal of the node B4, which is the output of N, becomes low level, and the NAND gate ND44 outputs a high level signal. Accordingly, the buffer enable signal (enable) becomes a high level before the read command is input, so that the data input buffer 280 operates.

Thereafter, when a read command is input, as shown in FIG. 10A, the control signal readS transitions to a high level for a predetermined period. Accordingly, the signal input to the logic unit 252 from the buffer off control unit 250 of FIG. 7 becomes low level and the first buffer control signal bufoff becomes low level during the period. In addition, as described above, since the control signal dqoff is disabled at a low level from one clock clk before the CAS latency is completed to one clock clk after the burst operation is completed, the control signal dqoff is disabled. When the control signal dqoff transitions to the low level, the signal output from the inverter IV21 in the buffer off controller 250 immediately transitions to the high level, while one side of the NAND gate ND21 is output from the inverter IV22. The signal entering the input stage maintains the previous high level during the delay section by the delay unit 251. Accordingly, since the NAND gate ND21 receives two signals of high level during the delay period, the signal of the node B1 becomes low level and the first buffer control signal bufoff becomes low level. As such, when the read command is input, the first buffer control signal bufoff becomes low during the period in which the control signal readS becomes high and the delay period by the delay unit 251.

In addition, when a read command is input, as illustrated in FIG. 10B, the control signal writeS transitions to a low level for a predetermined period. Accordingly, the signal input to the logic unit 262 by the buffer on control unit 260 of FIG. 8 becomes high level, and at this time, the signal of the node B2 is high level, so the output signal of the logic unit 262 is The high level and the second buffer control signal bufon become high during the period.

As described above, the control signal dqoff transitions to a low level from one clock clk before the CAS latency is completed to one clock clk after the burst operation is completed, and then again. Since the transition to the high level, the signal output from the inverter IV32 in the buffer on control unit 260 transitions to the high level immediately when the control signal dqoff transitions from the low level to the high level, while from the inverter IV33 The output signal, which is input to one input terminal of the NAND gate ND31, maintains the high level of the previous state during the delay section by the delay unit 261. Accordingly, since the NAND gate ND31 receives the high level 2 signal during the delay period, the signal of the node B2 becomes low level, even though the control signal writeS is transitioned to the low level. However, since the signal output from the logic unit 262 is at the low level, the second buffer control signal bufon is at the low level during the delay time by the delay unit 261.

Next, referring to the operation of the buffer controller 270 of FIG. 9, since the clock enable signal iCKE is high level and the bank active signal bankA is low level, the node B3 that is an output of the logic unit 272 is shown. Signal becomes high level, the state of the buffer enable signal (enable) is determined according to the node B6. If the data mask function is not used at this time, the data mask signal iDM is in a low level and the node B5 is at a high level, and thus the state of the buffer enable signal is enabled. Depends on the level of B4).

However, when the read command is input in the above, as shown in FIGS. 10A and 10B, as the control signal readS becomes high level and the control signal writeS becomes low level, the first buffer control signal bufoff becomes Since the low level and the second buffer control signal bufon become high level, the signal of the node B4 that is the output of the latch portion 271 becomes high level, and the NAND gate ND44 outputs a low level signal. . Therefore, when the read command is input, the buffer enable signal (enable) becomes low level, so the data input buffer 280 is turned off to stop the operation. Subsequently, even when the first buffer control signal bufoff transitions to a high level, the signal of the node B4, which is an output signal of the latch unit 271, becomes a high level in a period where the second buffer control signal bufon is high level. As a result, the buffer enable signal remains low and the data input buffer 280 continues to be turned off to not operate.

However, when the control signal dqoff transitions to the high level and the second buffer control signal bufon transitions to the low level, the signal of the node B4 becomes the low level, and thus the buffer enable signal is enabled. The data input buffer 280 is turned on.

In addition, even if the data input buffer 280 is turned off, the data mask signal iDM transitions from the low level to the high level when the data mask command is input, so that the node B5 is at the low level. The NAND gate ND44 outputs a high level signal. Accordingly, the buffer enable signal (enable) becomes a high level, the data input buffer 280 is turned on to perform the operation.

As described above, the data input circuit of the semiconductor device according to the present embodiment immediately turns off the data input buffer when a read command is input so that unnecessary current consumption does not occur. In addition, when the data mask signal is input, the data input buffer is turned on so that the data mask operation can be faithfully performed.

As described above, the data input circuit of the semiconductor device according to the present invention turns off the data input buffer immediately when a read command is input, but turns on the data input buffer when a data mask signal is input even during a read operation. As a result, the data mask operation can be faithfully performed, and the current consumption of the data input buffer can be reduced, thereby reducing the overall current consumption of the semiconductor device.

Claims (16)

A first buffer for controlling a turn-off related operation of the data input buffer by receiving a first control signal disabled during a read operation including a burst length and a second control signal enabled for a predetermined period when a read command is input. A buffer off controller for outputting a control signal; A buffer on controller configured to receive a first control signal and a third control signal disabled for a predetermined period when the read command is input and output a second buffer control signal for controlling a turn-on related operation of a data input buffer; A buffer controller which receives the first buffer control signal and the second buffer control signal and outputs a buffer enable signal; And a data input buffer enabled by the buffer enable signal to buffer input data. The method of claim 1, And the buffer controller enables the buffer enable signal regardless of the first and second buffer control signals when a data mask signal is input. The method of claim 1, And the buffer controller disables the buffer enable signal when a read command is input. The method of claim 1, The buffer control unit And a first logic element and a second logic element connected in a latch form, wherein the first logic element receives the first buffer control signal as one input terminal, and the second logic element receives the second buffer control signal as one input terminal. A latch unit which is inputted through; A buffer for buffering the data mask signal; And a first logic unit configured to logically operate the latch unit and an output signal of a buffer. The method of claim 4, wherein And the first logic element and the second logic element are NAND gates performing a negative logic operation. The method of claim 4, wherein And the first logic unit performs a negative logical product operation. The method of claim 4, wherein The buffer control unit A second logic unit for performing a logic operation on the bank active signal and the clock enable signal and outputting a result thereof; And a third logic unit configured to logically output output signals of the first logic unit and the second logic unit to output the buffer enable signal. The method of claim 7, wherein And the second logic unit and the third logic unit perform an AND operation. The method of claim 1, The buffer off control unit A delay unit for delaying the first control signal by a predetermined period; A buffer for buffering the output signal of the delayer; A first logic unit configured to logically operate the first control signal and an output signal of the buffer; And a second logic unit configured to logically operate the second control signal and the output signal of the first logic unit to output the first buffer control signal. The method of claim 9, And the first logic unit performs a negative logical product operation, and the second logic unit performs a logical product operation. The method of claim 1, The buffer on controller A delay unit for delaying the first control signal by a predetermined period; A buffer for buffering the output signal of the delayer; A first logic unit configured to logically operate the first control signal and an output signal of the buffer; And a second logic unit configured to logically operate the third control signal and the output signal of the first logic unit. The method of claim 11, The buffer on controller And a third logic unit configured to logically operate the output signal and the reset signal of the second logic unit. The method of claim 11, And the first logic unit performs a negative logical product operation, and the second logic unit performs a logical product operation. The method of claim 1, The data input buffer And a differential amplification type semiconductor input data circuit for amplifying the input data by comparing the input data with a predetermined reference voltage. The method of claim 1, And the first control signal is generated in a mode register. The method of claim 1, And the second control signal and the third control signal are generated by a command decoder.

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