JP3844939B2 - Ferroelectric semiconductor memory device with reduced test time - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor memory device using a ferroelectric, and more particularly to a ferroelectric semiconductor memory device in which the time required for device testing is shortened.
[0002]
[Prior art]
A ferroelectric semiconductor memory device (FRAM: Ferroelectric Random Access Memory) is a nonvolatile memory that uses a ferroelectric as a memory cell and records information as a difference in the position of electrons in the crystal structure of the ferroelectric.
[0003]
In the case of a DRAM (Dynamic Random Access Memory), a HIGH or LOW voltage is applied to one end of a memory capacitor as recording data, and a charge corresponding to the data is stored between the other end which is a ground. On the other hand, in the FRAM, data is not recorded only by applying a HIGH or LOW voltage to one end of the ferroelectric element. In order to record information, it is necessary to apply a positive pulse voltage to the other end of the ferroelectric element while applying a data voltage to one end of the ferroelectric element.
[0004]
The side to which the HIGH voltage is applied during data writing is called a plate and is connected to a plate line that controls the plate voltage. Simultaneously with the word selection by the word line, by selectively activating the plate line corresponding to the activated word line, data writing to the selected memory cell is performed.
[0005]
The data write operation of the FRAM is substantially the same as the data write operation of the DRAM except for the plate voltage control. In brief, the word line is activated to make the cell transistor conductive, the bit line data is written to the memory cell via the cell transistor, and after writing the data, the word line is deactivated and the cell transistor is closed. In the FRAM, data is written into the ferroelectric cell by selectively activating the plate line simultaneously with the word line selection.
[0006]
Since the ferroelectric cell has a parasitic capacitance, when the data write operation is executed as described above, in addition to the data voltage stored by the storage function of the ferroelectric, there is a charge stored in the parasitic capacitance. become. In a normal write operation, the presence of parasitic capacitance charges rather serves as a preferable factor because of the effect of enhancing the storage capability (data retention capability) of the ferroelectric memory cell.
[0007]
[Problems to be solved by the invention]
In DRAMs, FRAMs, and the like, a test for checking the memory retention capability of each memory cell is performed by repeating a data write operation and a data read operation before shipping the product. In this test, it is preferable to check the data retention capability of the ferroelectric element. However, since there is a charge of the parasitic capacitance as described above, the ferroelectric data retention capability and the DRAM-like capacitance are actually used. You will be testing your ability to add up the memory ability.
[0008]
In order to check only the data retention capability of the ferroelectric, it is necessary to wait until the charge of the parasitic capacitance disappears due to spontaneous discharge. Specifically, after data writing, a waiting time of several seconds to several minutes is taken during the test, and data is read after the charge is discharged, thereby testing the data holding ability not affected by the parasitic capacitance. .
[0009]
However, as the degree of integration of the semiconductor memory device increases, the test time becomes longer, and if it is necessary to provide the waiting time during the test as described above, the test time becomes longer.
[0010]
Accordingly, an object of the present invention is to provide an FRAM with a reduced test time.
[0011]
[Means for Solving the Problems]
According to another aspect of the present invention, a semiconductor memory device includes a memory cell made of a ferroelectric material, a bit line for transmitting data to be read from and written to the memory cell, and a cell connected between the memory cell and the bit line. A transistor, a word line for controlling on / off of the cell transistor, a word line drive circuit for driving the word line, a precharge circuit for precharging the bit line, and a precharge operation in the first state. A timing control circuit that controls the word line driving circuit and the precharge circuit so that the word line is deactivated before starting, and the word line is deactivated after the precharge operation starts in the second state; Including Thus, the first state is a normal operation state, and the second state is a test operation state. It is characterized by that.
[0012]
In the above invention, in the second state, the word line driving circuit and the precharge circuit are controlled so as to deactivate the word line after the precharge operation is started. Therefore, when the cell transistor is closed, the data voltage is set to the bit voltage. Since it is erased from the line, no data charge is stored in the parasitic capacitance of the memory cell. Therefore, it is possible to test only the data holding capability of the memory cell by the data read operation that immediately follows. In this case, it is not necessary to provide a waiting time after the data write operation and before the data read operation as in the case of the conventional test operation. Therefore, it becomes possible to test the memory cell in a short time.
[0014]
Claim 2 In the invention of claim 1 In the semiconductor memory device described above, a switch signal indicating the normal operation state or the test operation state is received from the outside of the device.
[0015]
In the above invention, the switch signal is supplied from the outside to the terminal of the semiconductor memory device, and the signal level of the switch signal is changed between the normal operation and the test operation, thereby inactivating the word line before the precharge operation starts. It is possible to switch between the operation to be activated and the operation to deactivate the word line after the precharge operation is started.
[0016]
Claim 3 In the invention of claim 1 The semiconductor memory device described above further includes a test circuit that controls a test operation, and the test circuit supplies a switch signal indicating the normal operation state or the test operation state to the timing control circuit.
[0017]
In the above-described invention, the semiconductor memory device is provided as a single package in combination with a chip of a control circuit such as a CPU. Even if the semiconductor memory device cannot be directly accessed from the outside of the package, the semiconductor memory device The test circuit provided in the circuit generates a switch signal, so that the operation of the test circuit is controlled by a control device such as a CPU, and the word line is deactivated before the precharge operation is started. And the operation of deactivating the word line after the precharge operation is started.
[0018]
Claim 4 In the semiconductor memory device according to claim 1, in the semiconductor memory device according to claim 1, the timing control circuit fixes a start timing of a precharge operation and sets a timing for deactivating a word line to the first state and the second state. It is characterized by changing between states.
[0019]
In the above invention, the memory cell can be tested under the condition that the timing of the precharge operation is the same as that in the normal operation.
[0020]
Claim 5 According to the invention, in the semiconductor memory device according to claim 1, the timing control circuit fixes a timing at which the word line is deactivated, and sets a start timing of the precharge operation to the first state and the second state. It is characterized by changing between states.
[0021]
In the above-described invention, it becomes possible to test a memory cell under the condition that the operation timing of the word line activation / deactivation is the same as that in the normal operation.
[0022]
Claim 6 In the semiconductor memory device according to claim 1, in the semiconductor memory device according to claim 1, the timing control circuit sets a timing for deactivating a word line with a fixed start timing of a precharge operation as the first state and the second state. The first operation mode to be changed between the first state and the timing for deactivating the word line is fixed, and the start timing of the precharge operation is changed between the first state and the second state. It is possible to operate in two operation modes and one of the selected operation modes.
[0023]
In the above invention, when the test is to be performed with the word line operation timing being the same as the normal write operation, and when the test is to be performed with the precharge operation timing being the same as the normal write operation In any case, it is possible to cope with it.
[0024]
Claim 7 The semiconductor memory device according to claim 7, further comprising: a unit capable of programmably setting information for determining which of the first operation mode and the second operation mode to select. Features.
[0025]
In the above invention, by providing a programmable circuit, the case where the operation timing of the word line is set to the same condition as that in the normal operation, and the case where the timing of the precharge operation is set to the same condition as in the normal operation are easy. It becomes possible to select and set to.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0027]
FIG. 1 is a diagram showing a ferroelectric semiconductor memory device to which the present invention is applied.
[0028]
1 includes an address processing unit 11, a data input / output unit 12, a control unit 13, a word decoder 14, a plate decoder 15, a column decoder 16, a cell circuit 17, a sense amplifier unit 18, and a timing control circuit 19.
[0029]
The cell circuit 17 includes a plurality of cells each having a ferroelectric as a memory element arranged vertically and horizontally, and is provided with circuits and wiring for addressing and data amplification for reading / writing data from / to each cell. Yes.
[0030]
The address processing unit 11 includes a circuit group such as an address buffer and an address predecoder, receives an address signal from the outside, and supplies the address to the word decoder 14, the plate decoder 15, and the column decoder 16 at an appropriate timing.
[0031]
The data input / output unit 12 is composed of a circuit group such as a data buffer, supplies data written from the outside to the sense amplifier unit 18 at an appropriate timing, and receives data read from the cell circuit 17 via the sense amplifier unit 18. Output to the outside at an appropriate timing. The sense amplifier unit 18 amplifies write data and supplies it to the cell circuit 17 and amplifies read data from the cell circuit 17.
[0032]
The control unit 13 is composed of a circuit group such as a control signal buffer and a command decoder, receives a control signal and a clock signal from the outside, interprets a command indicated by the control signal, and controls the operation and timing of each circuit in the FRAM 10. To do. That is, the control unit 13 supplies a clock signal and a timing signal to each unit in the FRAM 10, and each unit operates at an appropriate timing, whereby the data writing / reading operation of the FRAM 10 is realized. In FIG. 1, only the write control signal is shown as a control signal for convenience.
[0033]
The word decoder 14 decodes the row address supplied from the address processing unit 11 and activates a word line corresponding to one row address. The cell transistor connected to the activated word line is turned on, and the data write operation / data read operation for the memory cell of the selected word address is executed.
[0034]
The plate decoder 15 decodes the row address supplied from the address processing unit 11 and activates a plate line corresponding to one row address. In the FRAM, data is written by applying a HIGH voltage to the other end connected to the plate line while applying a HIGH or LOW data voltage to one end of the ferroelectric element. Simultaneously with the word selection by the word line, by selectively activating the plate line corresponding to the activated word line, data writing to the selected memory cell is performed.
[0035]
The column decoder 16 decodes the column address supplied from the address processing unit 11 and activates a column line corresponding to one column address. As a result, the corresponding column transistor is turned on, and the corresponding sense amplifier of the sense amplifier unit 18 and the data input / output unit 12 are connected.
[0036]
In the read operation, data is read from the memory cell connected to the activated word line to the bit line, and the bit line data is amplified by the sense amplifier unit 18. The amplified data is read from the sense amplifier corresponding to the activated column line and supplied to the data input / output unit 12. In the case of the write operation, contrary to the case of the read operation, data is supplied from the data input / output unit 12 to the sense amplifier selected by the activated column line, and the memory connected to the activated word line Data is written into the cell from the sense amplifier unit 18 via the bit line.
[0037]
The timing control circuit 19 is a circuit unique to the present invention, and controls the word line activation timing and the bit line precharge operation timing in accordance with the switch signal SW.
[0038]
FIG. 2 is a circuit diagram showing a configuration for controlling the word line activation timing and the bit line precharge timing.
[0039]
In FIG. 2, the timing control circuit 19 includes PMOS transistors 21 to 23, NMOS transistors 24 to 26, an inverter 27, and delay circuits 28 and 29. The timing control circuit 19 receives the switch signal SW from the outside of the FRAM 10 and also receives the timing signal TS from the control unit 13.
[0040]
The timing control circuit 19 delays the timing signal TS by a delay circuit 29 for a predetermined time, and then supplies it to the sense amplifier unit 18 as a precharge signal PR. When the switch signal SW is HIGH, the timing signal TS is supplied to the word decoder 14 via the transfer gate composed of the PMOS transistor 23 and the NMOS transistor 26. When the switch signal SW is LOW, the timing signal TS is sent to the word decoder 14 via the transfer gate composed of the PMOS transistor 21 and the NMOS transistor 24, the delay circuit 28, and the transfer gate composed of the PMOS transistor 22 and the NMOS transistor 25. Supply. Accordingly, the timing of the signal supplied to the word decoder 14 is later when the switch signal SW is LOW than when the switch signal SW is HIGH.
[0041]
The word decoder 14 includes PMOS transistors 31 and 32 and NMOS transistors 33 and 34. FIG. 2 shows only the portion related to one word line WL in the entire configuration of the word decoder 14. When an address corresponding to the illustrated word line WL is designated, the negative logic address decode signal becomes LOW, the PMOS transistor 32 is turned on, and the NMOS transistor 33 is turned off. At this time, the signal supplied from the timing control circuit 19 is LOW, the PMOS transistor 31 is conductive, and the NMOS transistor 34 is closed. As a result, the word line WL becomes HIGH. Thereafter, the signal from the timing control circuit 19 becomes HIGH. As a result, the PMOS transistor 31 is cut off and the NMOS transistor 34 is turned on. Therefore, the word line WL returns to LOW. That is, the word line WL is inactivated by the HIGH pulse from the timing control circuit 19.
[0042]
The word line WL extends to the cell circuit 17. The cell circuit 17 includes NMOS transistors 41 and 42 and memory cells 43 and 44 made of a ferroelectric material. The cell circuit 17 shown in FIG. 2 shows only a portion related to a pair of memory cells. The gates of the NMOS transistors 41 and 42 are connected to the word line WL. When the word line WL is activated, the data in the memory cells 43 and 44 are read out to the bit lines BL and / BL. One end of the memory cell 4344 is connected to the plate line PL.
[0043]
The sense amplifier unit 18 includes NMOS transistors 52 to 54 and a sense amplifier 51. The sense amplifier unit 18 of FIG. 2 shows only a part for one sense amplifier. When the precharge signal PR from the timing control circuit 19 becomes HIGH, the NMOS transistors 53 and 54 are turned on, and the bit lines BL and / BL are precharged to a precharge voltage that is a ground voltage.
[0044]
In the case of the write operation, the word line WL is activated, the NMOS transistors 41 and 42 are turned on, and the bit line data is written into the memory cells 43 and 44.
[0045]
Thereafter, in a normal write operation, the switch signal SW is HIGH, and the word line WL is inactivated before the precharge signal PR becomes HIGH. Therefore, in this case, charges corresponding to the voltage of the bit line are stored in the parasitic capacitances of the memory cells 43 and 44, and the data retention capability of the memory cells 43 and 44 is improved.
[0046]
On the other hand, in the case of the write operation during the test operation, the precharge signal PR is set to HIGH before the word line WL is inactivated by setting the switch signal to LOW. Therefore, in this case, while the word line WL is activated and the NMOS transistors 41 and 42 are conducting, the bit lines BL and / BL are precharged, and the voltage of the bit line becomes the ground voltage. Change. As a result, no charge is stored in the parasitic capacitances of the memory cells 43 and 44, and only the data holding capability of the memory cells 43 and 44 can be tested by the data read operation that immediately follows. In this case, it is not necessary to provide a waiting time after the data write operation and before the data read operation as in the case of the conventional test operation. Therefore, it becomes possible to test the memory cell in a short time.
[0047]
FIG. 3 is a timing chart for explaining the operation for controlling the word line activation timing and the bit line precharge timing.
[0048]
At the rising edge of the clock signal, write data and a write address are input, and a write control signal indicating a write operation is set to LOW. As a result, data is written in the first cycle of FIG. The timing signal is a signal generated by the control unit 13 based on the clock signal, and is a signal having a predetermined delay time from the rising edge of the clock signal. The timing signal is input to the timing control circuit 19, and generates a precharge signal PR and a signal for inactivating the word line as described with reference to FIG.
[0049]
As described above, the timing at which the word line WL is inactivated differs according to the HIGH or LOW of the switch signal SW. As shown in FIG. 3 as the word line signal WL1, when the switch signal SW is LOW, the word line WL is in an activated state for a while even if the precharge signal PR becomes HIGH. Therefore, by setting the switch signal SW to LOW during the test operation, it is possible to prevent the charge of parasitic capacitance from being stored in the memory element made of the ferroelectric. Also, as shown as the word line signal WL2, when the switch signal SW is HIGH, the word line WL is deactivated before the precharge operation is started, thereby accumulating charges in the parasitic capacitance and increasing the memory retention capability of the memory cell. Strengthen.
[0050]
In the above embodiment, the timing for deactivating the word line, that is, the timing for closing the cell transistor is adjusted with the timing of the precharge operation being constant. On the contrary, the timing at which the word line is inactivated may be fixed, and the timing at which the precharge signal PR is set to HIGH, that is, the timing at which the precharge operation is started may be adjusted.
[0051]
FIG. 4 is a configuration diagram of an embodiment in which the timing of the precharge signal is changed while the timing of deactivating the word line is constant. 4, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted.
[0052]
The timing control circuit 19A in FIG. 4 includes PMOS transistors 121 to 123, NMOS transistors 124 to 126, an inverter 127, and a delay circuit 128.
[0053]
The timing control circuit 19 receives the switch signal SW from the outside of the FRAM 10 and also receives the timing signal TS from the control unit 13.
[0054]
When the switch signal SW is HIGH, the timing control circuit 19A supplies the timing signal TS as the precharge signal PR to the sense amplifier unit 18 through the transfer gate composed of the PMOS transistor 123 and the NMOS transistor 126. When the switch signal SW is LOW, the timing signal TS is transferred to the precharge signal PR via the transfer gate composed of the PMOS transistor 121 and the NMOS transistor 124, the delay circuit 128, and the transfer gate composed of the PMOS transistor 122 and the NMOS transistor 125. To the sense amplifier unit 18. Therefore, when the switch signal SW is LOW, the timing at which the precharge signal PR becomes HIGH is later than when the switch signal SW is HIGH.
[0055]
The word decoder 14A includes a PMOS transistor 131 and an NMOS transistor 132. FIG. 2 shows only a portion related to one word line WL in the entire configuration of the word decoder 14A. When an address corresponding to the illustrated word line WL is designated, an address decode signal having a negative logic becomes LOW, the PMOS transistor 131 becomes conductive, and the NMOS transistor 132 closes. As a result, the word line WL becomes HIGH. Thereafter, when the address decode signal returns to HIGH, the PMOS transistor 131 is cut off and the NMOS transistor 132 is turned on. Therefore, the word line WL returns to LOW. That is, in the configuration of FIG. 4, the activation and deactivation timing of the word line depends on the address decode signal and is fixed regardless of the switch signal SW.
[0056]
In the configuration of FIG. 4, the circuit configurations of the cell circuit 17 and the sense amplifier unit 18 are the same as those shown in FIG.
[0057]
FIG. 5 is a timing chart for explaining the operation for controlling the bit line precharge timing with the word line activation timing fixed.
[0058]
At the rising edge of the clock signal, write data and a write address are input, and a write control signal indicating a write operation is set to LOW. As a result, data is written in the first cycle of FIG. The timing signal is a signal generated by the control unit 13 based on the clock signal, and is a signal having a predetermined delay time from the rising edge of the clock signal. The timing signal is input to the timing control circuit 19 and generates the precharge signal PR as described in FIG.
[0059]
As described above, the timing at which the word line WL is inactivated differs according to the HIGH or LOW of the switch signal SW. As shown as the precharge signal PR1 in FIG. 5, when the switch signal SW is LOW, the precharge operation starts after the word line WL is deactivated. Therefore, when the switch signal SW is LOW, the word line WL is deactivated before the precharge operation starts, so that charges are stored in the parasitic capacitance and the memory retention capability of the memory cell is enhanced. Further, as shown as the precharge signal PR1, during the test operation, the switch signal SW is set to HIGH so that the precharge operation is started before the word line is deactivated. Therefore, it is possible to prevent the charge of the parasitic capacitance from being stored.
[0060]
As shown in FIGS. 2 and 4, delay circuits are used in the timing control circuits 19 and 19A. These delay circuits can be configured by connecting several inverters, a Schmitt circuit, or the like. In this configuration, it may be designed to give different delays to the rising edge and falling edge of the input signal. For example, by appropriately adjusting the gate widths of the PMOS and NMOS transistors of the inverter constituting the delay circuit, or by appropriately adjusting the gate lengths of the PMOS and NMOS transistors, Different delays.
[0061]
The semiconductor memory device is not only provided as a single memory chip, but may be provided as a single package in combination with a chip of a control circuit such as a CPU. In such a configuration, it is often impossible to directly access the terminals of the semiconductor memory device from the outside of the package. In such a case, the semiconductor memory device can be controlled only from a control circuit such as a CPU. Therefore, it is preferable not to provide a terminal for supplying the switch signal SW, but to provide a test circuit inside the semiconductor memory device and control the operation of the test circuit from a control device such as a CPU.
[0062]
FIG. 6 is a diagram showing an FRAM according to the present invention connected to a control circuit such as a CPU. In FIG. 6, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
[0063]
The FRAM 10A in FIG. 6 includes a test circuit 150 in addition to the configuration in FIG. The timing control circuit 19 does not have a terminal for receiving a signal from the outside of the FRAM 10 </ b> A, and the switch signal SW is supplied from the test circuit 150.
[0064]
The test circuit 150 controls the test operation of the FRAM 10A in response to a command from the CPU 151 connected to the FRAM 10A. The test circuit itself is also provided in a conventional DRAM or the like, and is not unique to the present invention. However, in the present invention, the test circuit 151 is configured to output the switch signal SW in response to a command from the CPU 151. Here, the switch signal SW is a signal that only takes a HIGH or LOW value as described above, and only a technique for decoding the signal from the CPU 151 is required for its generation. Therefore, the description of the configuration for generating the switch signal SW in the test circuit 150 is omitted here.
[0065]
In the FRAM 10A of FIG. 6, the circuit configuration shown in FIG. 2 or 4 may be used as the configuration for controlling the deactivation timing of the word line or the start timing of the precharge signal in accordance with the test signal.
[0066]
In the above description, either the precharge operation timing is fixed and the word line deactivation timing is adjusted, or the word line deactivation timing is fixed and the precharge operation timing is adjusted. It was. However, in the device test, for example, when it is desired to execute the test under the same condition as the normal write operation, or the precharge operation timing is the same as the normal write operation. There are times when you want to execute.
[0067]
Therefore, during the test operation, the precharge operation timing is fixed and the deactivation timing of the word line is adjusted as necessary, or the deactivation timing of the word line is fixed and the precharge operation timing is adjusted. It is necessary to adjust or to be able to select the write operation mode during the test operation.
[0068]
FIG. 7 is a diagram showing an FRAM according to the present invention connected to a control circuit such as a CPU. In FIG. 7, the same components as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.
[0069]
In the FRAM 10B of FIG. 7, the timing control circuit 19B and the test circuit 150B are provided by replacing corresponding circuits with respect to the configuration of FIG. 6, and a programmable memory 152 is newly provided. The programmable memory 152 is programmed according to a command from the CPU 151. In the configuration of FIG. 7, it is selected whether the precharge operation timing is fixed and the word line deactivation timing is adjusted, or the word line deactivation timing is fixed and the precharge operation timing is adjusted. Therefore, in practice, it is sufficient to store 1-bit information indicating which operation mode is selected in accordance with an instruction from the CPU 151, and it is possible to configure a simple register. .
[0070]
The programmable memory 152 supplies a signal indicating which operation mode to select to the test circuit 150B. The test circuit 150B supplies the switch signal SW and the switching signal MC indicating the selected operation mode to the timing control circuit 19B. The switching signal MC may be directly supplied from the programmable memory 152 to the timing control circuit 19B.
[0071]
FIG. 8 is a circuit diagram of a timing control circuit that switches between adjusting the activation timing of the word line or adjusting the timing of the precharge operation in accordance with the switching signal.
[0072]
The timing control circuit 19B in FIG. 8 corresponds to the PMOS transistors 21 to 23, the NMOS transistors 24 to 26, the inverter 27, the delay circuits 28 and 29, and the timing control circuit 19A in FIG. 4 corresponding to the timing control circuit 19 in FIG. It includes PMOS transistors 21 to 23, NMOS transistors 24 to 26, an inverter 27, delay circuits 28 and 29, an inverter 201, PMOS transistors 202 to 205, NMOS transistors 206 to 209, and an inverter 210.
[0073]
When the switching signal CM is LOW, the transfer gate composed of the PMOS transistor 203 and the NMOS transistor 207 is opened, and a signal from the circuit portion corresponding to the timing control circuit 19 is supplied to the word decoder 14 shown in FIG. . Further, the transfer gate composed of the PMOS transistor 204 and the NMOS transistor 208 is opened, and the precharge signal PR from the circuit portion corresponding to the timing control circuit 19 is supplied to the sense amplifier unit 18.
[0074]
Therefore, when the switching signal CM is LOW, the precharge operation timing is fixed, and the timing for deactivating the word line is controlled according to the switch signal SW.
[0075]
When the switching signal CM is HIGH, the transfer gate composed of the PMOS transistor 202 and the NMOS transistor 206 is opened, and a signal that is always LOW is supplied to the word decoder 14 shown in FIG. Further, the transfer gate composed of the PMOS transistor 205 and the NMOS transistor 209 is opened, and the precharge signal PR from the circuit portion corresponding to the timing control circuit 19B is supplied to the sense amplifier unit 18.
[0076]
Therefore, when the switching signal CM is HIGH, the operation timing of the word line is fixed, and the timing of the precharge operation is controlled according to the switch signal SW.
[0077]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0078]
【The invention's effect】
In the present invention, the word line driving circuit and the precharge circuit are controlled so that the word line is deactivated after the precharge operation is started in the test operation. Therefore, when the cell transistor is closed, the data voltage is supplied from the bit line. Since the data is erased, no data charge is stored in the parasitic capacitance of the memory cell. Therefore, it is possible to test only the data holding capability of the memory cell by the data read operation that immediately follows. In this case, unlike the conventional test operation, it is not necessary to provide a waiting time after the data write operation and before the data read operation, and the memory cell can be tested in a short time.
[0079]
In addition, by supplying a switch signal from the outside to the terminal of the semiconductor memory device and changing the signal level of the switch signal between the normal operation and the test operation, the word line is deactivated before the precharge operation starts. It is possible to switch between the operation and the operation of deactivating the word line after the precharge operation is started.
[0080]
The semiconductor memory device is provided as a single package in combination with a chip of a control circuit such as a CPU. Even when the semiconductor memory device cannot be directly accessed from the outside of the package, the semiconductor memory device is provided inside the semiconductor memory device. An operation for controlling the operation of the test circuit from a control device such as a CPU and inactivating the word line before the precharge operation is started. It is possible to switch the operation of deactivating the word line after the precharge operation is started.
[0081]
Further, it is possible to test the memory cell under the condition that the timing of the precharge operation is the same as that in the normal operation. Alternatively, it is possible to test the memory cell under the condition that the operation timing of the word line activation / deactivation is the same as that in the normal operation.
[0082]
Also, if you want to run the test with the same timing as the normal write operation, and if you want to run the test with the same precharge timing as the normal write operation, In any case, it is possible to cope with it.
[Brief description of the drawings]
FIG. 1 is a diagram showing a ferroelectric semiconductor memory device to which the present invention is applied.
FIG. 2 is a circuit diagram showing a configuration for controlling word line activation timing and bit line precharge timing;
FIG. 3 is a timing chart illustrating an operation for controlling a word line activation timing and a bit line precharge timing.
FIG. 4 is a configuration diagram of an embodiment in which the timing of the precharge signal is changed while the timing of deactivating the word line is constant.
FIG. 5 is a timing chart for explaining the operation of controlling the bit line precharge timing with the word line activation timing fixed.
FIG. 6 is a diagram showing an FRAM according to the present invention connected to a control circuit such as a CPU.
FIG. 7 shows an FRAM according to the present invention connected to a control circuit such as a CPU.
FIG. 8 is a circuit diagram of a timing control circuit that switches between adjusting the activation timing of a word line or adjusting the timing of a precharge operation in accordance with a switching signal.
[Explanation of symbols]
10 FRAM
11 Address processing unit
12 Data input / output unit
13 Control unit
14 word decoder
15 Plate decoder
16 column decoder
17 Cell circuit
18 sense amplifier unit
19 Timing control circuit

Claims (7)

A memory cell made of a ferroelectric material;
A bit line for transmitting data to be read and written to the memory cell;
A cell transistor connected between the memory cell and the bit line;
A word line for controlling on / off of the cell transistor;
A word line driving circuit for driving the word line;
A precharge circuit for precharging the bit line;
In the first state, the word line driving circuit and the precharge are deactivated before the precharge operation starts, and in the second state, the word line is deactivated after the precharge operation starts. look including a timing control circuit for controlling the circuit, said first state is a normal operation state, the semiconductor memory device, wherein the second state is a test operation state. 2. The semiconductor memory device according to claim 1, wherein a switch signal indicating the normal operation state or the test operation state is received from outside the device. 2. The semiconductor memory device according to claim 1, further comprising a test circuit for controlling a test operation, wherein the test circuit supplies a switch signal indicating the normal operation state or the test operation state to the timing control circuit. . The timing control circuit fixes a start timing of a precharge operation and sets a timing for deactivating a word line. 1 State and the above 2 And changing the state between 1 The semiconductor memory device described. The timing control circuit fixes a timing for deactivating a word line and sets a start timing of a precharge operation to the first timing. 1 State and the above 2 And changing between the states of 1 The semiconductor memory device described. The timing control circuit fixes the start timing of the precharge operation and inactivates the word line at the timing for inactivating the word line. 1 State and the above 2 To change between the state of 1 The start timing of the precharge operation is fixed with the operation mode and the timing for deactivating the word line fixed. 1 State and the above 2 To change between the state of the 2 And an operation mode selected from any one of the operation modes. 1 The semiconductor memory device described. Said 1 Operating mode and the first 2 The information processing apparatus further includes a unit capable of programmably setting information for determining which operation mode to select. 6 The semiconductor memory device described.

Images