KR100772694B1 - Multi-port memory device having self-refresh mode and driving method thereof - Google Patents

Abstract

The present invention is to provide a multi-port memory for driving the self-refresh in response to one flag signal or a test signal, the present invention for receiving the flag signal to the cell refresh entering signal and the cell refresh escape signal Mode input / output control means for generating; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And internal address counting means for generating an internal address in response to the internal refresh signal.

Cell Refresh, Clock Enable Signal, Multi-Port Memory, Test Mode, Initialization

Description

MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE AND DRIVING METHOD THEREOF}

1 is a block diagram of a semiconductor memory device having a self refresh mode according to the prior art.

FIG. 2 is an internal circuit diagram of the refresh section signal generator of FIG. 1. FIG.

3 is an operational waveform diagram of a semiconductor memory device having the cell refresh mode shown in FIGS. 1 and 2;

4 is a block diagram illustrating a multi-port memory having a cell refresh mode according to a first embodiment of the present invention.

5 is an internal circuit diagram of the mode input / output controller of FIG. 4.

6 is an internal circuit diagram of the refresh section signal generation unit of FIG. 4.

7 is a simplified illustration of the process of the multi-port memory of the present invention to enter or exit the self refresh mode.

8 is an internal circuit diagram of the mode input / output controller of FIG. 4 according to a case where an initialization signal is applied.

9 is a block diagram of a multi-port memory having a cell refresh test mode according to a second embodiment of the present invention.

FIG. 10 is an internal circuit diagram of the test-clock enable signal generator of FIG. 9. FIG.

FIG. 11 is another exemplary embodiment of the test-clock enable signal generator of FIG. 9. FIG.

FIG. 12 is an internal circuit diagram of the mode input / output controller of FIG. 9. FIG.

FIG. 13 is an internal circuit diagram of another mode input / output control unit of FIG. 9. FIG.

* Explanation of symbols for the main parts of the drawings

100, 700: mode input / output control unit

200: refresh section signal generator

300: refresh cycle signal generation unit

400: internal refresh signal generator

500: internal address counting unit

600: test-clock enable signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a multi-port memory for driving self refresh with only one flag signal or test signal.

In general, in DRAM, data is stored in the cell capacitor in the form of charge, and the stored charge is lost due to leakage current or the like. Therefore, before the data is completely destroyed, a repeated process of extracting, amplifying, and rewriting the stored data at regular intervals is required. This is called a refresh operation.

Refresh is divided into auto refresh and self refresh. Here, the auto refresh is a case where the refresh is performed by applying the refresh auto refresh command AR at a predetermined time from the outside. In addition, self refresh is an operation mode designed to reduce power consumption among various operation modes of a semiconductor memory device. An external chipset simply inserts a self refresh entry command without giving a command to the semiconductor memory device. Thereafter, the semiconductor memory device performs the refresh by an internal timer until the self refresh escape command is applied. During the cell refresh mode, parts that are not related to cell refresh, such as the input buffer or delay locked loop, are turned off to minimize power consumption.

1 is a block diagram illustrating a semiconductor memory device having a self refresh mode according to the related art.

Referring to FIG. 1, a semiconductor memory device according to the related art receives a clock enable signal and an auto refresh command AR to receive an internal auto refresh signal AREFP, a cell refresh entry signal SREF_EN, and a cell refresh escape signal SREF_EXP. The self-input section signal SREF for notifying the section of the cell refresh by receiving the mode input / output control unit 10, the internal auto refresh signal AREFP, the cell refresh entrance signal SREF_EN, and the cell refresh escape signal SREF_EXP for generating a signal. A refresh period signal generator 20 for generating a C), a refresh period signal generator 30 for periodically outputting a period-pulse signal PL_FLG during activation of the cell refresh period signal SREF, and an internal auto An internal refresh signal generator 40 for activating the internal refresh signal REFP in response to the refresh signal AREFP and the period-pulse signal PL_FLG, and an internal refresh In response to the call (REFP) by increasing a row address to the internal address bit unit: and an internal address counting unit 50 for outputting a (RCNTI [N 0]).

For reference, the clock enable signal CKE is a signal indicating whether a clock for synchronizing driving of the semiconductor memory device is valid. Therefore, when only the clock enable signal is deactivated, the semiconductor memory device enters a power down mode to minimize its power consumption.

FIG. 2 is an internal circuit diagram of the refresh section signal generator 20 of FIG. 1.

Referring to FIG. 2, the refresh section signal generator 20 activates an output signal when the cell refresh entrance signal SREF_EN and the internal auto refresh signal AREFP are activated, and an output when the cell refresh escape signal SREF_EXP is activated. The signal generation unit 22 for deactivating the signal, the latch 24 for latching the output signal of the signal generation unit 22, and the output signal of the signal generation unit 22 are inverted to generate the cell refresh period signal SREF. Inverter I1 for outputting to () is provided.

Meanwhile, the driving of the refresh section signal generator 20 will be briefly described.

First, the signal generator 22 activates the output signal to the logic level 'L' when both the cell refresh entrance signal SREF_EN and the internal auto-refresh threshold signal AREFP are activated to the logic level 'H'. Subsequently, the latch 24 latches the output signal of the signal generator 22, and the inverter I1 inverts this to activate the cell refresh section signal SREF to a logic level 'H'.

In addition, when the cell fresh escape signal SREF_EXP is activated to the logic level 'L', the signal generator 22 deactivates the output signal to the logic level 'H'. Subsequently, the latch 24 latches the output signal of the signal generator 22, and the inverter I1 inverts the signal and deactivates the cell refresh period signal SREF.

That is, the refresh section signal generator 20 activates the cell refresh section signal SREF when the cell refresh entry signal SREF_EN and the internal auto refresh signal AREFP are activated, and the cell refresh exit signal SREF_EXP is applied. Keep active until Thereafter, when the cell refresh escape signal SREF_EXP is applied, the cell refresh section signal SREF is deactivated.

FIG. 3 is an operation waveform diagram of a semiconductor memory device having the cell refresh mode shown in FIGS. 1 and 2. Referring to this, the driving of the cell refresh is described.

As shown in FIG. 3, first, the clock enable signal CKE transitions to a logic level 'L', and the auto refresh command AR is activated.

Subsequently, the mode input / output controller 10 activates the cell refresh entry signal SREF_EN in response to the logic level transition of the clock enable signal CKE, and in response to the auto refresh command AR, an internal auto refresh signal AREFP. Activate.

Subsequently, the internal refresh signal generator 40 generates an internal refresh signal REFP in response to the internal auto refresh signal AREFP.

Subsequently, the internal address generator 50 increases the row address in units of one bit every time the internal refresh signal REFP is activated, and outputs the row address as the internal address RCNTI [0: N].

In addition, the refresh section signal generator 20 activates the cell refresh section signal SREF in response to the activation of the internal auto refresh signal AREFP and the cell refresh entry signal SREF_EN, which is a cell refresh escape signal SREF_EXP. Is maintained until is applied.

Subsequently, the refresh period signal generator 30 periodically activates the period-pulse signal PL_FLG during the activation of the cell refresh period signal SREF.

Subsequently, the internal refresh signal generator 40 activates a new internal refresh signal REFP in the form of a pulse every time the period-pulse signal PL_FLG is applied.

Subsequently, the internal address generator 50 increases the row address in units of one bit every time the internal refresh signal REFP is activated, and outputs the row address as the internal address RCNTI [0: N].

For reference, the internal refresh signal REFP is applied to each bank so that a word line corresponding to the internal address RCNTI [0: N] is activated to perform cell refresh.

As described above, the semiconductor memory device according to the related art enters the cell refresh mode when the clock enable signal CKE is deactivated to the logic level 'L' and is applied with the auto refresh command AR. When the clock enable signal CKE is activated at the logic level 'H', the cell refresh is terminated.

As described above, the semiconductor memory device according to the related art enters the cell refresh mode when the clock enable signal and the auto refresh command are applied together. This is to distinguish the case from entering the cell refresh mode since the auto-down command is applied together with the clock enable signal since only the clock enable signal is deactivated.

On the other hand, the applicant has filed a content regarding the multi-port memory, for example, the application number 10-2006-32948.

As such, in the multi-port memory, the power down mode and the cell refresh are not separately performed. Therefore, a new cell refresh driving method is needed in a multi-port memory.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a multi-port memory for driving self-refresh in response to one flag signal or a test signal and a driving method thereof. .

According to an aspect of the present invention, there is provided a multi-port memory including mode input / output control means for generating a cell refresh entry signal and a cell refresh escape signal by receiving a flag signal; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And internal address counting means for generating an internal address in response to the internal refresh signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a cell refresh apparatus of a multi-port memory according to a first embodiment of the present invention.

Referring to FIG. 4, the cell refresh apparatus according to the first embodiment of the present invention receives a clock enable signal CKE to generate a mode of the cell refresh entry signal SREF_EN and the cell refresh escape signal SREF_EXP. The controller 100 and the refresh interval signal generator 200 for generating the cell refresh interval signal SREF indicating the cell refresh interval in response to the cell refresh entrance signal SREF_EN and the cell refresh escape signal SREF_EXP. The refresh cycle signal generator 300 periodically generates the cycle-pulse signal PL_FLG during the activation of the cell refresh period signal SREF, the cell refresh entrance signal SREF_EN and the cycle-pulse signal PL_FLG. An internal refresh signal generator 400 for generating an internal refresh signal REFP and an internal address RCNTI [0: N] for generating an internal refresh signal REFP in response to the internal refresh signal REFP. The sub address counting unit 500 is provided.

Comparing the cell refresh apparatus of the multi-port memory according to the present invention with the prior art illustrated in FIG. 1, in the present invention, the mode input / output controller 100 for detecting the entry into the cell refresh mode includes a clock enable signal ( Only the cell refresh entry signal SREF_EN and the cell refresh escape signal SREF_EXP are generated by receiving only CKE, and the refresh period signal generator 200 applies only the cell refresh entrance signal SREF_EN and the cell refresh escape signal SREF_EXP. I can see it.

As such, it can be seen that the cell refresh apparatus according to the first embodiment enters or exits the cell refresh mode by receiving only the clock enable signal CKE. Thus, it has a simpler circuit implementation.

For reference, the other blocks except for the mode input / output controller 100 and the refresh period signal generator 200 have the same circuit implementation as the prior art. Therefore, the internal circuit diagrams of the mode input / output controller 100 and the refresh period signal generator 200 will be described below with reference to the accompanying drawings.

FIG. 5 is an internal circuit diagram of the mode input / output controller 100A of FIG. 4.

Referring to FIG. 5, the mode input / output controller 100A detects a deactivation of the clock enable signal CKE and generates a cell refresh entry signal generator 120 for generating a cell refresh entry signal SREF_EN, and a clock in. The cell refresh escape signal generator 140 is configured to detect the activation of the enable signal CKE and generate the cell refresh escape signal SREF_EXP.

In detail, the cell refresh entry signal generation unit 120 receives the clock enable signal CKE as a set signal and receives the feedback signal as a reset signal, and the output of the RS latch 122 is fixed. An inversion delay unit 124 for delaying and inverting the output signal as a feedback signal, a NAND gate ND1 having a positive output and a feedback signal as an input, and an output signal of the NAND gate ND1 by inverting the cell refresh entry signal. An inverter I2 for outputting to SREF_EN is included.

The cell refresh escape signal generation unit 140 receives an inverter I3 for inverting the clock enable signal CKE, an output signal of the inverter I3 as a set signal, and an RS receiving the feedback signal as a reset signal. A latch 142, an inversion delay unit 144 for delaying and inverting the positive output of the RS latch 142 and outputting it as a feedback signal, a NAND gate ND2 having a positive output and a feedback signal as an input, and a NAND And a delay unit 146 for delaying the output signal of the gate ND2 and outputting the cell refresh escape signal SREF_EXP.

Next, the operation of the mode input / output controller 100A will be briefly described.

First, the clock enable signal CKE is deactivated to the logic level 'L'.

Subsequently, the RS latch 122 in the cell-fresh entry signal generation unit 120 activates the cell-fresh entry signal SREF_EN to a logic level 'H' in response to the feedback after the delay time of the inversion delay unit 144. Since the signal has a logic level 'L', the cell refresh entry signal SREF_EN is inactivated.

Subsequently, when the clock enable signal CKE is activated at the logic level 'H', the RS latch 142 in the cell refresh escape signal generation unit 140 responds to the cell refresh escape signal SREF_EXP at the logic level 'L'. It is activated as', and is deactivated to the logic level 'H' after the delay time of the inversion delay unit 144.

That is, the mode input / output control unit 100A detects when the clock enable signal CKE transitions from the logic level 'H' to the logic level 'L' and makes the cell refresh entry signal SREF_EN high in pulse form. When the clock enable signal CKE is activated again to the logic level 'H', the clock enable signal CKE is sensed to activate the pulsed cell refresh escape signal SREF_EXP low.

Therefore, the cell refresh apparatus including the mode input / output controller 100A described above enters or exits the cell refresh mode by detecting only a change in the logic level of the clock enable signal CKE.

6 is an internal circuit diagram of the refresh period signal generator 200 of FIG. 4.

Referring to FIG. 6, the refresh period signal generator 200 activates the output signal in response to the cell refresh entrance signal SREF_EN and deactivates the output signal in response to the cell refresh escape signal SREF_EXP. 220, a latch 240 for latching and outputting the output signal of the signal generator 220, and an inverter for inverting the output signal of the signal generator 240 and outputting the cell refresh interval signal SREF. (I4) is provided.

The signal generator 220 has a cell refresh entry signal SREF_EN as a gate input, a PMOS transistor PM1 having a source-drain path between an external voltage VDD and an output node N1, and a cell refresh escape signal An NMOS transistor NM1 having a SREF_EXP as a gate input and having a drain-source path between the output node N1 and the ground voltage VSS is provided, and the voltage applied to the output node N1 is output as an output signal.

Next, the operation of the refresh section signal generator 200 will be described briefly.

First, when the cell refresh entrance signal SREF_EN is activated to the logic level 'H', the signal generator 220 activates the output signal to the logic level 'L' until the cell refresh escape signal SREF_EXP is applied. Keep it. Next, the latch 240 latches the output signal to the signal generator 220, and the inverter I4 inverts the output signal and outputs the cell refresh period signal SREF activated at the logic level 'H'.

In addition, when the cell refresh escape signal SREF_EXP is activated to a logic level 'L', the signal generator 220 deactivates the output signal and maintains it until the cell refresh entrance signal SREF_EN is applied. Subsequently, the latch 240 latches the output signal of the signal generator 220, and the inverter I4 inverts the output signal to deactivate the cell refresh period signal SREF.

That is, the refresh section signal generator 200 activates the cell refresh section signal SREF in response to the activation of the cell refresh entrance signal SREF_EN and deactivates the cell refresh exit signal SREF_EXP when the cell refresh exit signal SREF_EXP is applied. Accordingly, the cell refresh section signal SREF is continuously activated to a logic level 'H' during the cell refresh mode, indicating that the cell refresh section signal SREF is in the cell refresh mode.

Meanwhile, the driving of the cell refresh device illustrated in FIGS. 4 to 6 will be briefly described.

First, when the clock enable signal CKE is deactivated to the logic level 'L', the mode input / output controller 100 activates the cell refresh entry signal SREF_EN. Next, the refresh section signal generator 200 activates the cell refresh section signal SREF. Subsequently, the refresh period signal generator 300 activates the pulse-type period-pulse signal PL_FLG at intervals of a predetermined period while the cell refresh period signal SREF is activated. Subsequently, the internal refresh signal generator 400 generates an internal refresh signal REFP in response to the cell refresh entry signal SREF_EN, and generates a new internal refresh signal in the form of a pulse each time the periodic-pulse signal PL_FLG is activated. REFP). In addition, the internal address counting unit 500 increases the row address in units of one bit every time the internal refresh signal REFP is activated, and outputs the row address as the internal address RCNTI [0: N].

In addition, when the clock enable signal CKE is activated to the logic level 'H', the mode input / output controller 100 activates the cell refresh escape signal SREF_EXP so that the cell refresh section signal SREF is a cell refresh section signal ( SREF) is deactivated. Therefore, the refresh refresh cycle signal generator 300 terminates the driving in response to the deactivation of the cell refresh section signal SREF. In addition, since the period-pulse signal PL_FLG is not applied to the internal refresh signal generator 400, the internal refresh signal generator 400 does not generate the internal refresh signal REFP. Subsequently, the internal address counting unit 500 stops driving since the internal refresh signal REFP is not applied.

For reference, although not illustrated, an internal refresh signal REFP is applied to each bank to activate a word line corresponding to the internal address RCNTI [0: N] to perform cell refresh.

As described above, FIG. 7 briefly illustrates a process of entering or exiting the cell refresh apparatus of the present invention.

Referring to FIG. 7, the cell refresh apparatus of the multi-port memory according to the present invention enters the cell refresh mode when the clock enable signal CKE has a logic level 'L'. When the clock enable signal CKE is activated to the logic level 'H', it exits from the cell refresh mode.

That is, while entering the cell refresh mode by sensing the application of the auto refresh command AR together with the clock enable signal CKE, the present invention is to enter the cell refresh mode with only the clock enable signal CKE. Able to know.

Accordingly, the cell refresh apparatus according to the present invention has a simpler circuit implementation than the prior art. In addition, the input buffer for receiving the auto refresh command AR does not always need to be active.

On the other hand, by applying the initialization signal (RST) to the mode input and output control unit 100, it is possible to ensure that the cell refresh entry signal (SREF_EN) and the cell refresh escape signal (SREF_EXP) has a constant level without an error during the initial drive. This will be described in detail with reference to the accompanying drawings.

FIG. 8 is an internal circuit diagram of the mode input / output controller 100B of FIG. 4 according to a case where an initialization signal RST is applied.

Referring to FIG. 8, upon initial driving, the stable mode input / output control unit 100B detects the deactivation of the clock enable signal CKE to generate the cell refresh entry signal SREF_EN, and the cell refresh upon application of the initialization signal RST. The cell refresh entry signal generation unit 160 for initializing the entry signal SREF_EN and the cell enable escape signal SREF_EXP are generated by sensing the activation of the clock enable signal CKE and applying the initialization signal RST. And a cell refresh escape signal generation unit 180 for initializing the cell refresh escape signal SREF_EXP.

Referring to FIG. 8, the mode input / output control unit 100B shown in FIG. 8 has the same circuit implementation, and the initialization signal RST is respectively converted into the cell-fresh entry signal generation unit 160 and the cell-fresh escape signal generation unit ( 180) The difference is that it is applied as reset signal of RS latch. Accordingly, when the initialization signal RST, which is a reset signal, is activated to a logic level 'L', the cell refresh entry signal generator 160 and the cell refresh escape signal generator 180 respond to the cell refresh entry signal SREF_EN. Denotes a logic level 'L', and the cell refresh escape signal SREF_EXP has a logic level 'H'.

In addition, since the driving according to the level shift of the clock enable signal CKE is the same, the description thereof will be omitted.

As such, the mode input / output controller 100B according to another exemplary embodiment illustrated in FIG. 8 further receives the initialization signal RST, and thus, the cell refresh entry signal SREF_EN and the cell refresh escape signal SREF_EXP are initially applied. Have a stable level.

On the other hand, the following describes a cell refresh device that can enter the cell refresh mode in the test mode.

9 is a block diagram illustrating a cell refresh apparatus having a test mode of a multi-port memory according to a second embodiment of the present invention.

Referring to FIG. 9, the cell refresh apparatus according to the second embodiment of the present invention includes a test-clock enable signal generator 600 for outputting a test-clock enable signal CKE_TST, and a test signal TST_EN. A mode input / output controller 700 for generating a cell refresh entry signal SREF_EN and a cell refresh escape signal SREF_EXP by receiving a clock enable signal CKE or a test-clock enable signal CKE_TST in response thereto; The refresh section signal generator 200 for generating the cell refresh section signal SREF indicating the cell refresh section in response to the cell refresh entering signal SREF_EN and the cell refresh escape signal SREF_EXP, and the cell refresh section signal During the activation of SREF, the refresh cycle signal generator 300 periodically generates the cycle-pulse signal PL_FLG, and responds to the cell refresh entry signal SREF_EN and the cycle-pulse signal PL_FLG. The internal refresh signal generation unit 400 for generating the internal refresh signal REFP and the internal address counting unit 500 for generating the internal address RCNTI [0: N] in response to the internal refresh signal REFP. ).

Comparing the cell refresh apparatus according to the second exemplary embodiment with the first exemplary embodiment illustrated in FIG. 4, the cell refresh apparatus further includes a test clock enable signal generator 600 to generate a test clock enable signal CKE_TST. do. In addition, the test signal TST_EN may be applied to the mode input / output controller 700 to enter or exit the cell refresh mode in response to the test-clock enable signal CKE_TST. Therefore, even when the clock enable signal CKE is not applied during the test, the driving of the cell refresh can be tested regardless of this.

In addition, in the normal operation, it receives the clock enable signal CKE input from the outside, enters the cell refresh mode, and performs the cell refresh. Therefore, in the following, only the test-clock enable signal generator 600 and the mode input / output controller 700 will be described.

FIG. 10 is an internal circuit diagram of the test-clock enable signal generator 600A of FIG. 9.

As illustrated in FIG. 10, the test-clock enable signal generator 600A may directly apply a test-clock enable signal CKE_TST signal from the outside during the test as the pad 620.

FIG. 11 is another exemplary embodiment of the test-clock enable signal generator 600B of FIG. 9.

Referring to FIG. 11, the test-clock enable signal generator 600B generates a signal in response to a decoding unit 640 for decoding the test codes TST_CD1 and TST_CD2 and an output signal of the decoding unit 640. The flag generator 660 for resetting, the latch 680 for inverting, latching and outputting the output signal of the flag generator 660, and the test-clock enable signal by delaying the output signal of the latch 680. And a delay unit 690 for outputting to (CKE_TST).

As described above, the test-clock enable signal generator 600B shown in FIG. 11 decodes the test codes TST_CD1 and TST_CD2 to output the test-clock enable signal CKE_TST. That is, the test-clock enable signal CKE_TST may be generated through the combination of the test codes TST_CD1 and TST_CD2 applied in the test mode.

For reference, the output signals TEST1 and TEST2 of the decoding unit 640 may be used for other driving during the test mode.

FIG. 12 is an internal circuit diagram of the mode input / output controller 700A of FIG. 9.

Referring to FIG. 12, the mode input / output controller 700A may include a selection unit 710 for selectively transferring a clock enable signal CKE or a test-clock enable signal CKE_TST in response to a test signal TST_EN. In response to the output signal of the selection unit 710, the cell refresh entry signal generator 720 for generating the cell refresh entry signal SREF_EN, and the cell refresh escape signal in response to the output signal of the selection unit 710 And a cell fresh escape signal generator 730 for generating SREF_EXP.

For reference, comparing this with the mode input / output control unit 100A shown in FIG. 5, it can be seen that it further includes only the selection unit 710, and the other blocks have the same circuit implementation. Therefore, only the selection unit 710 will be described in detail.

Here, the selector 710 transfers the clock enable signal CKE to the cell refresh entry signal generator 720 in response to the deactivation of the test signal TST_EN and the test signal TST_EN. In response to the activation of the test gate TG3 and the test signal TST_EN for transmitting the clock enable signal CKE to the cell fresh escape signal generation unit 730 in response to the deactivation of the control signal, the test-clock enable signal CKE_TST. Transfers the test-clock enable signal CKE_TST to the cell refresh escape signal generator 730 in response to the transfer gate TG2 and the test signal TST_EN activated to transmit the signal to the cell refresh entrance signal generator 720. Transfergate TG4 to be included.

In brief, when the test signal TST_EN is deactivated, the selector selects the cell enable refresh signal CKE and the cell refresh entry signal generator 720 and the cell refresh escape signal generator 730 when the transfer gates TG1 and TG3 are activated. ) Is applied. Subsequently, when the clock enable signal CKE transitions to the logic level 'L', the cell refresh entry signal generator 720 activates the cell refresh entry signal SREF_EN and the cell refresh escape signal generator 730. Activates the cell refresh escape signal SREF_EXP when the clock enable signal CKE transitions to a logic level 'H'.

In addition, when the test signal TST_EN is activated, the selector 710 activates the transfer gates TG2 and TG4 to generate the test-clock enable signal CKE_TST and the cell-fresh entry signal generator 720 and the cell-fresh escape signal, respectively. Applied to the unit 730. Subsequently, when the test-clock enable signal CKE_TST transitions to the logic level 'L', the cell refresh entry signal generator 720 activates the cell refresh entry signal SREF_EN and the cell refresh escape signal generator 730 activates the cell fresh escape signal SREF_EXP when the test-clock enable signal CKE_TST transitions to a logic level 'H'.

As described above, in the test mode in which the test signal TST_EN is activated, the cell refresh apparatus of the multi-port memory according to the second embodiment is directly applied through the pad 600A or the test code TST_CD1 or TST_CD2. The cell refresh is performed in response to the test-clock enable signal CKE_TST generated through the combination. That is, the cell refresh driving can be tested regardless of the on / off state of the input buffer for applying the clock enable signal CKE in the test mode.

In addition, in the normal mode in which the test signal TST_EN is inactivated, it can be seen that normal cell refresh is performed in response to the clock enable signal CKE.

Meanwhile, the level of the cell refresh entrance signal SREF_EN and the cell fresh escape signal SREF_EXP may be stabilized upon initial driving by receiving the initialization signal RST. This will be described with reference to the accompanying drawings.

FIG. 13 is an internal circuit diagram of another embodiment of the mode input / output controller 700B shown in FIG. 9.

Comparing the mode input / output control unit 700B according to FIG. 13 with FIG. 12, the mode input / output control unit 700A according to another embodiment has the same circuit implementation, but the cell-fresh entry signal generation unit 740 and the cell-fresh escape. It can be seen that only the point where the initialization signal RST is applied to the signal generator 750 is different.

In addition, it can be seen that the cell refresh entry signal generator 740 and the cell refresh escape signal generator 750 have the same circuit implementation as in FIG. 6.

Accordingly, when the initialization signal RST is activated, the mode input / output controller 700B according to another embodiment may perform the cell refresh entry signal regardless of the level of the clock enable signal CKE or the test-clock enable signal CKE_TST. It can be seen that (SREF_EN) is deactivated to logic level 'L' and the cell fresh escape signal SREF_EXP is deactivated to logic level 'H'. In the test mode, the same driving as in FIG. 12 is performed, and thus the description thereof will be omitted.

Therefore, in the test mode in which the test signal TST_EN is activated, the cell refresh apparatus having the test mode according to the second embodiment shown in FIGS. 9 to 13 may be directly applied from the outside or a combination of the test codes TST_CD1 and TST_CD2 may be used. The cell refresh is performed in response to the test-clock enable signal CKE_TST. That is, not only the cell refresh driving can be tested during the test mode, but also this can be performed regardless of the application or level change of the clock enable signal CKE.

Meanwhile, the cell refresh apparatus of the multi-port memory according to the first and second embodiments may enter or escape the cell refresh using only one signal of the clock enable signal CKE. Accordingly, the present invention has a simpler circuit implementation than when the clock enable signal CKE and the auto refresh command AR were to be applied together. In addition, the driving of the cell refresh can be tested in the test mode.

Meanwhile, in the above-described present invention, the case of entering the cell refresh in response to the deactivation of the clock enable signal and escaping in response to the activation is described. However, at the specific logic level of the signal replacing the clock enable signal or the clock enable signal. Not limited by For example, it may enter cell refresh during the activation of the clock enable signal and may exit upon deactivation.

Meanwhile, in the above-described embodiment of the present invention, the case of entering the cell refresh in response to the logic level of the clock enable signal is exemplified. However, this is not limited to the clock enable signal. In response to the flag signal can be implemented to input and output in the cell refresh mode.

Meanwhile, the present invention exemplifies a case in which a test-clock enable signal is generated by receiving a test code of 2 bits, but the idea of the present invention is not limited by the number of bits of the test code.

Meanwhile, the above-described present invention proposes a new cell refresh apparatus of a multi-port memory, but it is also applicable to a conventional semiconductor memory device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the cell refresh can be performed using only one flag signal, and the normal performance can be tested.

Claims (30)

Mode input / output control means for receiving a flag signal to generate a cell refresh entry signal and a cell refresh escape signal; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And Internal address counting means for generating an internal address in response to the internal refresh signal Multi-port memory having. The method of claim 1, The mode input and output control means, A cell refresh entry signal generation unit for generating the cell refresh entry signal by detecting the deactivation of the flag signal; And a cell fresh escape signal generator for generating the cell fresh escape signal by detecting activation of the flag signal. Multi-port memory characterized by. The method of claim 2, The cell refresh entry signal generation unit, A first RS latch receiving the flag signal as a set signal and receiving a first feedback signal as a reset signal; A first inversion delay unit for delaying and inverting a constant output of the first RS latch to output the first feedback signal; A first NAND gate having the constant output and the first feedback signal as an input; And a first inverter for inverting the output signal of the first NAND gate to output the cell refresh entry signal. Multi-port memory characterized by. The method of claim 3, The cell fresh escape signal generation unit, A second inverter for inverting the flag signal; A second RS latch receiving an output signal of the second inverter as a set signal and receiving a second feedback signal as a reset signal; A second inversion delay unit for delaying and inverting a constant output of the second RS latch to output the second feedback signal; A second NAND gate having the positive output and the second feedback signal as inputs; And a delay unit for delaying an output signal of the second NAND gate to output the cell refresh escape signal. Multi-port memory characterized by. Mode input / output control means for generating a cell refresh entry signal and a cell refresh escape signal upon receiving a flag signal, and deactivating the cell refresh entry signal and the cell refresh escape signal in response to an initialization signal; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And Internal address counting means for generating an internal address in response to the internal refresh signal Multi-port memory having. The method of claim 5, The mode input and output control means, A cell refresh entry signal generation unit for generating the cell refresh entry signal by detecting the deactivation of the flag signal, and initializing the cell refresh entry signal when the initialization signal is applied; Detecting the activation of the flag signal to generate the cell fresh escape signal, wherein the cell fresh escape signal generation unit is configured to initialize the cell fresh escape signal upon application of the initialization signal; Multi-port memory characterized by. The method of claim 6, The cell refresh entry signal generation unit, A first RS latch receiving the flag signal as a set signal and a first feedback signal as a reset signal; A first inversion delay unit for delaying and inverting a constant output of the first RS latch to output the first feedback signal; A first NAND gate having the positive output, the first feedback signal, and the initialization signal as an input; And a first inverter for inverting the output signal of the first NAND gate to output the cell refresh entry signal. Multi-port memory characterized by. The method of claim 7, wherein The cell fresh escape signal generation unit, A second inverter for inverting the flag signal; A second RS latch receiving an output signal of the second inverter as a set signal and receiving a second feedback signal as a reset signal; A second inversion delay unit for delaying and inverting a constant output of the second RS latch to output the second feedback signal; A second NAND gate having the positive output, the second feedback signal, and the initialization signal as an input; And a delay unit for delaying an output signal of the second NAND gate to output the cell refresh escape signal. Multi-port memory characterized by. The method according to claim 4 or 8, The refresh section signal generating means, A signal generator for activating an output signal in response to the cell refresh entry signal and deactivating an output signal in response to the cell fresh escape signal; A latch for latching and outputting an output signal of the signal generator; And a third inverter for inverting the output signal of the signal generator and outputting the signal as the cell refresh section signal. Multi-port memory characterized by. The method of claim 9, The signal generator, A PMOS transistor having the cell refresh entry signal as a gate input and having a source-drain path between an external voltage and an output node; An NMOS transistor having the cell refresh escape signal as a gate input and having a drain-source path between the output node and a ground voltage, Outputting the voltage across the output node as the output signal Multi-port memory characterized by. Entering a cell refresh mode in response to deactivation of the flag signal; And Exiting the cell refresh mode in response to the activation of the flag signal; Method of driving a multi-port memory having a. The method of claim 11, The step of entering, Generating an entry signal in response to deactivation of the flag signal; Activating the section signal in response to the entry signal; Activating a period-pulse signal at intervals of a predetermined period during activation of the interval signal; Generating a new internal refresh signal for performing a cell refresh in response to the activation of the entry signal or the period-pulse signal; And outputting an internal address by incrementing a row address by one bit every time the internal refresh signal is activated. A method of driving a multi-port memory, characterized in that. Test-flag signal generating means for outputting a test-flag signal; Mode input / output control means for receiving a flag signal or the test-flag signal in response to a test signal to generate a cell refresh entry signal and a cell refresh escape signal; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And Internal address counting means for generating an internal address in response to the internal refresh signal Multi-port memory having. The method of claim 13, And said test flag flag generating means is a pad, for directly applying said test flag flag from outside. The method of claim 13, The test flag flag generating means, A decoding unit for decoding a plurality of test codes; A signal generator for activating an output signal in response to the output signal of the decoder; A first latch for inverting, latching, and outputting an output signal of the signal generator; And a first delay unit for delaying an output signal of the first latch and outputting the test-flag signal. Multi-port memory characterized by. The method according to claim 14 or 15, The mode input and output control means, A selection unit for selectively transferring the flag signal or the test-flag signal in response to the test signal; A cell refresh entry signal generation unit for generating the cell refresh entry signal in response to an output signal of the selection unit; And a cell fresh escape signal generator for generating the cell fresh escape signal in response to an output signal of the selector. Multi-port memory characterized by. The method of claim 16, The selection unit, A first transfer gate configured to transfer the flag signal to the cell refresh entry signal generator and the cell refresh escape signal generator in response to deactivation of the test signal; And a second transfer gate configured to transfer the test-flag signal to the cell refresh entrance signal generator and the cell fresh escape signal generator in response to the activation of the test signal. Multi-port memory characterized by. The method of claim 17, The cell refresh entry signal generation unit, A first RS latch receiving the output signal of the selector as a set signal and receiving a first feedback signal as a reset signal; A first inversion delay unit for delaying and inverting a constant output of the first RS latch to output the first feedback signal; A first NAND gate having the constant output and the first feedback signal as an input; And a first inverter for inverting the output signal of the first NAND gate to output the cell refresh entry signal. Multi-port memory characterized by. The method of claim 18, The cell fresh escape signal generation unit, A second inverter for inverting the output signal of the selection unit; A second RS latch receiving an output signal of the second inverter as a set signal and receiving a second feedback signal as a reset signal; A second inversion delay unit for delaying and inverting a constant output of the second RS latch to output the second feedback signal; A second NAND gate having the positive output and the second feedback signal as inputs; And a delay unit for delaying an output signal of the second NAND gate to output the cell refresh escape signal. Multi-port memory characterized by. Test-flag signal generating means for outputting a test-flag signal; A mode input / output for generating a cell refresh entrance signal and a cell refresh escape signal by receiving a flag signal or the test-flag signal in response to a test signal, and deactivating the cell refresh entrance signal and the cell refresh escape signal in response to an initialization signal. Control means; Refresh interval signal generation means for generating a cell refresh interval signal indicating a cell refresh interval in response to the cell refresh entry signal and the cell refresh escape signal; Refresh period signal generating means for generating a periodic pulse signal periodically during the activation of the cell refresh period signal; Internal refresh signal generating means for generating an internal refresh signal in response to the cell refresh entry signal and the period-pulse signal; And Internal address counting means for generating an internal address in response to the internal refresh signal Multi-port memory having. The method of claim 20, And said test flag flag generating means is a pad, for directly applying said test flag flag from outside. The method of claim 20, The test flag flag generating means, A decoding unit for decoding a plurality of test codes; A signal generator for activating an output signal in response to the output signal of the decoder; A first latch for inverting, latching, and outputting an output signal of the signal generator; And a first delay unit for delaying an output signal of the first latch and outputting the test-flag signal. Multi-port memory characterized by. The method of claim 21 or 22, The mode input and output control means, A selection unit for selectively transferring the flag signal or the test-flag signal in response to the test signal; A cell refresh entry signal generation unit for generating the cell refresh entry signal by sensing an output signal of the selection unit, and initializing the cell refresh entry signal when the initialization signal is applied; Sensing the output signal of the selector to generate the cell fresh escape signal, and having a cell fresh escape signal generator for initializing the cell fresh escape signal upon application of the initialization signal; Multi-port memory characterized by. The method of claim 23, wherein The selection unit, A first transfer gate configured to transfer the flag signal to the cell refresh entry signal generator and the cell refresh escape signal generator in response to deactivation of the test signal; And a second transfer gate configured to transfer the test-flag signal to the cell refresh entrance signal generator and the cell fresh escape signal generator in response to the activation of the test signal. Multi-port memory characterized by. The method of claim 24, The cell refresh entry signal generation unit, A first RS latch receiving the output signal of the selector as a set signal and receiving a first feedback signal as a reset signal; A first inversion delay unit for delaying and inverting a constant output of the first RS latch to output the first feedback signal; A first NAND gate having the positive output, the first feedback signal, and the initialization signal as an input; And a first inverter for inverting the output signal of the first NAND gate to output the cell refresh entry signal. Multi-port memory characterized by. The method of claim 25, The cell fresh escape signal generation unit, A second inverter for inverting the flag signal; A second RS latch receiving an output signal of the second inverter as a set signal and receiving a second feedback signal as a reset signal; A second inversion delay unit for delaying and inverting a constant output of the second RS latch to output the second feedback signal; A second NAND gate having the positive output, the second feedback signal, and the initialization signal as an input; And a delay unit for delaying an output signal of the second NAND gate to output the cell refresh escape signal. Multi-port memory characterized by. Entering a cell refresh mode in response to deactivation of the test-flag signal applied in the test mode; And Exiting the cell refresh mode in response to activation of the test-flag signal Method of driving a multi-port memory having a. The method of claim 27, And the test-flag signal is externally applied through a pad. The method of claim 27, And the test-flag signal is generated by a combination of a plurality of test codes. The method of claim 28 or 29, The step of entering, Generating an entry signal in response to deactivation of the test flag flag; Activating the section signal when the entry signal is activated; Activating a period-pulse signal at intervals of a predetermined period during activation of the interval signal; Generating a new internal refresh signal for performing cell refresh in response to activation of the entry signal and the period-pulse signal; And outputting an internal address by incrementing a row address by one bit every time the internal refresh signal is activated. A method of driving a multi-port memory, characterized in that.

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