JPWO2015173906A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
Description
本発明の実施の形態1について説明する前に、図9と図10を用いて、前提技術に係る半導体装置の構成について説明する。図9は、前提技術に係る半導体装置の断面図であり、図10は、前提技術に係る別の半導体装置の断面図である。
次に、本発明の実施の形態1について、図面を用いて以下に説明する。図1は、実施の形態1に係る半導体装置の製造方法において、リードフレーム4,5を金型9内に配置した状態を示す断面図であり、図2(a)は、半導体装置の製造方法において、金型9内に樹脂8を注入している状態を示す断面図であり、図2(b)は、樹脂7および樹脂8の硬化後の状態を示す図である。なお、実施の形態1において、前提技術で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態2に係る半導体装置の製造方法について説明する。図4は、実施の形態2に係る半導体装置の製造方法において、上型キャビティ11で樹脂8および樹脂7を圧縮している状態を示す断面図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態3に係る半導体装置の製造方法について説明する。図5は、実施の形態3に係る半導体装置の製造方法において、リードフレーム4,5を金型9内に配置した状態を示す断面図であり、図6は、半導体装置の製造方法において、可動ピン12で仮圧縮している状態を示す断面図であり、図7は、半導体装置の製造方法において、金型9内に樹脂8を注入した後、可動ピン12を金型9から引き抜いた状態を示す断面図である。なお、実施の形態3において、実施の形態1,2で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態4に係る半導体装置の製造方法について説明する。図8(a)は、実施の形態4に係る半導体装置の製造方法において、金型9内に樹脂8を注入している状態を示す断面図であり、図8(b)は、樹脂7および樹脂8の硬化後の状態を示す図である。なお、実施の形態4において、実施の形態1から3で説明したものと同一の構成要素については同一符号を付して説明は省略する。
Claims (9)
- (a)半導体素子(6a)が搭載されたダイパッド(4a)を有するリードフレーム(4)を準備する工程と、
(b)金型(9)内において、粒状の第1樹脂(7)を配置する工程と、
(c)前記第1樹脂(7)が前記ダイパッド(4a)の下側に接触するように、前記リードフレーム(4)を前記金型(9)内に配置する工程と、
(d)前記金型(9)内において前記第1樹脂(7)の上側に第2樹脂(8)を充填する工程と、
(e)前記第1樹脂(7)および前記第2樹脂(8)を硬化させることで成型する工程と、
を備える、半導体装置の製造方法。 - 前記工程(b)は、金型(9)内において、粉末状または破砕状である前記第1樹脂(7)を配置する工程である、請求項1記載の半導体装置の製造方法。
- 前記金型(9)は、前記半導体素子(6a)の側方から前記第2樹脂(8)を注入するためのサイドゲート(9c)を備え、
前記工程(d)は、前記金型(9)の前記サイドゲート(9c)から前記第2樹脂(8)を注入することで充填する工程であり、
前記工程(e)は、前記第2樹脂(8)で前記第1樹脂(7)を圧縮しながら成型する工程である、請求項1記載の半導体装置の製造方法。 - 前記金型(9)は、前記半導体素子(6a)の上方から前記第2樹脂(8)を注入するためのトップゲート(9d)を備え、
前記工程(d)は、前記金型(9)の前記トップゲート(9d)から前記第2樹脂(8)を注入することで充填する工程であり、
前記工程(e)は、前記第2樹脂(8)で前記第1樹脂(7)を圧縮しながら成型する工程である、請求項1記載の半導体装置の製造方法。 - 前記金型(9)は、前記リードフレーム(4)が配置される下金型(9a)と、前記下金型(9a)に対して下方に移動させることで前記第2樹脂(8)および前記第1樹脂(7)を圧縮する上型キャビティ(11)とを備え、
前記工程(d)は、粒状に形成された前記第2樹脂(8)を前記金型(9)内に散布することで充填する工程であり、
前記工程(e)は、前記下金型(9a)に対して前記上型キャビティ(11)を下方に移動させることで前記第2樹脂(8)および前記第1樹脂(7)を圧縮しながら成型する工程である、請求項1記載の半導体装置の製造方法。 - 前記工程(b)は、金型(9)内において、前記第2樹脂(8)よりも大きな絶縁特性を有する前記第1樹脂(7)を配置する工程である、請求項1記載の半導体装置の製造方法。
- 前記工程(b)は、金型(9)内において、前記第2樹脂(8)よりも大きな放熱特性を有する前記第1樹脂(7)を配置する工程である、請求項1記載の半導体装置の製造方法。
- (f)前記工程(c)の後、前記ダイパッド(4a)を下側に押さえつけるための可動ピン(12)で前記ダイパッド(4a)を下側に押さえつけることで前記第1樹脂を仮圧縮する工程と、
(g)前記工程(d)の後、前記可動ピン(12)を前記金型(9)内から引き抜く工程と、
をさらに備える、請求項1記載の半導体装置の製造方法。 - 前記工程(a)は、前記リードフレーム(4a)に代えて、複数の半導体素子(6a)が搭載された個片化される前の絶縁基板(14)を準備する工程であり、
前記工程(c)は、前記第1樹脂(7)が前記絶縁基板(14)の下側に接触するように、前記絶縁基板(14)を前記金型(9)内に配置する工程である、請求項1記載の半導体装置の製造方法。
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US20190371625A1 (en) * | 2017-02-27 | 2019-12-05 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62150755A (ja) * | 1985-12-25 | 1987-07-04 | Hitachi Ltd | 電子装置およびその製造方法 |
JPH05198707A (ja) * | 1992-01-22 | 1993-08-06 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JPH0837270A (ja) * | 1994-07-26 | 1996-02-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2010274495A (ja) * | 2009-05-28 | 2010-12-09 | Towa Corp | 電子部品の樹脂封止用の成形型及び樹脂封止方法 |
JP2014036046A (ja) * | 2012-08-07 | 2014-02-24 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2014187209A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 半導体装置 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0434958A (ja) | 1990-05-31 | 1992-02-05 | Toshiba Corp | 樹脂封止型半導体装置およびその製造方法 |
JP3199963B2 (ja) | 1994-10-06 | 2001-08-20 | 株式会社東芝 | 半導体装置の製造方法 |
JP3897478B2 (ja) * | 1999-03-31 | 2007-03-22 | 松下電器産業株式会社 | 樹脂封止型半導体装置の製造装置及びその製造方法 |
JP4007741B2 (ja) | 2000-01-12 | 2007-11-14 | 三菱電機株式会社 | 半導体装置 |
JP3784684B2 (ja) | 2001-10-04 | 2006-06-14 | 三菱電機株式会社 | 樹脂パッケージ型半導体装置の製造方法 |
JP4553813B2 (ja) | 2005-08-29 | 2010-09-29 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
JP4422094B2 (ja) * | 2005-12-12 | 2010-02-24 | 三菱電機株式会社 | 半導体装置 |
MY148064A (en) | 2006-10-30 | 2013-02-28 | Sumitomo Bakelite Co | Liquid resin composition, semiconductor wafer having adhesive layer, semiconductor element having adhesive layer, semiconductor package , process for manufacturing semiconductor element and process for manufacturing semiconductor package. |
JP5285285B2 (ja) | 2008-01-29 | 2013-09-11 | Towa株式会社 | 半導体チップの圧縮成形方法 |
MY152342A (en) * | 2008-12-10 | 2014-09-15 | Sumitomo Bakelite Co | Granular epoxy resin composition for encapsulating semiconductor, semiconductor device using the same and method for producing semiconductor device |
JP2010162710A (ja) * | 2009-01-13 | 2010-07-29 | Sumitomo Heavy Ind Ltd | 樹脂封止装置及び樹脂封止方法 |
JP5150597B2 (ja) * | 2009-10-08 | 2013-02-20 | 新電元工業株式会社 | 半導体パッケージ及びその製造方法 |
WO2011158753A1 (ja) | 2010-06-17 | 2011-12-22 | 日立化成工業株式会社 | 樹脂ペースト組成物 |
JP5563917B2 (ja) | 2010-07-22 | 2014-07-30 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置及びその製造方法 |
JP4965715B1 (ja) | 2011-02-03 | 2012-07-04 | ナミックス株式会社 | エポキシ樹脂組成物およびそれを用いた半導体封止材 |
JP5811492B2 (ja) | 2011-04-28 | 2015-11-11 | 三菱化学株式会社 | デバイス製造方法 |
JP5828990B2 (ja) * | 2013-09-30 | 2015-12-09 | リンテック株式会社 | 樹脂膜形成用複合シート |
JP6191453B2 (ja) * | 2013-12-27 | 2017-09-06 | 日亜化学工業株式会社 | 発光装置 |
US10262912B2 (en) * | 2015-04-15 | 2019-04-16 | Mitsubishi Electric Corporation | Semiconductor device |
JP2017147272A (ja) * | 2016-02-15 | 2017-08-24 | ローム株式会社 | 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体 |
-
2014
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- 2014-05-14 JP JP2016519032A patent/JP6469660B2/ja active Active
- 2014-05-14 WO PCT/JP2014/062829 patent/WO2015173906A1/ja active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62150755A (ja) * | 1985-12-25 | 1987-07-04 | Hitachi Ltd | 電子装置およびその製造方法 |
JPH05198707A (ja) * | 1992-01-22 | 1993-08-06 | Nec Kyushu Ltd | 半導体装置の製造方法 |
JPH0837270A (ja) * | 1994-07-26 | 1996-02-06 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2010274495A (ja) * | 2009-05-28 | 2010-12-09 | Towa Corp | 電子部品の樹脂封止用の成形型及び樹脂封止方法 |
JP2014036046A (ja) * | 2012-08-07 | 2014-02-24 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2014187209A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 半導体装置 |
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