JPS6135714B2 - - Google Patents

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Publication number
JPS6135714B2
JPS6135714B2 JP54014099A JP1409979A JPS6135714B2 JP S6135714 B2 JPS6135714 B2 JP S6135714B2 JP 54014099 A JP54014099 A JP 54014099A JP 1409979 A JP1409979 A JP 1409979A JP S6135714 B2 JPS6135714 B2 JP S6135714B2
Authority
JP
Japan
Prior art keywords
electrode
pad
gate electrode
bonding pad
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54014099A
Other languages
English (en)
Other versions
JPS55108775A (en
Inventor
Yutaka Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1409979A priority Critical patent/JPS55108775A/ja
Priority to EP80300256A priority patent/EP0015072B1/en
Priority to DE8080300256T priority patent/DE3063218D1/de
Priority to US06/118,225 priority patent/US4298879A/en
Publication of JPS55108775A publication Critical patent/JPS55108775A/ja
Publication of JPS6135714B2 publication Critical patent/JPS6135714B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は、GaAs・FET（GaAs電界効果トラ
ンジスタ）のような半導体装置の改良に関する。
従来、GaAs.FETは４〔ＧHz〕から18〔ＧHz〕
近辺までの高周波増幅、発振などを行なう装置と
して多用され、近年は益々大出力化される傾向に
ある。大出力化するにはゲート幅を大にする必要
があり、また、第１図に見られるような櫛歯形構
造を採つている。
第１図に於いて、１はメサ型能動領域、２はソ
ース電極、２Ａはソース・コンタクト窓、３はド
レイン電極、３Ａはドレイン・コンタクト窓、４
はゲート電極をそれぞれ示す。
第２図は第１図の線Ａ―A′に於ける断面図、
第３図は同じく線Ｂ―B′に於ける断面図、第４図
は同じく線Ｃ―C′に於ける断面図であり、第１
図に関して説明した部分と同部分を同記号で指示
してある。
図に於いて、１１は半絶縁性単結晶基板、１２
はバツフア層、１３はGaAs動作層、１４は二酸
化シリコンの絶縁層をそれぞれ示す。
さて、このような半導体装置を使用可能な状態
にするには第５図に見られるようなシート接地法
に依りパツケージに実装する手法が採られる。
第５図に於いて、２１は電源の接地側母線、、
２２はＬ字形金シート、２３は金・錫のソルダ、
２４は半導体チツプ、２５はドレイン・リードの
接続領域、２６はゲート・リードの接続領域であ
る。尚、金シート２２は図に表われている起立し
た部分と、金・錫ソルダ２３で覆われて見えない
平面部分とからなるＬ字形をなしている。
通常、この種のFETはソース接地の状態で使
用され、従つて、ソース・インダクタンスを減少
させないと良好な高周波特性を期待できない。そ
こで、第５図に見られる実装方法が採られている
のである。この方法に依るとソースは最短距離
で、しかも、大面積で接地されるのでソース・イ
ンダクタンスは大幅に低減される。
ところで、半導体チツプ２４の表面で金・錫ソ
ルダ２３が付着する部分は第１図で見た場合、ソ
ース・コンタクト窓２Ａの下方エツジ部分、即
ち、ゲート電極４のボンデイング・パツドより下
方の部分に金・錫ソルダが被着されるものである
が、この接地部分とFETとして活性な部分との
距離は出来る限り短縮することが望ましいが、従
来の装置では250〔μｍ〕程度が一般的であり、
その為に電力利得が充分にとれない、特に大出力
のFET、例えばゲート幅20〔mm〕のものでは８
〔ＧHz〕で約１〔dB〕の電力利得しか得られな
い。一般に、ゲート幅が大きくなればなる程、接
地端のインダクタンスを小さくしなければならな
い。
前記したところから明らかなように、FETの
特性を改善するには、接地部分と活性部分との間
の距間を短かくする必要があるけれども、第１図
から明らかなように、その距離を規定する要因と
なつているのはゲート電極４に於けるボンデイン
グ・パツドの部分である。
本発明は、前記のようなFETに於けるゲート
電極のボンデイング・パツド部分及びソース電極
を改善し、前記した接地部分と活性部分の間の距
離を短縮してインダクタンスを更に減少させ、高
周波大出力を取り出し得るように、また、ゲート
電極外部リード引出し用パツドとドレイン電極の
ボンデイング・パツドとの間に接地されるソース
電極の一部を介在させて入出力を分離し、高周波
の漏れに依る発振を防止するようにしたものであ
り、以下、これを説明する。
第６図は本発明一実施例の要部平面図、第７図
は第６図の線Ｄ―D′に於ける断面図であり、第
１図乃至第４図に関して説明した部分と同部分を
同記号で指示してある。
本発明実施例が従来例と相違する点はメサ型能
動領域が１Ａ，１Ｂの二つに分割され、その間に
形成された空所にゲート電極４のボンデイング・
パツド４′を配設したことである。
このような構成にすると、ボンデイング・パツ
ド４′は櫛歯形構造の部分から張出さないから、
活性部分と接地部分との間の距離を著しく短かく
することができ、従来の構造で250〜350〔μｍ〕
であつたものを150〔μｍ〕以下にすることがで
きた。
さて、一般に、この種FETではゲートが入
力、ドレインが出力になつている。従つて、ゲー
ト電極のボンデイング・パツドとドレイン電極の
ボンデイング・パツドが接近した場合、そのまま
では発振する惧れがある。しかしながら、前記実
施例ではドレイン電極３のボンデイング・パツド
とゲート電極４のボンデイング・パッド４′との
間にはソース電極２の一部が介在しているので、
入出力間に高周波信号の漏れを生ずることは殆ん
どなく発振は生じない。
以上の説明で判るように、本発明装置に依れ
ば、ゲート電極のボンデイング・パツド、即ち、
外部リード引出し用パツドが、複数に分割された
活性動作部分の間に生じた空所に配置された構成
になつているので、接地部分と活性動作部分との
間の距離を著しく短縮することができ、また、ソ
ース電極は、その一部がチツプのエツジに沿つて
延在し且つ一部が前記ゲート電極外部リード引出
し用パツドとドレイン電極のボンデイング・パツ
ドとの間に介在した構成になつているので、第５
図に見られる構成を採るか或いはチツプ側面にメ
タライズ層を形成した構成にして接地する場合に
有利であり、また、ソース電極は接地されるもの
であるから、前記構成に依り、入出力間、即ち、
ゲート電極外部リード引出し用パツドとドレイン
電極のボンデイング・パツド間が分離され、それ
等の間に高周波の漏れが発生せず、従つて、無用
な発振が生ずることはなくなる。
このようなことから、接地インダクタンスは減
少し、利得は２〔dB〕以上も大になり、安定指
数も改善される。
【図面の簡単な説明】
第１図は従来例の平面図、第２図乃至第４図は
第１図の要所に於ける断面図、第５図は半導体チ
ツプの実装状態を説明する斜視図、第６図は本発
明一実施例の要部平面図、第７図は第６図の線Ｄ
―D′に於ける断面図である。 図に於いて、１，１Ａ，１Ｂはメサ型能動領
域、２はソース電極、２Ａはソース・コンタクト
窓、３はドレイン電極、３Ａはドレイン・コンタ
クト窓、４はゲート電極、４′はボンデイング・
パツドである。

Claims (1)

    【特許請求の範囲】
  1. １ 櫛型電極構造を有し、且つ、接地される電極
    とグラウンドとの間を半導体チツプ側面を経由し
    て電気的に接続する半導体装置に於いて、複数個
    に分割された活性動作部分と、それ等活性動作部
    分の間の空間に形成されたゲート電極外部リード
    引出し用パツドと、一部が前記櫛型電極の配列方
    向に沿うと共に前記半導体チツプのエツジにも沿
    つて延在し且つ一部が前記ゲート電極外部リード
    引出し用パツドとドレイン電極のボンデイング・
    バツドとの間に介在して入出力を分離しているソ
    ース電極とを有してなることを特徴とする半導体
    装置。
JP1409979A 1979-02-09 1979-02-09 Semiconductor device Granted JPS55108775A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1409979A JPS55108775A (en) 1979-02-09 1979-02-09 Semiconductor device
EP80300256A EP0015072B1 (en) 1979-02-09 1980-01-29 A field effect transistor
DE8080300256T DE3063218D1 (en) 1979-02-09 1980-01-29 A field effect transistor
US06/118,225 US4298879A (en) 1979-02-09 1980-02-04 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1409979A JPS55108775A (en) 1979-02-09 1979-02-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55108775A JPS55108775A (en) 1980-08-21
JPS6135714B2 true JPS6135714B2 (ja) 1986-08-14

Family

ID=11851660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1409979A Granted JPS55108775A (en) 1979-02-09 1979-02-09 Semiconductor device

Country Status (4)

Country Link
US (1) US4298879A (ja)
EP (1) EP0015072B1 (ja)
JP (1) JPS55108775A (ja)
DE (1) DE3063218D1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010098243A (ja) * 2008-10-20 2010-04-30 Renesas Technology Corp 半導体装置

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JPS57117276A (en) * 1981-01-14 1982-07-21 Hitachi Ltd Semiconductor device
CA1200017A (en) * 1981-12-04 1986-01-28 Ho C. Huang Microwave field effect transistor
US4684965A (en) * 1983-05-09 1987-08-04 Raytheon Company Monolithic programmable attenuator
US4587541A (en) * 1983-07-28 1986-05-06 Cornell Research Foundation, Inc. Monolithic coplanar waveguide travelling wave transistor amplifier
DE3578533D1 (de) * 1984-04-28 1990-08-09 Sony Corp Halbleiterbauelement mit von source- und/oder drain-gebieten umgebenen anschlussflaechen.
JPS6276568A (ja) * 1985-09-28 1987-04-08 Sharp Corp 電界効果トランジスタ
JPH0770733B2 (ja) * 1988-02-22 1995-07-31 株式会社東芝 半導体装置とその使用方法
US4870478A (en) * 1988-04-21 1989-09-26 Motorola, Inc. Dual-gate gallium arsenide power metal semiconductor field effect transistor
US5023677A (en) * 1990-05-02 1991-06-11 Texas Instruments Incorporated Low parasitic FET topology for power and low noise GaAs FETs
JPH04252036A (ja) * 1991-01-10 1992-09-08 Fujitsu Ltd 半導体装置
US5199136A (en) * 1991-05-16 1993-04-06 Coors Ceramicon Designs, Ltd. Button for articles of clothing
JP2637937B2 (ja) * 1995-01-30 1997-08-06 関西日本電気株式会社 電界効果トランジスタの製造方法
JP3189691B2 (ja) * 1996-07-10 2001-07-16 株式会社村田製作所 高周波半導体デバイス
JPH11136111A (ja) * 1997-10-30 1999-05-21 Sony Corp 高周波回路
US6774416B2 (en) * 2001-07-16 2004-08-10 Nanowave, Inc Small area cascode FET structure operating at mm-wave frequencies
FR2911005B1 (fr) * 2006-12-27 2009-06-12 St Microelectronics Sa Transistor mos adapte a la tenue de forts courants

Citations (1)

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JPS5192185A (ja) * 1975-02-10 1976-08-12

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US3969745A (en) * 1974-09-18 1976-07-13 Texas Instruments Incorporated Interconnection in multi element planar structures
US3986196A (en) * 1975-06-30 1976-10-12 Varian Associates Through-substrate source contact for microwave FET
US4141021A (en) * 1977-02-14 1979-02-20 Varian Associates, Inc. Field effect transistor having source and gate electrodes on opposite faces of active layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192185A (ja) * 1975-02-10 1976-08-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010098243A (ja) * 2008-10-20 2010-04-30 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
EP0015072B1 (en) 1983-05-18
DE3063218D1 (en) 1983-07-07
JPS55108775A (en) 1980-08-21
US4298879A (en) 1981-11-03
EP0015072A1 (en) 1980-09-03

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