JPS59161846A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59161846A
JPS59161846A JP58036962A JP3696283A JPS59161846A JP S59161846 A JPS59161846 A JP S59161846A JP 58036962 A JP58036962 A JP 58036962A JP 3696283 A JP3696283 A JP 3696283A JP S59161846 A JPS59161846 A JP S59161846A
Authority
JP
Japan
Prior art keywords
terminals
resin
resin body
lead
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58036962A
Other languages
English (en)
Inventor
Masayuki Arai
荒井　眞幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58036962A priority Critical patent/JPS59161846A/ja
Publication of JPS59161846A publication Critical patent/JPS59161846A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、半導体素子を樹脂で包んで、該半導体素子の
電極と直接またはボンディングワイヤで導電接続したリ
ード端子を前記封止樹脂体の外部に引き出した形の樹脂
封止半導体装置に関する。
第１図はこのような樹脂封止半導体装置の従来例の断面
図である。図において、リードフレームの半導体素子搭
載部に搭載された半導体素子１の電極とリード端子２と
がホンディングワイヤ３で導電接続されたのち、樹脂４
で包み外部界囲気から保護されている。
このような従来の樹脂封止半導体装置では、リード端子
２の封止樹脂体４の引き出し根本から湿気が浸入し易い
とか、また、相隣るリード端子間のマイグレーションの
発生、および、樹脂封止時に金型からのにじみがあるな
どの欠点がある。
本発明の目的は、上記の欠点を取除いた樹脂封止半導体
装置を提供するにある。
本発明の半導体装置は、封止樹脂体に包まれた半導体素
子に導電接続して前記封止樹脂体の外部に引出されたリ
ード端子の、前記封止樹脂体の表面と交差する部分の内
側と外側にわたる一部分、を、フィルム状樹脂で予じめ
被覆した後、前記樹脂封止がなされた構成を有する。
本発明によれば、リード端子が封止樹脂体から引出され
た引出し根元部がフィルム状樹脂と封止樹脂の二層構造
をとっているので、この根本部からの湿気の浸入および
相隣るリード端子間の耐圧低下が防止できる。
つぎに本発明を実施例により説明する。
第２図は本発明の一実施例の断面図である。第２図にお
いて、リード端子２が封止樹脂体４の表面と父差する部
分の内側と外側にまたがる一部分に、封止樹脂体４で封
止する前に予じめ形成した、ポリイミドまたはポリエス
テルなどの耐熱性フィルム樹脂層５で被覆されている。
このフィルム便脂層５があることにより、樹脂封止の隙
にリードフレームの金型に対するクッションになるため
、リード端子２の封止樹脂のにじみがなく、また、相隣
るリード端子間の沿面距離が犬となり、その結果、湿気
の浸入および微小リークならびにマイグレーションの減
小が得られ、耐圧が向上する。
第３図は本発明の他の実施例の製造工程途中の部分平面
図である。図において、リードフレームの外枠２ａから
引き出された多数のリード端子２．。
２、・・・・・・における、封止樹脂体の表面と交差す
る部分Ｘ−Ｘの内側、外側にまだがり、各リード端子２
．２．・・・を部分的に耐熱性の樹脂フィルム６で覆っ
ている。なお、樹脂フィルム６は隣り合うリード端子の
間をも基いでつながって形成されている。
つぎに第４図（ａ）の部分平面図および、同図（ｂ）の
リード端子引出し側の側面図に示すように、半導体索子
１およびリード端子２，２．・・・の先端部を含めて封
止樹脂体４で包んでいる。本例の耐熱性樹脂６は、各リ
ード端子の封止樹脂体４からの引出し根本を覆うと共に
、各リード端子間の部分をも塞いでいるので、封止樹脂
体４に吸湿性があっても、第２図の実施例の場合よりも
一層絶縁性が向上されてのる。
【図面の簡単な説明】
第１図は従来の樹脂封止半導体装置の断面図、第２図は
本発明の一実施例の断面図、第３図は本発明の他の実施
例の製造工程途中の部分平面図、第４図（ａ）　、　（
ｂ）はそれぞれ第３図の工程を経た本発明の他の実施例
の部分平面図と部分側面図である。 １・・・・・・半導体素子、２・・・・・・リード端子
％　２ａ・・・・・リード端子外枠、３・・・・・・ボ
ンディング勝、４・・・・・・封止樹脂体、５，６・・
・・・・耐熱性樹脂フィルム。 パぐ炒′ 第　１　区 第２図 （θ） （１７） 第４図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子を樹脂で包み、前記半導体系子と導電接続し
    たリード端子を前記封止樹脂体の外部に引き出してなる
    樹脂封止半導体装置において、前記リード端子の前記封
    止樹脂体の表面と交差する部分の内側と外側にわたる一
    部分を予じめフィルム状樹脂で被覆した後前記封止樹脂
    体で包んでなることを特徴とする半導体装置。
JP58036962A 1983-03-07 1983-03-07 半導体装置 Pending JPS59161846A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58036962A JPS59161846A (ja) 1983-03-07 1983-03-07 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58036962A JPS59161846A (ja) 1983-03-07 1983-03-07 半導体装置

Publications (1)

Publication Number Publication Date
JPS59161846A true JPS59161846A (ja) 1984-09-12

Family

ID=12484357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58036962A Pending JPS59161846A (ja) 1983-03-07 1983-03-07 半導体装置

Country Status (1)

Country Link
JP (1) JPS59161846A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265845A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体装置
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPS6473751A (en) * 1987-09-16 1989-03-20 Toshiba Chem Corp Resin sealed semiconductor device
JPH0461363A (ja) * 1990-06-29 1992-02-27 Nec Corp 表面実装型プラスチックパッケージ

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265845A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体装置
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPS6473751A (en) * 1987-09-16 1989-03-20 Toshiba Chem Corp Resin sealed semiconductor device
JPH0461363A (ja) * 1990-06-29 1992-02-27 Nec Corp 表面実装型プラスチックパッケージ

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