JPH10303289A - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法Info
- Publication number
- JPH10303289A JPH10303289A JP9112467A JP11246797A JPH10303289A JP H10303289 A JPH10303289 A JP H10303289A JP 9112467 A JP9112467 A JP 9112467A JP 11246797 A JP11246797 A JP 11246797A JP H10303289 A JPH10303289 A JP H10303289A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- groove
- semiconductor substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Priority Applications (15)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9112467A JPH10303289A (ja) | 1997-04-30 | 1997-04-30 | 半導体集積回路装置の製造方法 |
| TW087102181A TW388100B (en) | 1997-02-18 | 1998-02-17 | Semiconductor deivce and process for producing the same |
| CNB021571880A CN1284224C (zh) | 1997-02-18 | 1998-02-18 | 半导体器件及其制造工艺 |
| CN98802666A CN1112727C (zh) | 1997-02-18 | 1998-02-18 | 半导体器件及其制造工艺 |
| PCT/JP1998/000671 WO1998036452A1 (en) | 1997-02-18 | 1998-02-18 | Semiconductor device and process for producing the same |
| US09/367,524 US6242323B1 (en) | 1997-02-18 | 1998-02-18 | Semiconductor device and process for producing the same |
| CNB031306020A CN100521146C (zh) | 1997-02-18 | 1998-02-18 | 半导体器件的制造工艺 |
| US09/066,757 US6057241A (en) | 1997-04-30 | 1998-04-27 | Method of manufacturing a semiconductor integrated circuit device |
| TW087106611A TW418492B (en) | 1997-04-30 | 1998-04-29 | Method of manufacturing a semiconductor integrated circuit device |
| KR1019980015280A KR19980081825A (ko) | 1997-04-30 | 1998-04-29 | 반도체 집적회로장치의 제조방법 |
| MYPI98000689A MY121321A (en) | 1997-02-18 | 1998-08-11 | Semiconductor device and process for producing the same |
| KR1019997007482A KR100307000B1 (ko) | 1997-02-18 | 1999-08-18 | 반도체 장치 및 그 제조 공정 |
| US09/845,338 US6559027B2 (en) | 1997-02-18 | 2001-05-01 | Semiconductor device and process for producing the sme |
| US10/392,916 US6881646B2 (en) | 1997-02-18 | 2003-03-21 | Semiconductor device and process for producing the same |
| US11/108,827 US7402473B2 (en) | 1997-02-18 | 2005-04-19 | Semiconductor device and process for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9112467A JPH10303289A (ja) | 1997-04-30 | 1997-04-30 | 半導体集積回路装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10303289A true JPH10303289A (ja) | 1998-11-13 |
| JPH10303289A5 JPH10303289A5 (enExample) | 2005-02-10 |
Family
ID=14587379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9112467A Pending JPH10303289A (ja) | 1997-02-18 | 1997-04-30 | 半導体集積回路装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6057241A (enExample) |
| JP (1) | JPH10303289A (enExample) |
| KR (1) | KR19980081825A (enExample) |
| TW (1) | TW418492B (enExample) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2001332613A (ja) * | 2000-05-24 | 2001-11-30 | Nec Corp | 半導体装置の製造方法 |
| KR100345400B1 (ko) * | 1999-10-08 | 2002-07-26 | 한국전자통신연구원 | 가장자리에 두꺼운 산화막을 갖는 트렌치 형성방법 |
| US6518144B2 (en) | 2000-10-10 | 2003-02-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having trenches and process for same |
| JP2003249546A (ja) * | 2003-01-06 | 2003-09-05 | Seiko Epson Corp | 半導体ウエハおよびその処理方法ならびに半導体装置の製造方法 |
| JP2004510330A (ja) * | 2000-09-18 | 2004-04-02 | モトローラ・インコーポレイテッド | 半導体装置及びその形成プロセス |
| WO2005119758A1 (ja) * | 2004-06-04 | 2005-12-15 | Az Electronic Materials (Japan) K.K. | トレンチ・アイソレーション構造の形成方法 |
| JP2007184609A (ja) * | 2005-12-29 | 2007-07-19 | Dongbu Electronics Co Ltd | トレンチ形成方法 |
| JP2009283494A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP2009283493A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP2009283492A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4592837B2 (ja) * | 1998-07-31 | 2010-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2000082808A (ja) * | 1998-09-04 | 2000-03-21 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6599812B1 (en) * | 1998-10-23 | 2003-07-29 | Stmicroelectronics S.R.L. | Manufacturing method for a thick oxide layer |
| JP3571236B2 (ja) * | 1998-11-09 | 2004-09-29 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| JP3955404B2 (ja) * | 1998-12-28 | 2007-08-08 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
| JP4012350B2 (ja) * | 1999-10-06 | 2007-11-21 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
| JP2001345375A (ja) * | 2000-05-31 | 2001-12-14 | Miyazaki Oki Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
| US6451704B1 (en) * | 2001-05-07 | 2002-09-17 | Chartered Semiconductor Manufacturing Ltd. | Method for forming PLDD structure with minimized lateral dopant diffusion |
| ITTO20011038A1 (it) * | 2001-10-30 | 2003-04-30 | St Microelectronics Srl | Procedimento per la fabbricazione di una fetta semiconduttrice integrante dispositivi elettronici e una struttura per il disaccoppiamento el |
| JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| DE10259728B4 (de) * | 2002-12-19 | 2008-01-17 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Grabenisolationsstruktur und Verfahren zum Steuern eines Grades an Kantenrundung einer Grabenisolationsstruktur in einem Halbleiterbauelement |
| JP2006332404A (ja) * | 2005-05-27 | 2006-12-07 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
| WO2020098738A1 (en) * | 2018-11-16 | 2020-05-22 | Changxin Memory Technologies, Inc. | Semiconductor device and fabricating method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4576834A (en) * | 1985-05-20 | 1986-03-18 | Ncr Corporation | Method for forming trench isolation structures |
| US4693781A (en) * | 1986-06-26 | 1987-09-15 | Motorola, Inc. | Trench formation process |
| JPH07105436B2 (ja) * | 1986-07-18 | 1995-11-13 | 株式会社東芝 | 半導体装置の製造方法 |
| US4906585A (en) * | 1987-08-04 | 1990-03-06 | Siemens Aktiengesellschaft | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches |
-
1997
- 1997-04-30 JP JP9112467A patent/JPH10303289A/ja active Pending
-
1998
- 1998-04-27 US US09/066,757 patent/US6057241A/en not_active Expired - Lifetime
- 1998-04-29 KR KR1019980015280A patent/KR19980081825A/ko not_active Withdrawn
- 1998-04-29 TW TW087106611A patent/TW418492B/zh not_active IP Right Cessation
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100345400B1 (ko) * | 1999-10-08 | 2002-07-26 | 한국전자통신연구원 | 가장자리에 두꺼운 산화막을 갖는 트렌치 형성방법 |
| JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2001332613A (ja) * | 2000-05-24 | 2001-11-30 | Nec Corp | 半導体装置の製造方法 |
| JP2004510330A (ja) * | 2000-09-18 | 2004-04-02 | モトローラ・インコーポレイテッド | 半導体装置及びその形成プロセス |
| US6518144B2 (en) | 2000-10-10 | 2003-02-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having trenches and process for same |
| JP2003249546A (ja) * | 2003-01-06 | 2003-09-05 | Seiko Epson Corp | 半導体ウエハおよびその処理方法ならびに半導体装置の製造方法 |
| WO2005119758A1 (ja) * | 2004-06-04 | 2005-12-15 | Az Electronic Materials (Japan) K.K. | トレンチ・アイソレーション構造の形成方法 |
| JP2005347636A (ja) * | 2004-06-04 | 2005-12-15 | Az Electronic Materials Kk | トレンチ・アイソレーション構造の形成方法 |
| JP2007184609A (ja) * | 2005-12-29 | 2007-07-19 | Dongbu Electronics Co Ltd | トレンチ形成方法 |
| JP2009283494A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP2009283493A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP2009283492A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW418492B (en) | 2001-01-11 |
| US6057241A (en) | 2000-05-02 |
| KR19980081825A (ko) | 1998-11-25 |
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