JPH09508502A - 半導体素子を有し導体トラックが形成されている基板が接着層により結合されている支持本体を有する半導体装置 - Google Patents
半導体素子を有し導体トラックが形成されている基板が接着層により結合されている支持本体を有する半導体装置Info
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- JPH09508502A JPH09508502A JP8516697A JP51669796A JPH09508502A JP H09508502 A JPH09508502 A JP H09508502A JP 8516697 A JP8516697 A JP 8516697A JP 51669796 A JP51669796 A JP 51669796A JP H09508502 A JPH09508502 A JP H09508502A
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.基板が接着層により結合されている支持本体を有する半導体装置であって、 前記基板には、前記支持本体と対向する第1の側に半導体素子が形成され、さら に基板の支持本体とは反対の第2の側から外部接続するための接点電極(又は、 ボンドパッド)を有する導体トラックのパターンが形成されている半導体装置に おいて、 前記外部接続用の接点電極を有する導体トラックのパターンが基板の第1の 側に形成され、基板のボンドパッドの領域に第2の側から外部接続するための窓 が形成されていることを特徴とする半導体装置。 2.請求項1に記載の半導体装置において、前記基板が絶縁性材料層で構成され 、前記半導体素子が基板の第1の側に存在するシリコン層に形成されていること を特徴とする半導体装置。 3.請求項2に記載の半導体装置において、前記シリコン層が、半導体素子が存 在するアイランド部に隣接するシリコン酸化物に変換され、前記接点電極が前記 アイランド部に隣接するシリコン酸化物層に形成されていることを特徴とする半 導体装置。 4.請求項2に記載の半導体装置において、前記シリコン層が基板上にアイラン ド部の形態で局部的に存在し、前記接点電極が前記シリコンアイランド部に隣接 して基板上に直接形成されていることを特徴とする半導体装置。 5.請求項2、3又は4に記載の半導体装置において、前記半導体基板がシリコ ンスライスで形成され、このシリコンスライスの第1の側に埋め込み絶縁層が形 成され、このシリコンスライスがその第2の側から前記埋め込み層まで除去され ていることを特徴とする半導体装置。 6.請求項5に記載の半導体装置において、前記埋め込み絶縁層が、シリコンと 共に絶縁性材料を構成するイオンのイオン注入によりシリコンスライス中に形成 されていることを特徴とする半導体装置。 7.請求項6に記載の半導体装置において、前記埋め込み絶縁層が、窒素又は酸 素のイオン注入によりシリコンスライス中に形成されていることを特徴とする 半導体装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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NL94203386.1 | 1994-11-22 | ||
EP94203386 | 1994-11-22 | ||
PCT/IB1995/000879 WO1996016443A1 (en) | 1994-11-22 | 1995-10-16 | Semiconductor device with a carrier body on which a substrate with a semiconductor element is fastened by means of a glue layer and on which a pattern of conductor tracks is fastened |
Publications (2)
Publication Number | Publication Date |
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JPH09508502A true JPH09508502A (ja) | 1997-08-26 |
JP4319251B2 JP4319251B2 (ja) | 2009-08-26 |
Family
ID=8217398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP51669796A Expired - Lifetime JP4319251B2 (ja) | 1994-11-22 | 1995-10-16 | 半導体素子を有し導体トラックが形成されている基板が接着層により結合されている支持本体を有する半導体装置 |
Country Status (6)
Country | Link |
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US (1) | US5739591A (ja) |
EP (1) | EP0740853B1 (ja) |
JP (1) | JP4319251B2 (ja) |
KR (1) | KR100389754B1 (ja) |
DE (1) | DE69507284T2 (ja) |
WO (1) | WO1996016443A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003503854A (ja) * | 1999-06-29 | 2003-01-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体デバイス |
US8349707B2 (en) | 2001-08-24 | 2013-01-08 | Wafer-Level Packaging Portfolio Llc | Process for making contact with and housing integrated circuits |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100513412B1 (ko) * | 1996-03-12 | 2005-12-06 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 지지체에접착된기판을구비하는반도체장치 |
JPH11261010A (ja) | 1998-03-13 | 1999-09-24 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
WO2000065655A1 (en) | 1999-04-23 | 2000-11-02 | Koninklijke Philips Electronics N.V. | A semiconductor device with an operating frequency larger than 50mhz comprising a body composed of a soft ferrite material |
US6580107B2 (en) * | 2000-10-10 | 2003-06-17 | Sanyo Electric Co., Ltd. | Compound semiconductor device with depletion layer stop region |
JP2005503671A (ja) * | 2001-09-18 | 2005-02-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | X線を用いて半導体材料のウェハを検査する方法 |
DE10356885B4 (de) | 2003-12-03 | 2005-11-03 | Schott Ag | Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement |
ATE550019T1 (de) | 2005-05-17 | 2012-04-15 | Merck Sharp & Dohme | Cis-4-ä(4-chlorophenyl)sulfonylü-4-(2,5- difluorophenyl)cyclohexanepropansäure zur behandlug von krebs |
GB0603041D0 (en) | 2006-02-15 | 2006-03-29 | Angeletti P Ist Richerche Bio | Therapeutic compounds |
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JPS63308386A (ja) * | 1987-01-30 | 1988-12-15 | Sony Corp | 半導体装置とその製造方法 |
JPH01215033A (ja) * | 1988-02-24 | 1989-08-29 | Fuji Electric Co Ltd | 半導体チップ用ボンディングパッド |
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1995
- 1995-10-16 KR KR1019960703919A patent/KR100389754B1/ko not_active IP Right Cessation
- 1995-10-16 EP EP95932885A patent/EP0740853B1/en not_active Expired - Lifetime
- 1995-10-16 JP JP51669796A patent/JP4319251B2/ja not_active Expired - Lifetime
- 1995-10-16 DE DE69507284T patent/DE69507284T2/de not_active Expired - Lifetime
- 1995-10-16 WO PCT/IB1995/000879 patent/WO1996016443A1/en active IP Right Grant
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003503854A (ja) * | 1999-06-29 | 2003-01-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体デバイス |
US8349707B2 (en) | 2001-08-24 | 2013-01-08 | Wafer-Level Packaging Portfolio Llc | Process for making contact with and housing integrated circuits |
Also Published As
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DE69507284T2 (de) | 1999-07-01 |
US5739591A (en) | 1998-04-14 |
EP0740853A1 (en) | 1996-11-06 |
EP0740853B1 (en) | 1999-01-13 |
KR970700942A (ko) | 1997-02-12 |
KR100389754B1 (ko) | 2003-10-17 |
DE69507284D1 (de) | 1999-02-25 |
JP4319251B2 (ja) | 2009-08-26 |
WO1996016443A1 (en) | 1996-05-30 |
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