KR970700942A - 반도체 장치(semiconductor device with a carrier body on which a substrate with a semiconductor element is fastened by means of a gluelayer and on which a pattern of conductor tracks is fastened) - Google Patents
반도체 장치(semiconductor device with a carrier body on which a substrate with a semiconductor element is fastened by means of a gluelayer and on which a pattern of conductor tracks is fastened)Info
- Publication number
- KR970700942A KR970700942A KR1019960703919A KR19960703919A KR970700942A KR 970700942 A KR970700942 A KR 970700942A KR 1019960703919 A KR1019960703919 A KR 1019960703919A KR 19960703919 A KR19960703919 A KR 19960703919A KR 970700942 A KR970700942 A KR 970700942A
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- substrate
- silicon
- semiconductor device
- carrier body
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Abstract
본 발명은 기재(3)가 접착층(2)에 의해 고정되어 있고, 캐리어 본체(carrier body)(1)와 대향하고 있는 그의 제1측(4)에 반도체 소자를 구비하고 있으며, 또한 상기 캐리어 본체(1)로부터 멀리 떨어져 대향하고 있는 기재의 제2측(8)으로부터 외부 접촉시키기 위한 접촉 전극 또는 결합 패드(7)를 가진 도체 트랙(conductor tracks)(6)의 패턴을 구비하고 있는 캐리어 본체(1)를 가진 반도체 장치(semiconductor device)를 개시한다.
외부 접촉을 위한 접촉 전극(7)을 가진 도체 트랙(6)의 패턴은 접촉 전극(7)의 영역에 제2측(8)으로부터 외부 접촉시키기 위한 윈도우(9)를 구비한 기재(3)의 제1측(4)에 제공된다.
기재(3)를 캐리어 본체(1)에 고정시키는 접착공정 이전의 공정 단계는 반도체 소자의 제조에 적합한 청정실내에서 수행하지만, 나머지 공정 단계는 바람직하게는 최종 실장을 위해 청정실 외측에 설치된 보다 하급의 청정실내에서 수행한다. 본 발명에서는 간단한 접촉 마스크를 이용하여 비교적 큰 윈도우(9)를 형성시킬 수 있기 때문에, 상기 2개의 청정실에 이용되는 고가의 사진석판 장비를 사용하지 않고서도 상기 공정을 수행할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도3은 본 발명에 따른 반도체 장치의 제3실시태양의 개략 단면도.
Claims (7)
- 결합 패드(bond pad)의 영역에 제2측으로부터 외부 접촉시키기 위한 윈도우를 구비한 기재의 제1측상에 외부 접촉을 위한 접촉 전극(contact electrode)을 가진 도체 트랙(conductor track)의 패턴을 구비하고 있음을 특징으로 하는, 접착층에 의해 기재가 고정되고, 캐리어 본체와 대향하고 있는 그의 제1측에 반도체 소자를 구비하고 있으며, 또한 상기 캐리어 본체로부터 멀리 떨어져 대향하고 있는 기재의 제2측으로부터 외부 접촉시키기 위한 접촉 전극(또는 결합 패드)를 포함하는 도체 트랙의 패턴을 구비하고 있는 캐리어 본체를 가진 반도체 장치.
- 제1항에 있어서, 상기 기재가 절연 물질의 층으로 이루어지고, 상기 반도체 소자가 상기 기재의 제1측상에 존재하는 실리콘층내에 형성되어 있음을 특징으로 하는 반도체 장치.
- 제2항에 있어서, 상기 실리콘층이 반도체 소자가 존재하는 아일랜드(island) 근처에서 이산화실리콘으로 전환되고, 상기 접촉 전극이 상기 아일랜드 근처에서 이산화실리콘상에 형성되어 있음을 특징으로 하는 반도체 장치.
- 제2항에 있어서, 상기 실리콘층이 아일랜드의 형태로 상기 기재상에 국부적으로 존재하고, 상기 접촉 전극이 상기 실리콘 아일랜드 근처에서 기재상에 직접 형성되어 있음을 특징으로 하는 반도체 장치.
- 제2항, 제3항 또는 제4항에 있어서, 상기 반도체 기재가 그의 제1측에 매립된 절연층을 구비하고 있는 실리콘 슬라이스로부터 형성되고, 상기 슬라이스의 상기 매립된 절연층 아래의 제2측으로부터 실리콘을 제거함으로써 형성된 것임을 특징으로 하는 반도체 장치.
- 제5항에 있어서, 상기 매립된 절연층이 실리콘과 절연 물질을 형성하는 이온을 주입시킴으로써 실리콘 슬라이스내에 형성된 것임을 특징으로 하는 반도체 장치.
- 제6항에 있어서, 상기 매립된 절연층이 질소 또는 산소 이온을 주입시킴으로써 실리콘 슬라이스내에 형성된 것임을 특징으로 하는 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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EP94203386 | 1994-11-22 | ||
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US (1) | US5739591A (ko) |
EP (1) | EP0740853B1 (ko) |
JP (1) | JP4319251B2 (ko) |
KR (1) | KR100389754B1 (ko) |
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-
1995
- 1995-10-16 KR KR1019960703919A patent/KR100389754B1/ko not_active IP Right Cessation
- 1995-10-16 EP EP95932885A patent/EP0740853B1/en not_active Expired - Lifetime
- 1995-10-16 JP JP51669796A patent/JP4319251B2/ja not_active Expired - Lifetime
- 1995-10-16 DE DE69507284T patent/DE69507284T2/de not_active Expired - Lifetime
- 1995-10-16 WO PCT/IB1995/000879 patent/WO1996016443A1/en active IP Right Grant
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1997
- 1997-07-08 US US08/889,716 patent/US5739591A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69507284T2 (de) | 1999-07-01 |
US5739591A (en) | 1998-04-14 |
EP0740853A1 (en) | 1996-11-06 |
EP0740853B1 (en) | 1999-01-13 |
KR100389754B1 (ko) | 2003-10-17 |
JPH09508502A (ja) | 1997-08-26 |
DE69507284D1 (de) | 1999-02-25 |
JP4319251B2 (ja) | 2009-08-26 |
WO1996016443A1 (en) | 1996-05-30 |
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