KR950034534A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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KR950034534A
KR950034534A KR1019950012817A KR19950012817A KR950034534A KR 950034534 A KR950034534 A KR 950034534A KR 1019950012817 A KR1019950012817 A KR 1019950012817A KR 19950012817 A KR19950012817 A KR 19950012817A KR 950034534 A KR950034534 A KR 950034534A
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semiconductor
slice
semiconductor device
conductive
layer
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KR1019950012817A
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KR100348233B1 (ko
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데커 로날드
고데프리더스 라파엘 마스 헨리쿠스
테오도러스 안토니우스 요하네스 반 덴 아인덴 빌헬르무스
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프레데릭 얀 스미트
필립스 일렉트로닉스 엔. 브이.
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Publication of KR100348233B1 publication Critical patent/KR100348233B1/ko

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Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 절연층(3)상에 배치된 반도체재료층(4)이 마련되어 있는 반도체 슬라이스(1)의 제1면(2)상에 반도체소자(5)와 전도체트랙(14)이 형성된다. 그 후 상기 제1면(2)에 의해 반도체 슬라이스(1)가 가지는 슬라이스(15)에 고정되고, 그후 절연층(3)이 노출될 때까지 제2면(17)로부터 반도체 슬라이스(1)에서 재료가 제거되는 반도체장치의 제조방법에 관한 것이다. 절연층(3)에는 전도성소자(19)가 형성된 접촉윈도우(18)가 마련된다.
이것은 반도체 슬라이스(1)가 지지 슬라이스(15)에 고정되기 전에, 반도체 슬라이스(1)의 제1면(2)으로 부터 실행된다. 반도체소자(5)는 전도성소자(19)를 거쳐 접촉와이어(20)에 외부적으로 접촉된다. 반도체소자를 제조하기 위해 실행되는 프로세서 단계시, 접촉윈도우(18)과 전도성소자(19)가 형성된다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도~제6도는 본 발명에 따른 방법에 의한 여러가지 제조공정에 있어서의 반도체장치의 일부분을 모식적으로 도시한 단면도.

Claims (5)

  1. 절연층상에 놓인 반도체재료층이 마련되어 있는 반도체 슬라이스의 제1면상에 반도체소자와 전도체트랙이 형성되고, 그후 이 제1면에 의해 상기 반도체 슬라이스가 지지 슬라이스에 고정되고, 그후 절연층이 노출될때 까지 제2면으로 부터 반도체 슬라이스에서 재료가 제거되는 반도체장치의 제조방법으로서, 이 방법이 실행되는 동안에, 반도체소자에 접촉되고 전도성소자가 마련된 접촉윈도우가 절연층에 마련되는 방법에 있어서, 상기 전도체소자가 지지 슬라이스에 고정되기 전에 접촉윈도우가 상기 절연층에 마련되고 상기 전도성소자가 반도체 슬라이스의 제1면으로부터 접촉윈도우에 마련되는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 절연층에 접촉윈도우를 형성한 후, 전도층이 반도체 슬라이스의 제1면상에 퇴적되고, 계속해서 여기에 전도체트랙 및 전도성소자가 형성되는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제2항에 있어서, 전도성재료층이 전도성 베이스층상에 퇴적되고, 그후 상기 전도체트랙 및 전도성소자가 전도층 및 베이스층에 형성되는 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제2항에 있어서, 상기 전도층을 퇴적하기 전에 접촉윈도우의 바닥에 2보조층이 마련되는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제3항 또는 제4항에 있어서, 상기 절연층이 노출된 후, 상기 접촉윈도우 내부의 전도층도 노출되는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950012817A 1994-05-24 1995-05-23 반도체장치의제조방법 KR100348233B1 (ko)

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BE9400527A BE1008384A3 (nl) 1994-05-24 1994-05-24 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met halfgeleiderelementen gevormd in een op een dragerplak aangebrachte laag halfgeleidermateriaal.
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EP0684643A1 (en) 1995-11-29
JP2987081B2 (ja) 1999-12-06
JPH07321298A (ja) 1995-12-08
US5504036A (en) 1996-04-02
BE1008384A3 (nl) 1996-04-02
CN1115118A (zh) 1996-01-17
DE69505048D1 (de) 1998-11-05
CN1061783C (zh) 2001-02-07
KR100348233B1 (ko) 2002-11-02
EP0684643B1 (en) 1998-09-30
DE69505048T2 (de) 1999-05-12

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