CN1115118A - 制造具有设置在支撑薄片上的半导体材料层中形成的半导体元件的半导体器件的方法 - Google Patents

制造具有设置在支撑薄片上的半导体材料层中形成的半导体元件的半导体器件的方法 Download PDF

Info

Publication number
CN1115118A
CN1115118A CN95108567A CN95108567A CN1115118A CN 1115118 A CN1115118 A CN 1115118A CN 95108567 A CN95108567 A CN 95108567A CN 95108567 A CN95108567 A CN 95108567A CN 1115118 A CN1115118 A CN 1115118A
Authority
CN
China
Prior art keywords
layer
semiconductor
wafer
insulating barrier
contact window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN95108567A
Other languages
English (en)
Other versions
CN1061783C (zh
Inventor
R·德克尔
H·G·R·马斯
W·T·A·J·艾因邓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of CN1115118A publication Critical patent/CN1115118A/zh
Application granted granted Critical
Publication of CN1061783C publication Critical patent/CN1061783C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges

Abstract

一种制造半导体装置的方法包括：在绝缘(3)上施加一层半导体材料层(4)构成的半导体薄片(1)的第一面(2)上形成半导体元件(5)和导体线路(14)。然后把第一面(2)粘结在一个支撑片(15)上，之后把材料从半导体薄片(1)的另一面除去直到露出绝缘层(3)。在绝缘层(3)上形成接触窗口(18)，窗口中设置有导电元件(19)。这是在第一面(2)粘结在支撑片(15)之前完成的。接触窗口(18)和导电元件(19)在制造半导体元件(5)的工艺步骤中形成。

Description

制造具有设置在支撑薄片上的 半导体材料层中形成的半导体 元件的半导体器件的方法
本发明涉及一种制造半导体器件的方法，其包括，在一个由一个绝缘层上施加了一层半导体材料构成的半导体薄片的第一面上形成半导体元件和导体线路，在此之后把该半导体薄片的第一面粘结在一个支撑片上，然后把材料从半导体薄片的另一面，第二面上除去，直到露出绝缘层，在这一方法中，绝缘层上设有接触窗口，该窗口中形成有与半导体元件连接的导电元件。
支撑片可以用常用的方法例如用锯切的方法分割成独立的部分，以便形成包括一个或多个半导体元件的独立的半导体器件。在前一种情况下，获得分离的半导体器件，而后一种情况获得集成半导体器件。半导体元件可以是，例如，双极晶体管或场效应晶体管。
由于在半导体元件形成后，不必使半导体薄片加热到大约200℃以上，因此对粘结到支撑片上的半导体薄片和支撑片本身并不需要承受极端的要求。半导体薄片可以利用例如环氧树脂或丙烯酸酯胶一类的合成树脂胶粘结在一个由例如铜一类的金属构成的导电支撑片上，或是粘结在由例如玻璃或氧化铝一类的绝缘体构成的绝缘支撑片上。支撑片的膨胀系数可以与半导体薄片材料的不同。但膨胀的差别在后续处理工序中应是不大的，并能够被胶层缓解。
半导体材料层-例如由硅构成的-可以是单晶的，但也可以是多晶或非晶的。绝缘层-例如由氧化硅构成的-可以用沉积的方法制备，但也可以用一些其它方法制备。例如可以通过将氧离子注入到硅片中获得氧化硅层。
其上可制备半导体材料的绝缘层，在使绝缘层暴露出来的整体减薄(bulk-reducing)处理过程中，用作使整体减薄自动停止层；在蚀刻处理工序中用作蚀刻停止层，或是在抛光处理中作为抛光停止层。绝缘层本身并不被除去，并在以后为半导体元件绝缘。绝缘层上开有接触窗口，窗口中设有与半导体元件相连接的导电元件。半导体元件可以通过这些导电元件与外部连接。
JP-A-1/18248专利的英文文摘中公开了一种在开头一段中提到的那种方法，其包括在绝缘层上设有接触窗口，并且接触窗口中的导电元件是用整体减薄处理使绝缘层暴露出来之后才提供的。
按照通常的方法，在绝缘层上设置一层光致抗蚀剂掩膜，以便在绝缘层上形成接触窗口。因此要在被暴露出来的绝缘层上涂一层光致抗蚀剂然后用照相法形成光致抗蚀剂掩膜。已知方法的缺点在于，它不能在这个光刻工艺中使用设置在半导体薄片的第一面上的对准标记，该对准标记是在这一面上形成半导体元件和导体线路过程中提供的。在接触窗口中形成导电元件时也需要设置一个光致抗蚀剂掩膜，对此也不能使用所述对准标记。
此外为了设置接触窗口和导电元件，需要使用另外的不是用来在半导体薄片上形成半导体元件和导体线路的设备。其上粘结着半导体元件，导体线路和绝缘层的支撑片具有，例如，不同于半导体薄片的厚度。
本发明的目的是提供一种方法，其能够在半导体薄片的第一面上利用相同的光刻设备和相同的对准标记，它们被用来在半导体薄片的第一面上形成半导体元件和导体线路，也被用来在绝缘层上形成接触窗口和形成导电元件。
开始一段所述的方法就是为了这一目的，其特征在于，在半导体薄片粘结于支撑片之前，从半导体薄片的第一面为绝缘层设置窗口和在接触窗口中形成导电元件。
同一个半导体薄片在其相同的第一面上形成半导体元件和导体线路的加工也用于在绝缘层上形成接触窗口和用于形成导电元件。对此能够利用同样的光刻设备和同样的对准标记。本发明是基于这样的认识：在半导体薄片粘结于支撑片之前形成于接触窗口中的导电元件将在暴露绝缘层的整体减薄处理过程中暴露出来。这样暴露出来的导电元件将为半导体元件提供对外连接的可能。
实际上，把半导体薄片粘结到支撑片上之前的所有工序步骤都可以在一个与进行其余工序步骤的空间不同的空间中进行。前面的工序必须在一个洁净室中完成，而其余的工序可以在洁净室外面的对无粉尘颗粒要求不那么严格的空间中完成。由于这样的空间比一个洁净室便宜得多，因此本发明的方法可以在较低的成本下进行。
如果在绝缘层中形成接触窗口之后，在半导体薄片的第一面上沉积一个用来形成导体线路和导电元件的导电层，那么导体线路和导电元件可以用单独一个光刻工序形成。
较好的是，把导电层沉积在一个导电基层之上，然后在导电层和基层中都形成导体路线和导电元件。可以选择适当的基层和导电层的材料，使得在暴露绝缘层的加工中导电层受到基层的充分保护，除此之外还能使导体线路具有相对较低的电阻。如果使用的由硅构成的半导体薄片，具有一个氧化硅的绝缘层，在绝缘层上设有一半导体材料的硅层，然后在暴露绝缘层的工艺去掉硅。当到达氧化硅绝缘层时，这种整体减薄处理就会停止。这种处理可以用通常的方法进行，例如在一个盛有KOH的蚀刻槽中高度选择性地进行。在这种情况下，导电层能够被钛，钨或钛-钨合金的基层有效地保护。例如在基层上提供一层铝或铝合金，能够形成电阻大大低于在钛，钨或钛-钨合金层中形成的导体线路的电阻的导体线路。
也可以在沉积导电层之前给接触窗口的底部设置一个辅助层。在暴露绝缘层的工艺中，辅助层可以保护导电层。在使用与上述相同的半导体薄片时，辅助层可以由钛，钨或钛-钨合金构成。但作为选择，此时的辅助层也可以由非导电材料构成。在这里给出的例子中可以使用，例如，氮化硅，在盛有KOH的槽中蚀刻工艺中，氮化硅有效地起到腐蚀停止层的作用。但是在整体减薄处理过程中或之后，导电层需要在接触窗口中暴露出来。
不仅仅是在辅助层是由一种绝缘材料构成时暴露出导电层，而最好是在辅助层是由一种导电材料构成时，和导电层是形成于导电基层之上的这种情况下，导电层被暴露出来。在所有这些情况下，都可以由诸如铝或铝合金一类的材料制造出导电层，在其上可以利用通常的键合技术提供一个导电布线，用于对外连接。
下面通过举例方式并参考附图对本发明进行更为详细的说明。
图1至6以图解方式，按照若干制造阶段，显示了用本发明的方法制造一个半导体装置的部分截面图；
图7至10以图解方式显示了采用本发明的优选实施例的几个制造阶段中的一个半导体装置的部分截面图。
图1至6以图解方式显示了采用本发明的方法的几个制造阶段中的一个半导体装置的部分截面图。用一个大约700μm厚的半导体薄片1开始制造，其具有一个置于一个绝缘层3之上的半导体材料层4的第一面2。在本例中，使用了单晶硅的半导体薄片1，其中用氧离子注入法形成了一个大约0.4μm厚的氧化硅层3。在氧化硅层3上有一层大约0.1μm厚的，由单晶硅构成的半导体材料层4。但这对本发明并不重要。半导体层可以选择多晶或非晶半导体材料层，它可以是非硅半导体材料。绝缘层也可以由非氧化硅材料制造。
用通常的方法在第一面2上形成半导体元件。它们可以是各种各样的元件，例如场效应晶体管和双极晶体管。在本例中为了清楚起见，显示了一个场效应晶体管形式的单一元件的构造。为此目的，用通常的方法对硅层4进行P-型掺杂，接下来将其分割为相互隔离的岛状物5，在本例中，岛状物5之间的硅层4被从绝缘层3上腐蚀掉。这些岛状物中的每一个形成一个场效应晶体管。为此目的，给硅层4提供一个栅介质层6，然后对硅层4进行通常的热氧化。然后，沉积一层多晶硅7，其中形成了一个栅电极8。以栅电极8作为掩膜，随后通过n-型掺杂剂的注入生成源极9和漏极10。最后将这样形成的晶体管用绝缘氧化硅层11覆盖。
在氧化硅层11中形成接触窗口12，随后以常用的方法在半导体薄片1的第一面2上的导电层13中形成导体线路14。
在导体线路14形成之后，把半导体薄片1的第一面2粘结在一个支撑片15上。在本例中，用丙烯酸酯胶层16把半导体薄片1粘结在一个大约1.5mm厚的玻璃支撑片15上。在导体线路14形成后，半导体薄片1并不需要加热到大约200℃以上，这就是为什么把半导体片1粘结于支撑片15的工艺和支撑片15本身并不需要经受极端的要求之原因。半导体薄片1可以用例如环氧树脂胶或如本例中的丙烯酸酯胶一类的合成树脂胶粘结于支撑片15。在本例中支撑片15是由玻璃构成的，但选择例如由铜构成的金属支撑片，或是选择其它替代的绝缘物，例如-氧化铝-也是可以的。一般地讲，允许支撑片的膨胀系数与半导体薄片材料的不一样。但在后续的加工工序中膨胀的差应当很小，并能被胶层缓解。
在把半导体薄片1粘结于支撑片15后，把材料从半导体薄片的另一面，即第二面17上除去，直到暴露出绝缘层3。为此目的，首先将第二面17进行通常的化学-机械抛光处理，直到离氧化硅绝缘层3不到几μm为止，在此基础上，使层3在一个盛有KOH的腐蚀槽中暴露出来。当到达层3时腐蚀处理自动停止，这一层起到腐蚀停止层的作用。
氧化硅绝缘层3设置有接触窗口18，窗口18中设置有连接于半导体元件的导电元件19，在附图中导电元件连接于晶体管的源极9。根据本发明，接触窗口18和导电元件19是在半导体薄片1粘结于支撑片15之前从半导体薄片1的第一面2上形成的。在本例中，绝缘氧化硅层3中的接触窗口18是在形成氧化硅层11中的接触窗口12的同一个光刻工艺步骤中形成的。因此，用于形成接触窗口12的同一个对准标记(未示出)也可以用于形成接触窗口18。在本例中，导体线路14和导电元件19是在同一个导电层13中形成的。因此，导体线路14和导电元件19可以用通常的方法在同一个光刻工艺步骤中完成。用于形成接触窗口12和18的对准标记也可以用于此目的。
在绝缘氧化硅层3从半导体薄片1的第二面17暴露出来之后，形成于接触窗口18中的导电元件也被暴露出来。因此半导体元件-在本例中是场效应晶体管-就可以利用暴露出来的导电元件19进行连接。在本例中，连接是通过利用常用的键合技术提供的接触布线20完成的。也可以选择用电镀的方法在露出的导电元件18上形成对外接触。
为形成这样的对外接触布线20，支撑片被用通常的方法分割成单独的部分，例如用锯切法，这样就形成了独立的半导体器件。这些独立的半导体器件每个可以包括一个或多个半导体元件。前者获得分立半导体器件，后者获得集成半导体器件。
把半导体薄片1粘结到支撑片15上之前的所有工艺步骤都可以在一个与进行其余工艺步骤的空间的不同空间中完成。前面的工艺步骤在一个洁净空间中完成，而其它各工艺步骤可以在对无粉尘颗粒要求不那么严格的室中进行。结果是本发明的方法可以在较低的花费下进行。
图7显示了本发明方法的一个优选实施例的一个加工阶段，其中在导电基层21上沉积了导电层13，此后导体线路14，14A和导电元件19，19A被形成于导电层13(14和19)和基层(14A和19A)中。基层21和导电导13的材料可以进行选择，使得在暴露绝缘层3的工艺中，基层21能够适当地保护导电层13，除此之外使导体线路14具有较低的电阻。在本例中选择钛，钨或钛-钨合金作为基层21的材料。在盛有KOH的腐蚀槽中使氧化硅绝缘层3暴露出来。在这个腐蚀槽中导电层13受到基层21的有效保护。选择铝或铝合金为导电层13的材料。结果是导体线路14具有大大低于在钛，钨或钛-钨合金层中形成的导体电路的电阻。
图8显示了本发明方法的一个优选的实施例中的一个加工阶段，其中在沉积导电层13前在接触窗口18的底部22上提供一个辅助层23。其制作方法是：在绝缘层11上和接触窗口12和18中沉积一个辅助层24，随后用光致抗蚀剂掩膜(未示出)覆盖辅助层，光致抗蚀剂掩膜覆盖在窗口18和环绕这个窗口的边缘15上。接着进行腐蚀处理，除去辅助层的未被覆盖的部分。结果辅助层23存留在接触窗口18的底部22上。在底部22被辅助层23覆盖之后，沉积层电层13，随后在其中形成导体线路14和导电元件19。
在暴露绝缘层3的过程中，导电层13受到辅助层23的保护。在图8所示的例子中，辅助层23的材料和导电层13的材料应能有效地防止槽中KOH的腐蚀，导电层13的材料应能使制成的导体线路14具有低的电阻和与半导体元件有良好的接触。在本例中，辅助层23可以由钛，钨或钛-钨合金构成，导电层13可以由铝或铝合金构成。在这里的辅助层的厚度在大约10nm，为导电元件19提供了一个适当的保护。
图9显示了本方法的一种优选实施例，其中辅助层26是由一种非导电材料构成的，例如在本例中是一种大约20nm厚的氮化硅层，它在含KOH的腐蚀槽中的腐蚀过程中是一个十分有效的腐蚀停止层。在暴露绝缘层3的过程中或在其后，如图10中所示，接触窗口18中的导电元件19也被暴露出来。这一步可以用一种简单的方法完成，在这种方法中，在KOH腐蚀槽中暴露出氧化硅绝缘层3后，于常用的CF4-O4等离子体中进行蚀刻处理。
当辅助层23如图8所示实施例那样是由一种导电材料构成时，或是如图7所示实施例那样导电元件19是形成于一种导电基层19A上时，可以选择不同的有利方法暴露导电元件19。在这些方法中都可以由例如铝或铝合金一类的材料制造出导电层13，可以利用通常的键合技术在其上提供一种用于外连接的导电布线20。

Claims (5)

1.一种制造半导体器件的方法包括：在一个由一个绝缘层中施加了一层半导体材料构成的半导体薄片的第一面上形成半导体元件和导体线路，在此之后把该半导体薄片的第一面粘结在一个支撑片上，然后把材料从半导体薄片的另一面，即第二面上除去，直到露出绝缘层，在这一方法中绝缘层上形成有接触窗口，该接触窗口中设置有与半导体元件连接的导电元件，其特征在于，在绝缘层中形成接触窗口和在接触窗口中形成导电元件都是从半导体薄片的第一面进行的，而且是在将半导体薄片的第一面粘结于支撑片之前进行的。
2.一种如权利要求1所述的方法，其特征在于，在绝缘层中形成接触窗口之后，半导体薄片的第一面上沉积一导电层，随后导体线路和导电元件都形成于这一导电层中。
3.一种如权利要求2所述的方法，其特征在于，在一个导电基层上沉积一导电材料层，其后在导电层和基层中都形成导体线路和导电元件。
4.一种如权利要求2所述的方法，其特征在于，在沉积导电层之前接触窗口12在它们的底部上形成一个辅助层。
5.一种如权利要求3或4所述的方法，其特征在于，绝缘层被暴露出来后，接触窗口内的导电层也被露出。
CN95108567A 1994-05-24 1995-05-24 制造半导体器件的方法 Expired - Lifetime CN1061783C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE9400527A BE1008384A3 (nl) 1994-05-24 1994-05-24 Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met halfgeleiderelementen gevormd in een op een dragerplak aangebrachte laag halfgeleidermateriaal.
BE09400527 1994-05-24

Publications (2)

Publication Number Publication Date
CN1115118A true CN1115118A (zh) 1996-01-17
CN1061783C CN1061783C (zh) 2001-02-07

Family

ID=3888174

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95108567A Expired - Lifetime CN1061783C (zh) 1994-05-24 1995-05-24 制造半导体器件的方法

Country Status (8)

Country Link
US (1) US5504036A (zh)
EP (1) EP0684643B1 (zh)
JP (1) JP2987081B2 (zh)
KR (1) KR100348233B1 (zh)
CN (1) CN1061783C (zh)
BE (1) BE1008384A3 (zh)
DE (1) DE69505048T2 (zh)
TW (1) TW288193B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328602A (zh) * 2015-06-30 2017-01-11 台湾积体电路制造股份有限公司 封装件结构

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
JP4060882B2 (ja) * 1995-05-10 2008-03-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子装置の製造方法
AU714520B2 (en) * 1996-01-31 2000-01-06 Cochlear Limited Thin film fabrication technique for implantable electrodes
US5698474A (en) * 1996-02-26 1997-12-16 Hypervision, Inc. High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection
JP2839007B2 (ja) * 1996-04-18 1998-12-16 日本電気株式会社 半導体装置及びその製造方法
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
EP1503406A3 (en) * 1996-10-29 2009-07-08 Tru-Si Technologies, Inc. Back-side contact pads of a semiconductor chip
KR100377033B1 (ko) 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ｉｃ 및 그 제조방법
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US5897371A (en) * 1996-12-19 1999-04-27 Cypress Semiconductor Corp. Alignment process compatible with chemical mechanical polishing
EP1148546A1 (de) * 2000-04-19 2001-10-24 Infineon Technologies AG Verfahren zur Justierung von Strukturen auf einem Halbleiter-substrat
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
JP3788268B2 (ja) * 2001-05-14 2006-06-21 ソニー株式会社 半導体装置の製造方法
TW487958B (en) * 2001-06-07 2002-05-21 Ind Tech Res Inst Manufacturing method of thin film transistor panel
US7831151B2 (en) 2001-06-29 2010-11-09 John Trezza Redundant optical device array
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP4110390B2 (ja) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
US8294172B2 (en) 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
US20030189215A1 (en) 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
US6841802B2 (en) * 2002-06-26 2005-01-11 Oriol, Inc. Thin film light emitting diode
JP2005150686A (ja) 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
CN101002130A (zh) * 2004-08-09 2007-07-18 皇家飞利浦电子股份有限公司 用于将至少两种预定量的流体和/或气体结合在一起的方法
CN100555633C (zh) * 2004-10-05 2009-10-28 Nxp股份有限公司 半导体器件
JP2009500820A (ja) * 2005-06-29 2009-01-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ アセンブリを製造する方法及びアセンブリ
JP2008078486A (ja) * 2006-09-22 2008-04-03 Oki Electric Ind Co Ltd 半導体素子
GB2492532B (en) * 2011-06-27 2015-06-03 Pragmatic Printing Ltd Transistor and its method of manufacture
GB2492442B (en) * 2011-06-27 2015-11-04 Pragmatic Printing Ltd Transistor and its method of manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532003A (en) * 1982-08-09 1985-07-30 Harris Corporation Method of fabrication bipolar transistor with improved base collector breakdown voltage and collector series resistance
US4596069A (en) * 1984-07-13 1986-06-24 Texas Instruments Incorporated Three dimensional processing for monolithic IMPATTs
JPS6418248A (en) * 1987-07-13 1989-01-23 Nec Corp Manufacture of semiconductor device
US5081061A (en) * 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers
US5347154A (en) * 1990-11-15 1994-09-13 Seiko Instruments Inc. Light valve device using semiconductive composite substrate
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328602A (zh) * 2015-06-30 2017-01-11 台湾积体电路制造股份有限公司 封装件结构
CN106328602B (zh) * 2015-06-30 2019-07-19 台湾积体电路制造股份有限公司 封装件结构

Also Published As

Publication number Publication date
TW288193B (zh) 1996-10-11
EP0684643A1 (en) 1995-11-29
JP2987081B2 (ja) 1999-12-06
JPH07321298A (ja) 1995-12-08
US5504036A (en) 1996-04-02
BE1008384A3 (nl) 1996-04-02
DE69505048D1 (de) 1998-11-05
CN1061783C (zh) 2001-02-07
KR950034534A (ko) 1995-12-28
KR100348233B1 (ko) 2002-11-02
EP0684643B1 (en) 1998-09-30
DE69505048T2 (de) 1999-05-12

Similar Documents

Publication Publication Date Title
CN1061783C (zh) 制造半导体器件的方法
TWI224371B (en) Semiconductor device
US5366589A (en) Bonding pad with circular exposed area and method thereof
EP0039174B1 (en) Gold metallisation in semiconductor devices
US6835999B2 (en) Semiconductor device and method of manufacturing the same
EP0453787B1 (en) Semiconductor device having an insulating film
CN1689152A (zh) 适用于形成集成电路互连和器件的金属－金属氧化物蚀刻阻滞/电子迁移屏蔽的方法
JPH0883888A (ja) 集積回路チップ、集積回路チップの形成方法、電子モジュール、および電子モジュールの形成方法
JPH0821559B2 (ja) 半導体集積回路装置の製造方法
JPH05291343A (ja) 半導体装置
CN101640179B (zh) 焊垫结构的制作方法
JPH03120821A (ja) 集積回路デバイスの製造方法
JP2723559B2 (ja) 半導体集積回路装置
KR0179558B1 (ko) 반도체 소자의 본딩 패드 형성방법
JPH0332214B2 (zh)
JPH06310597A (ja) 半導体装置
JPS60145628A (ja) 半導体装置
US6864582B1 (en) Semiconductor interconnect and method of providing interconnect using a contact region
KR100207285B1 (ko) 반도체 소자의 본딩패드 형성방법
KR100220243B1 (ko) 반도체 소자의 본딩 패드 형성방법
KR100299332B1 (ko) 반도체 소자의 층간 절연막 제조 방법
KR100929424B1 (ko) 반도체 소자의 패드 형성방법
KR100187724B1 (ko) 고 방열 구조를 갖는 반도체 칩
US20060063365A1 (en) Aluminum cap for reducing scratch and wire-bond bridging of bond pads
KR0161854B1 (ko) 반도체 소자의 보호막 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: ROYAL PHILIPS ELECTRONICS CO., LTD.

Effective date: 20090710

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090710

Address after: Holland Ian Deho Finn

Patentee after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Patentee before: Koninklike Philips Electronics N. V.

ASS Succession or assignment of patent right

Owner name: YINGWEN SASI CO., LTD.

Free format text: FORMER OWNER: KONINKL PHILIPS ELECTRONICS NV

Effective date: 20120502

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20120502

Address after: American California

Patentee after: Tessera Inc.

Address before: Holland Ian Deho Finn

Patentee before: Koninkl Philips Electronics NV

C17 Cessation of patent right
CX01 Expiry of patent term

Expiration termination date: 20150524

Granted publication date: 20010207