JPH09507612A - 三次元回路装置の製造方法 - Google Patents
三次元回路装置の製造方法Info
- Publication number
- JPH09507612A JPH09507612A JP7518769A JP51876995A JPH09507612A JP H09507612 A JPH09507612 A JP H09507612A JP 7518769 A JP7518769 A JP 7518769A JP 51876995 A JP51876995 A JP 51876995A JP H09507612 A JPH09507612 A JP H09507612A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- metallization
- adhesive layer
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.第1の主面(11)の領域内に少なくとも1個の第1の回路パターン(12 )、第1の金属化面(13)及びこの第1の金属化面(13)を覆っている第1 のパッシベーンョン層(14)を含んでいる第1の基板(1)が、第1の主面( 11)上に施されている第1の接着層(17)を介して補助基板(18)と接続 され、 第1の基板(1)が第1の主面(11)に対向している第2の主面で薄層化さ れ、 第3の主面(21)の領域内に少なくとも第2の回路パターン(22)、第2 の金属化面(23)及びこの第2の金属化面(23)を覆っている第2のパッシ ベーション層(24)を含んでいる第2の基板(2)が、、第3の主面(21) 上に第2の接着層(26)を有しており、 第1の基板(1)の第2の主面が第2の基板(2)上の第2の接着層(24) と境を接しており、第1の基板(1)と第2の基板(2)とが第2の接着層(2 6)を介して固く結合されるように第1の基板(1)と第2の基板(2)とが接 合されており、 第1の主面(11)から第1の金属化層(13)上に第1の接触孔(16)が 開けられ、 補助基板(18)及び第1の接着層(17)の除去後第1の主面(11)から 出発して少なくとも1つの第2の接触孔(4)が第2の金属化面(23)に達す るまで開けられ、 第1の主面(11)上に第1の金属化面(13)と第2の金属化面(23)を 電気的に互いに接続する導電層(7)が形成される ことを特徴とする三次元回路装置の製造方法。 2.導電層(7)を形成する前に少なくとも第2の接触孔(4)の側壁に側面絶 縁部分(5)が形成されることを特徴とする請求項1記載の方法。 3.第1の基板(1)及び第2の基板(2)にそれぞれ整合マークが備えられて おり、それらを介して第1の基板(1)と第2の基板(2)の接合の際に赤外線 透過で整合が行われることを特徴とする請求項1又は2記載の方法。 4.第1の基板(1)の薄層化が薄層研磨及び/又は薄層エッチングにより行わ れることを特徴とする請求項1ないし3の1つに記載の方法。 5.少なくとも第1の基板(1)が単結晶シリコン層、埋込まれたSiO2層及 びシリコンウェハを含んでいるSOI基板であり、、第1の基板(1)の薄層化 の際にシリコンウェハが除去され、第1の回路パターン(12)がSOI基板の 単結晶シリコン層内に形成されていることを特徴とする請求項4記載の方法。 6.導電層(7)上に全面的にもう1つのパッシベーション層を施すことを特徴 とする請求項1ないし5の1つに記載の方法。 7.第1の金属化面(13)の下方にある第1の基板(1)内及び/又は第2の 金属化面(23)の下方にある第2の基板(2)内に別の金属化面(15、25 )を配設することを特徴とする請求項1ないし6の1つに記載の方法。 8.第1の接着層(17)をポリイミド又はポリアクリレートから形成し、O2 プラズマ又は湿式化学法により除去することを特徴とする請求項1ないし7の1 つに記載の方法。 9.第2の接着層(26)をポリイミドから形成し、この接着層(26)を第1 の基板(1)と第2の基板(2)を接合させた後に重合により硬化させることを 特徴とする請求項1ないし8の1つに記載の方法。 10.第2の接触孔(4)を少なくともHNO3/HFでの等方性エッチング及 びHBrプラズマ中での異方性エッチングを含む複合エッチングで開口すること を特徴とする請求項1ないし9の1つに記載の方法。 11.第2の接触孔(4)をCHF3及びHBrプラズマ中での異方性エッチン グにより開口することを特徴とする請求項1ないし9の1つに記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4400985.2 | 1994-01-14 | ||
DE4400985A DE4400985C1 (de) | 1994-01-14 | 1994-01-14 | Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung |
PCT/DE1995/000031 WO1995019642A1 (de) | 1994-01-14 | 1995-01-12 | Verfahren zur herstellung einer dreidimensionalen schaltungsanordnung |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09507612A true JPH09507612A (ja) | 1997-07-29 |
JP3904228B2 JP3904228B2 (ja) | 2007-04-11 |
Family
ID=6507953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51876995A Expired - Fee Related JP3904228B2 (ja) | 1994-01-14 | 1995-01-12 | 三次元回路装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5741733A (ja) |
EP (1) | EP0739540B1 (ja) |
JP (1) | JP3904228B2 (ja) |
KR (1) | KR100347656B1 (ja) |
DE (2) | DE4400985C1 (ja) |
WO (1) | WO1995019642A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100663549B1 (ko) * | 2005-12-21 | 2007-01-02 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
JP2009135350A (ja) * | 2007-12-03 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2011192712A (ja) * | 2010-03-12 | 2011-09-29 | Renesas Electronics Corp | 半導体装置の製造方法 |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4442652A1 (de) * | 1994-11-30 | 1996-01-25 | Siemens Ag | Verfahren zur Herstellung eines Kontaktloches auf eine Metallisierungsebene einer dreidimensionalen Schaltungsanordnung |
DE19543540C1 (de) * | 1995-11-22 | 1996-11-21 | Siemens Ag | Vertikal integriertes Halbleiterbauelement mit zwei miteinander verbundenen Substraten und Herstellungsverfahren dafür |
KR100228719B1 (ko) * | 1996-05-27 | 1999-11-01 | 윤덕용 | 전기 화학적 식각방법을 이용하는 soi형 반도체 소자 및 이를 이용한 능동구동 액정표시장치의 제조방법 |
US5897333A (en) * | 1997-03-14 | 1999-04-27 | Lucent Technologies, Inc. | Method for forming integrated composite semiconductor devices |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US6030860A (en) * | 1997-12-19 | 2000-02-29 | Advanced Micro Devices, Inc. | Elevated substrate formation and local interconnect integrated fabrication |
US6500694B1 (en) * | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6984571B1 (en) | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6291858B1 (en) * | 2000-01-03 | 2001-09-18 | International Business Machines Corporation | Multistack 3-dimensional high density semiconductor device and method for fabrication |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US6743697B2 (en) * | 2000-06-30 | 2004-06-01 | Intel Corporation | Thin silicon circuits and method for making the same |
US6563133B1 (en) * | 2000-08-09 | 2003-05-13 | Ziptronix, Inc. | Method of epitaxial-like wafer bonding at low temperature and bonded structure |
US6759282B2 (en) * | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US7608927B2 (en) * | 2002-08-29 | 2009-10-27 | Micron Technology, Inc. | Localized biasing for silicon on insulator structures |
FR2848336B1 (fr) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
KR101003541B1 (ko) | 2008-10-14 | 2010-12-30 | 이상윤 | 3차원 반도체 장치의 제조 방법 |
DE10303643B3 (de) * | 2003-01-30 | 2004-09-09 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung von Substratkontakten bei SOI-Schaltungsstrukturen |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
FR2856844B1 (fr) * | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
US6821826B1 (en) * | 2003-09-30 | 2004-11-23 | International Business Machines Corporation | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers |
FR2861497B1 (fr) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
FR2889887B1 (fr) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
KR100755368B1 (ko) * | 2006-01-10 | 2007-09-04 | 삼성전자주식회사 | 3차원 구조를 갖는 반도체 소자의 제조 방법들 및 그에의해 제조된 반도체 소자들 |
FR2910179B1 (fr) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
DE102007046493A1 (de) | 2007-09-28 | 2009-04-09 | Continental Automotive Gmbh | Dreidimensionaler elektronischer Schaltungsträgeraufbau, sowie Schaltungsgrundträger aufweisend den Schaltungsträgeraufbau als Funktionsbauteil und dreidimensionale Schaltungsanordnung bestehend aus zumindest zwei derartigen dreidimensionalen Schaltungsträgeraufbauten |
FR2922359B1 (fr) * | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire |
DE102008033395B3 (de) * | 2008-07-16 | 2010-02-04 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelementes und Halbleiterbauelement |
DE102009005458B4 (de) * | 2009-01-21 | 2010-09-30 | Austriamicrosystems Ag | Halbleiterbauelement mit Durchkontaktierung und Verfahren zu dessen Herstellung |
FR2947098A1 (fr) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
DE102009049102B4 (de) | 2009-10-13 | 2012-10-04 | Austriamicrosystems Ag | Halbleiterbauelement mit Durchkontaktierung und Verfahren zur Herstellung einer Durchkontaktierung in einem Halbleiterbauelement |
DE102010045055B4 (de) | 2010-09-10 | 2019-03-28 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Durchkontaktierung |
EP2884542A3 (en) * | 2013-12-10 | 2015-09-02 | IMEC vzw | Integrated circuit device with power gating switch in back end of line |
FR3030881A1 (fr) * | 2014-12-22 | 2016-06-24 | Commissariat Energie Atomique | Procede de realisation d'un circuit integre en trois dimensions |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59155951A (ja) * | 1983-02-25 | 1984-09-05 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0612799B2 (ja) * | 1986-03-03 | 1994-02-16 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
KR900008647B1 (ko) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | 3차원 집적회로와 그의 제조방법 |
JPH0793259B2 (ja) * | 1987-01-14 | 1995-10-09 | 工業技術院長 | 半導体薄膜結晶層の製造方法 |
JPH063837B2 (ja) * | 1987-03-03 | 1994-01-12 | シャープ株式会社 | 三次元半導体集積回路の製造方法 |
JPH01253228A (ja) * | 1988-03-31 | 1989-10-09 | Sharp Corp | 半導体装置の製造方法 |
DE4314907C1 (de) * | 1993-05-05 | 1994-08-25 | Siemens Ag | Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen |
-
1994
- 1994-01-14 DE DE4400985A patent/DE4400985C1/de not_active Expired - Fee Related
-
1995
- 1995-01-12 WO PCT/DE1995/000031 patent/WO1995019642A1/de active IP Right Grant
- 1995-01-12 DE DE59508426T patent/DE59508426D1/de not_active Expired - Fee Related
- 1995-01-12 KR KR1019960703751A patent/KR100347656B1/ko not_active IP Right Cessation
- 1995-01-12 JP JP51876995A patent/JP3904228B2/ja not_active Expired - Fee Related
- 1995-01-12 US US08/676,164 patent/US5741733A/en not_active Expired - Lifetime
- 1995-01-12 EP EP95905535A patent/EP0739540B1/de not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100663549B1 (ko) * | 2005-12-21 | 2007-01-02 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
JP2009135350A (ja) * | 2007-12-03 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2011192712A (ja) * | 2010-03-12 | 2011-09-29 | Renesas Electronics Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE59508426D1 (de) | 2000-07-06 |
DE4400985C1 (de) | 1995-05-11 |
KR100347656B1 (ko) | 2002-11-29 |
US5741733A (en) | 1998-04-21 |
WO1995019642A1 (de) | 1995-07-20 |
JP3904228B2 (ja) | 2007-04-11 |
EP0739540A1 (de) | 1996-10-30 |
EP0739540B1 (de) | 2000-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3904228B2 (ja) | 三次元回路装置の製造方法 | |
JP3999828B2 (ja) | マイクロエレクトロニックシステムを垂直方向で集積する方法 | |
US20200035641A1 (en) | Post cmp processing for hybrid bonding | |
US5766984A (en) | Method of making a vertical integrated circuit | |
US6831367B2 (en) | Semiconductor device and method of manufacturing the same | |
US6448174B1 (en) | Wiring method for producing a vertical, integrated circuit structure and vertical, integrated circuit structure | |
TWI388050B (zh) | 半導體裝置的製造方法、半導體裝置以及晶圓 | |
US7645701B2 (en) | Silicon-on-insulator structures for through via in silicon carriers | |
KR100294747B1 (ko) | 수직접속된반도체부품을형성하기위한방법 | |
TWI514442B (zh) | 單一光罩通道之方法與裝置 | |
US6930382B2 (en) | Semiconductor device and method of manufacturing the same | |
KR100510112B1 (ko) | 다적층 3차원 고밀도 반도체 디바이스 및 그 제조 방법 | |
JPH09106968A (ja) | 集積回路チップのエッジを正確に画定する方法 | |
JPH08204123A (ja) | 3次元集積回路の製造方法 | |
TWI750009B (zh) | 具有矽穿孔插塞的半導體元件及其製備方法 | |
JPH08213548A (ja) | 3次元集積回路の製造方法 | |
JPH04298037A (ja) | 集積化されたシリコン非シリコン半導体装置の製造方法 | |
EP1195808B1 (en) | Method of fabricating a thin, free-standing semiconductor device layer and of making a three-dimensionally integrated circuit | |
US20220336373A1 (en) | Scribe structure for memory device | |
JP2002110948A (ja) | 半導体装置の製造方法 | |
CN115799159A (zh) | 隔离器件的形成方法 | |
CN116998004A (zh) | 半导体装置的制造方法、半导体装置、集成电路元件及集成电路元件的制造方法 | |
JP2001244333A (ja) | 半導体集積回路装置の製造方法 | |
JPH07249634A (ja) | ゲッタリング方法およびそれを用いた半導体集積回路装置 | |
JPH06120419A (ja) | 積層型半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051115 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20060214 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20060403 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060512 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060627 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060922 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20061207 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20061214 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070109 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100119 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110119 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120119 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130119 Year of fee payment: 6 |
|
LAPS | Cancellation because of no payment of annual fees |