JPH0437149A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0437149A
JPH0437149A JP2141684A JP14168490A JPH0437149A JP H0437149 A JPH0437149 A JP H0437149A JP 2141684 A JP2141684 A JP 2141684A JP 14168490 A JP14168490 A JP 14168490A JP H0437149 A JPH0437149 A JP H0437149A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrode
lead frame
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2141684A
Other languages
English (en)
Other versions
JP2540652B2 (ja
Inventor
Takao Fujizu
隆夫 藤津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2141684A priority Critical patent/JP2540652B2/ja
Priority to KR1019910009041A priority patent/KR970000972B1/ko
Priority to DE69133497T priority patent/DE69133497T2/de
Priority to EP00103351A priority patent/EP1020903B1/en
Priority to EP91108886A priority patent/EP0459493B1/en
Priority to DE69132685T priority patent/DE69132685T2/de
Publication of JPH0437149A publication Critical patent/JPH0437149A/ja
Priority to US08/344,605 priority patent/US5654584A/en
Priority to US08/461,448 priority patent/US5556810A/en
Application granted granted Critical
Publication of JP2540652B2 publication Critical patent/JP2540652B2/ja
Priority to KR1019960058149A priority patent/KR970005714B1/ko
Priority to KR1019960058150A priority patent/KR970005715B1/ko
Priority to KR1019960058151A priority patent/KR970005716B1/ko
Priority to KR96058153A priority patent/KR970005718B1/ko
Priority to KR1019960058152A priority patent/KR970005717B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は半導体チップ上の電極とインナーリードとの
間の電気的接続、アウターリードと印刷配線基板上の配
線パターンとの電気的接続が図られた半導体装置及びそ
の製造方法に係り、特に電気的接続を図る配線間隔が微
小な半導体装置及びその製造方法に関する。
（従来の技術） 半導体装置を製造する際、半導体チップ上の電極パッド
とインナーリードとの間、アウターリードと印刷配線基
板上の配線パターンとの間、等のように相互に電気的接
続を図る箇所が多数存在する。従来、例えば半導体チッ
プ上の電極パッドとインナーリードとの間の電気的接続
は、通常、ワイヤボンディングによるＡｕワイヤもしく
はＡ１ワイヤを用いた金属接合、ＴＡＢテープ（Ｔａｐ
ｅ　Ａｕｔｏｍａｔｅｄ　Ｂｏｎｄｉｎｇ）による金属
接合、フリップチップ等のバンブ電極とリードとの間の
金属間接合によるオーミックコンタクト等によって行わ
れる。
（発明が解決しようとする課題） ところで、ワイヤボンディングによる接続は、使用する
ボンディング用キャビラリイ　（針）の外形により、隣
接するワイヤ間の最短距離が制約され、半導体チップ上
のパッド間距離を約１００μｍ程度以下に縮小すること
は難しい。また、ＡｕボールやＡＩワイヤと半導体チッ
プ上のアルミニウム・パッドとの金属接続のため、加熱
、加圧、超音波振動等の物理的負荷を加える必要があり
、時としては電極パッド下の半導体チップそのものにダ
メージを与えることがある。
一方、ＴＡＢテープを使用する場合やフリップチップを
使用する場合は、Ａｕバンブ、半田バンブとインナーリ
ードとの金属接続であり、ワイヤボンディング接続より
も高温になることがあるため、加圧力による物理的ダメ
ージが残ることかある。この場合、パッド間隔は８０μ
ｍ程度まで縮小できるが、金属接合を行うため、バンブ
サイズの縮小には限界がある。しかも、多数箇所の接続
を一括して行うため、バンブ高さ、接続条件等、接続箇
所が多数になる程、接続の安定性を得るため難しく、プ
ロセス条件を安定化させる必要がある。
また、上記のような問題は、半導体チップ上のバットや
バンブとインナーリードとの間の電気的接続のみではな
く、アウターリードと印刷配線基板上の配線パターンと
の間の電気的接続の場合等にも起こり得る。
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、相互に電気的接続を図る箇所の間隔
を従来よりも縮小することができ、かつ電気的接続を図
る際に加熱、加圧等の物理的ダメージを与えないで高い
信頼性を有する半導体装置を提供することにある。
［発明の構成］ （課題を解決するための手段） この発明の半導体装置は、導電性材料からなるリードフ
レームと、表面に電極が形成された半導体チップと、上
記リードフレームの所定位置と上記半導体チップの電極
とを電気的に接続する金属メッキによる接続部とを具備
している。
この発明の半導体装置は、絶縁フィルムと、上記絶縁フ
ィルム上に形成された配線パターンと、表面に電極が形
成された半導体チップと、上記配線パターンの端面と上
記半導体チップの電極とを電気的に接続する金属メッキ
による接続部とを具備している。
また、この発明の半導体装置は、半導体チップが接続さ
れたリードフレームと、表面に配線パターンが形成され
た配線基板と、上記リードフレームと上記配線基板の配
線パターンとを電気的に接続する金属メッキによる接続
部とを具備している。
さらにこの発明の半導体装置は、導電性材料からなるリ
ードフレームと、表面に電極が形成された半導体チップ
と、上記リードフレームの所定位置と上記半導体チップ
の電極とを電気的に接続する導電性の接着剤からなる第
１の接続部と、上記第１の接続部の周囲を覆うように設
けられ上記リードフレームと上記半導体チップの電極と
を電気的に接続する金属メッキによる第２の接続部とを
具備している。
この発明の半導体装置の製造方法は、導電性材料からな
るリードフレームの所定位置と半導体チップの表面に形
成された電極とを近接させた状態で該リードフレームに
半導体チップを貼着する工程と、両者を電界メッキ溶液
中に浸して上記リードフレームの所定位置と上記半導体
チップの電極とを電気的に接続する金属メッキ層を形成
する工程とを具備している。
（作　用） 相互に電気的に接続する必要があるリードフレームと半
導体チップの電極、又はリードフレームと配線基板の配
線パターンとの間を接続、金属メッキもしくは導電性の
接着剤と金属メッキとの併用によって行うことにより、
各接続間に十分なオーミツクンタクトが形成できるとと
もに十分な機械的強度を持たせることができる。しかも
、複数箇所を一括して接続することができ、接続時に加
熱や加圧は不要である。
（実施例） 以下、図面を参照してこの発明を実施例により説明する
。
第１図はこの発明を半導体チップ上の電極パッドとイン
ナーリードとの間の接続に実施した半導体装置の一部構
成を示す断面図であり、第２図はそのほぼ全体の構成を
示す断面図である。
図において、１１はトランジスタ等の能動素子や、抵抗
、容量等の受動素子が形成されている半導体チップであ
る。この半導体チップ１１の主面上の全周囲には、それ
ぞれ下層が例えばアルミニウム（ＡＩ）からなる金属層
１２によって形成され、上層が少なくとも一層のニッケ
ル層を含む金属層１３で構成された複数の電極パッド１
４が一定の間隔で一列に配列されている。そして、上記
各電極パッド１４の形成位置以外では、半導体チップ１
１はシリコン酸化膜等の絶縁性の表面保護膜１５で覆わ
れている。さらに、上記半導体チップ１１はエポキシ系
の接着剤１６によってＴＡＢテープ１７の所定箇所に貼
着されている。
上記ＴＡＢテープ１７は、第１図に示すように、エポキ
シやポリイミド系等の樹脂からなり膜厚が例えば７５μ
ｍ程度の有機フィルム基材１８に、膜厚が例えば３５μ
ｍ程度の銅（Ｃｕ）等の導体層をラミネートし、その後
、選択エツチング技術によって上記複数の電極パッド１
４と接続すべき複数のインナーリード１９及びこれら各
インナーリード１９と接続された図示しないアウターリ
ードとを備えた配線パターンを形成することによって構
成されている。そして、この配線パターンの形成面が上
記接着剤１６によって半導体チップ１１に貼着されてい
る。
また、上記ＴＡＢテープ１７に半導体チップ１１を貼着
する際は、上記複数のインナーリード１９の先端部の各
端面が露出している付近に上記各電極パラド１４が位置
するような状態で位置合わせが行われる。そして、半導
体チップｌｌ上の各電極パッド１４とインナーリード１
９の各先端部とは、例えばニッケル（Ｎｉ）からなる金
属メッキ層２０を介して電気的に接続されている。
第３図は上記各電極パッド１４の詳細な構成を示す断面
図である。アルミニウム（Ａ１）からなる金属層１２上
に形成されている金属層１３は少なくとも２層の金属層
で構成されている。すなわち、アルミニウムからなる金
属層１２と接触する下層は例えば膜厚が１０００人のチ
タン（Ｔｉ）層３工からなり、上層は例えば膜厚が３０
００人のニッケル（Ｎｉ）層３２からなっている。ここ
で上層のニッケル層３２は、電極パッド１４に対してニ
ッケルからなる金属メッキ層２０の形成を可能にするた
めに設けられているものであり、下層のチタン層３１は
バリアメタルの役割を持つ。
第４図は上記複数の電極パッド１４と、ＴＡＢテープ１
７に形成された複数のインナーリード１９との接続状態
を示す平面図であり、図中、斜線を施した領域が金属メ
ッキ層２０を示している。
上記実施例によれば、半導体チップ１１上の各電極パッ
ド１４とインナーリード１７とを金属メッキ層２０を用
いて接続するようにしているので、ワイヤボンディング
、ＴＡＢ接続等に使用されるボンディング用キャビラリ
イ、ＴＡＢツール治具の使用が不要になる。このため、
各電極パッド１４相互の間隔は１００μｍ以下の例えば
５０μｍ程度にまで縮小することができる。また、各電
極パッド１４と各インナーリード１７とを電気的に接続
する際には物理的な加圧力が半導体チップ１１に加わら
ないので、この加圧力のダメージによる信頼性の低下は
なくなる。そして、多数の接続箇所を一括してかつ同一
条件で行うことができるため、接続の信頼性が向上する
。さらに、接続時に加熱する必要がないので、半導体チ
ップ１１を構成する各層の熱膨張係数のミスマツチから
くる熱応力による信頼性低下も防止することができる。
ところで、上記電極パッドとインナーリードとを電気的
に接続する金属メッキ層の形成は次のようにして行われ
る。すなわち、第５図のＴＡＢテープで示すように、前
記有機フィルム基材１８に銅等の導体層をラミネートし
た後、選択エツチング技術により、前記インナーリード
及びこのインナーリードと接続されたアウターリードと
からなる複数のリード電極４１を各半導体装置毎に形成
する。
このとき同時に、各半導体装置毎に複数のリード電極４
１全体を接続する共通電極４２を周囲に形成すると共に
これら全ての共通電極４２も共通に接続しておく。なお
、第５図において、４３は上記有機フィルム基材１８に
形成された開孔部である。第６図は上記第５図のＴＡＢ
テープにおける１つの半導体装置の部分を拡大して示す
平面図である。第６図中、−点鎖線で示した領域に半導
体チップ１１か位置するように位置合わせした状態でＴ
ＡＢテープに貼着される。このとき、前記したように、
複数のインナーリードの先端部の各端面が露出している
付近に半導体チップ上の各電極パッドが位置することに
なる。
この後、ＴＡＢテープをメッキ用電極と共にニッケル中
メッキ浴に浸す。このニッケル・メッキ浴としては、一
般にワット浴と称され、硫酸ニッケル、塩化ニッケル及
び添加剤等からなるものがある。上記の両者をこのワッ
ト浴に浸した後、前記共通電極４２が正極性、メッキ用
電極が負極性となるように両者間に所定の直流電圧を印
加し、電界メッキを所定時間行う。例えば、印加する直
流電圧を２Ｖ、両者間に流す電流を６０　ｍ　Ａ　ｓメ
ッキ時間を１０分間としたところ、前記金属メッキ層２
０として１０μｍの膜厚のニッケル・メッキ層が得られ
た。このニッケル・メッキ層は始めはインナーリードの
先端部の各端面から成長する。これがチップ上の電極パ
ッドに接触すると、この後は電極パッド上にもメッキ層
が成長し、最終的には両者がメッキ層によって電気的に
接続されることになる。メッキ終了後は純水で洗浄され
、メッキ時に表面に付着した汚染物質が除去される。
なお、予めインナーリード及びアウターリードからなる
各リード電極４１の、インナーリードの先端部を除いた
大部分の表面を例えばグリーンコートと称されるエポキ
シ系の絶縁被膜を被着させておくことにより、必要部分
にのみメッキ層を形成することができ、メッキ時間の短
縮を図ることができる。
次に上記実施例の種々の変形例を説明する。上記実施例
では半導体チップの主面上に電極パッドが一定の間隔で
一列に配列されている場合について説明したが、第７図
の変形例装置では、この発明を半導体チップ上の電極パ
ッド１４が千鳥状に配列されたものに実施したものであ
る。なお、前記第４図と対応する箇所には同じ符号を付
してその説明は省略する。また、第８図の変形例装置で
は、この発明を半導体チップ上の電極パッドがチップ上
の全面にランダムに配置された、いわゆるフリー・アク
セス・パッド・レイアウト方式のものに実施したもので
ある。このようにこの発明は、チップ上の電極パッドの
配置状態にかかわらず、どのような方式のものにも実施
することができる。
次にこの発明の他の実施例を説明する。
第９図はこの発明をリードフレームのアウターリードと
印刷配線基板上の配線パターンとの間の接続に実施した
半導体装置の構成を示す断面図である。図において、１
１は半導体チップ、１７はＴＡＢテープである。この実
施例装置の場合、ＴＡＢテープのインナーリードの先端
部と半導体チップ１１上の電極パッドとは、上記実施例
の場合と同様に金属メッキ層２０によって電気的に接続
されている。さらにこの実施例装置では、印刷配線基板
５１上に形成されている配線パターン５２と、ＴＡＢテ
ープのアウターリードとの間も金属メッキ層２０によっ
て電気的に接続されている。
第１０図はこの発明をリードフレームのアウターリード
と印刷配線基板上の配線パターンとの間の接続に実施し
た半導体装置の構成を示す断面図である。この実施例の
場合、リードフレームは例えば４−２アロイと称される
合金や銅等からなる金属薄膜をプレスにより打ち抜き加
工して得られたものであり、このリードフレームのイン
ナーリード５３と、半導体チップｌｌ上の電極パッド１
４とは、導電性の接着剤５４と金属メッキ層５５とを併
用して電気的に接続されている。ＴＡＢテープを使用す
る前記実施例の場合には、ＴＡＢテープ上に半導体チッ
プを接着剤により予め固定した上で金属メッキ層を形成
することができる。しかし、金属薄膜を打ち抜き加工し
たリードフレームを使用する場合にも、各電極パッド１
４上にスクリーン印刷の手法により予め接着剤５４を形
成しておき、これらの接着剤によってリードフレームと
接着した後、前記と同様の方法によりメッキ層を形成す
ることによって両者を電気的に接続することができる。
このようにこの発明はリードフレームのインナーリード
と半導体チップ上の電極パッドとの接続のみではなく、
アウターリードと印刷配線基板上の配線パターンとの間
の接続にも実施することができ、それぞれ同様の効果を
得ることができる。
また、さらには液晶表示装置とＴＡＢテープとの間の電
気的接続等にも実施することができる。
なお、この発明は上記各実施例に限定されるものではな
く、この他にも種々の変形が可能であることはいうまで
もない。例えば上記各実施例では金属メッキ層がニッケ
ル・メッキ層である場合について説明したが、これは他
に金（Ａｕ）メッキ層、銅メッキ層等も使用可能である
。
また、上記実施例では、予めインナーリードの先端部を
除いた大部分の表面に絶縁被膜を被着させておく場合に
ついて説明した。しかし、電界メッキを行うときに、イ
ンナーリードの先端部以外の箇所には先端部の約１／１
０以下の厚みにしがメッキ層が成長しないので、前記絶
縁被膜の被着を省略することもできる。
さらに上記実施例の方法では、上記メッキ層を電界メッ
キ法によって形成する場合について説明したが、これは
無電界メッキ法によって形成することも可能である。
［発明の効果］ 以上説明したようにこの発明によれば、相互に電気的接
続を図る箇所の間隔を従来よりも縮小することができ、
かつ電気的接続を図る際に加熱、加圧等の物理的ダメー
ジを与えないで高い信頼性を有する半導体装置及びその
製造方法を提供することができる。
【図面の簡単な説明】
第１図はこの発明の一実施例装置の一部構成を示す断面
図、第２図は上記実施例装置のほぼ全体の構成を示す断
面図、第３図は上記実施例装置にお、ける電極パッドの
詳細な構成を示す断面図、第４図は上記実施例装置にお
ける複数の電極パッドと複数のインナーリードとの接続
状態を示す平面図、第５図及び第６図はそれぞれＴＡＢ
テープの平面図、第７図及び第８図はそれぞれ上記実施
例の変形例装置の平面図、第９図及び第１０図はそれぞ
れこの発明の他の実施例装置の断面図である。 １１・・・半導体チップ、１２．１３・・・金属層、１
４・・・電極パッド、１５・・・絶縁性の表面保護膜、
１Ｂ・・・エポキシ系の接着剤、１７・・・ＴＡＢテー
プ、１Ｂ・・・有機フィルム基材、１９・・・インナー
リード、２０・・・金属メッキ層。 出願人代理人　弁理士　鈴江武彦 第 図 第 図 第 図 第 図 第 図 第 １゜ 図

Claims (9)

    【特許請求の範囲】
  1. （１）導電性材料からなるリードフレームと、表面に電
    極が形成された半導体チップと、 上記リードフレームの所定位置と上記半導体チップの電
    極とを電気的に接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。
  2. （２）前記リードフレームが絶縁フィルム上に配線パタ
    ーンが形成されたＴＡＢ方式のものである請求項１記載
    の半導体装置。
  3. （３）前記リードフレームが金属薄膜を打ち抜き加工し
    て得られるものである請求項１記載の半導体装置。
  4. （４）前記半導体チップの表面に形成された電極が アルミニウム層と、 上記アルミニウム層上に形成されたチタン層と上記チタ
    ン層上に形成された金層又はニッケル層又は銅層のいず
    れか一つの層とから構成されている請求項１記載の半導
    体装置。
  5. （５）絶縁フィルムと、 上記絶縁フィルム上に形成された配線パターンと、 表面に電極が形成された半導体チップと、 上記配線パターンの端面と上記半導体チップの電極とを
    電気的に接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。
  6. （６）前記半導体チップの表面に形成された電極が アルミニウム層と、 上記アルミニウム層上に形成されたチタン層と、上記チ
    タン層上に形成された金層又はニッケル層又は銅層のい
    ずれか一つの層とから構成されている請求項５記載の半
    導体装置。
  7. （７）半導体チップが接続されたリードフレームと、 表面に配線パターンが形成された配線基板と、上記サー
    ドフレームと上記配線基板の配線パターンとを電気的に
    接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。
  8. （８）導電性材料からなるリードフレームと、表面に電
    極が形成された半導体チップと、 上記リードフレームの所定位置と上記半導体チップの電
    極とを電気的に接続する導電性の接着剤からなる第１の
    接続部と、 上記第１の接続部の周囲を覆うように設けられ上記リー
    ドフレームと上記半導体チップの電極とを電気的に接続
    する金属メッキによる第２の接続部と を具備したことを特徴とする半導体装置。
  9. （９）導電性材料からなるリードフレームの所定位置と
    半導体チップの表面に形成された電極とを近接させた状
    態で該リードフレームに半導体チップを貼着する工程と
    、 両者を電界メッキ溶液中に浸して上記リードフレームの
    所定位置と上記半導体チップの電極とを電気的に接続す
    る金属メッキ層を形成する工程とを具備したことを特徴
    とする半導体装置の製造方法。
JP2141684A 1990-06-01 1990-06-01 半導体装置 Expired - Fee Related JP2540652B2 (ja)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2141684A JP2540652B2 (ja) 1990-06-01 1990-06-01 半導体装置
KR1019910009041A KR970000972B1 (ko) 1990-06-01 1991-05-31 반도체 장치 및 그 제조 방법
DE69133497T DE69133497T2 (de) 1990-06-01 1991-05-31 Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren
EP00103351A EP1020903B1 (en) 1990-06-01 1991-05-31 A semiconductor device using a lead frame and its manufacturing method
EP91108886A EP0459493B1 (en) 1990-06-01 1991-05-31 A semiconductor device comprising a TAB tape and its manufacturing method
DE69132685T DE69132685T2 (de) 1990-06-01 1991-05-31 Halbleiteranordnung bestehend aus einem TAB-Band und deren Herstellungsverfahren
US08/344,605 US5654584A (en) 1990-06-01 1994-11-18 Semiconductor device having tape automated bonding leads
US08/461,448 US5556810A (en) 1990-06-01 1995-06-05 Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
KR1019960058149A KR970005714B1 (ko) 1990-06-01 1996-11-27 반도체 장치 및 그 제조 방법
KR1019960058150A KR970005715B1 (ko) 1990-06-01 1996-11-27 반도체 장치 및 그 제조 방법
KR1019960058151A KR970005716B1 (ko) 1990-06-01 1996-11-27 반도체 장치 및 그 제조 방법
KR96058153A KR970005718B1 (en) 1990-06-01 1996-11-27 A semiconductor device and its menufacture method
KR1019960058152A KR970005717B1 (ko) 1990-06-01 1996-11-27 반도체 장치 및 그 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2141684A JP2540652B2 (ja) 1990-06-01 1990-06-01 半導体装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP8011933A Division JP2777345B2 (ja) 1996-01-26 1996-01-26 半導体装置
JP1193496A Division JP2736247B2 (ja) 1996-01-26 1996-01-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPH0437149A true JPH0437149A (ja) 1992-02-07
JP2540652B2 JP2540652B2 (ja) 1996-10-09

Family

ID=15297809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2141684A Expired - Fee Related JP2540652B2 (ja) 1990-06-01 1990-06-01 半導体装置

Country Status (5)

Country Link
US (1) US5654584A (ja)
EP (2) EP1020903B1 (ja)
JP (1) JP2540652B2 (ja)
KR (1) KR970000972B1 (ja)
DE (2) DE69133497T2 (ja)

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EP0459493B1 (en) 2001-08-16
EP1020903B1 (en) 2005-12-14
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JP2540652B2 (ja) 1996-10-09
KR970000972B1 (ko) 1997-01-21
EP1020903A1 (en) 2000-07-19
DE69132685D1 (de) 2001-09-20
EP0459493A3 (ja) 1994-02-23
US5654584A (en) 1997-08-05

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