JPH0437149A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPH0437149A JPH0437149A JP2141684A JP14168490A JPH0437149A JP H0437149 A JPH0437149 A JP H0437149A JP 2141684 A JP2141684 A JP 2141684A JP 14168490 A JP14168490 A JP 14168490A JP H0437149 A JPH0437149 A JP H0437149A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electrode
- lead frame
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000007747 plating Methods 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000002815 nickel Chemical class 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910021586 Nickel(II) chloride Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- QMMRZOWCJAIUJA-UHFFFAOYSA-L nickel dichloride Chemical compound Cl[Ni]Cl QMMRZOWCJAIUJA-UHFFFAOYSA-L 0.000 description 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
この発明は半導体チップ上の電極とインナーリードとの
間の電気的接続、アウターリードと印刷配線基板上の配
線パターンとの電気的接続が図られた半導体装置及びそ
の製造方法に係り、特に電気的接続を図る配線間隔が微
小な半導体装置及びその製造方法に関する。
間の電気的接続、アウターリードと印刷配線基板上の配
線パターンとの電気的接続が図られた半導体装置及びそ
の製造方法に係り、特に電気的接続を図る配線間隔が微
小な半導体装置及びその製造方法に関する。
(従来の技術)
半導体装置を製造する際、半導体チップ上の電極パッド
とインナーリードとの間、アウターリードと印刷配線基
板上の配線パターンとの間、等のように相互に電気的接
続を図る箇所が多数存在する。従来、例えば半導体チッ
プ上の電極パッドとインナーリードとの間の電気的接続
は、通常、ワイヤボンディングによるAuワイヤもしく
はA1ワイヤを用いた金属接合、TABテープ(Tap
e Automated Bonding)による金属
接合、フリップチップ等のバンブ電極とリードとの間の
金属間接合によるオーミックコンタクト等によって行わ
れる。
とインナーリードとの間、アウターリードと印刷配線基
板上の配線パターンとの間、等のように相互に電気的接
続を図る箇所が多数存在する。従来、例えば半導体チッ
プ上の電極パッドとインナーリードとの間の電気的接続
は、通常、ワイヤボンディングによるAuワイヤもしく
はA1ワイヤを用いた金属接合、TABテープ(Tap
e Automated Bonding)による金属
接合、フリップチップ等のバンブ電極とリードとの間の
金属間接合によるオーミックコンタクト等によって行わ
れる。
(発明が解決しようとする課題)
ところで、ワイヤボンディングによる接続は、使用する
ボンディング用キャビラリイ (針)の外形により、隣
接するワイヤ間の最短距離が制約され、半導体チップ上
のパッド間距離を約100μm程度以下に縮小すること
は難しい。また、AuボールやAIワイヤと半導体チッ
プ上のアルミニウム・パッドとの金属接続のため、加熱
、加圧、超音波振動等の物理的負荷を加える必要があり
、時としては電極パッド下の半導体チップそのものにダ
メージを与えることがある。
ボンディング用キャビラリイ (針)の外形により、隣
接するワイヤ間の最短距離が制約され、半導体チップ上
のパッド間距離を約100μm程度以下に縮小すること
は難しい。また、AuボールやAIワイヤと半導体チッ
プ上のアルミニウム・パッドとの金属接続のため、加熱
、加圧、超音波振動等の物理的負荷を加える必要があり
、時としては電極パッド下の半導体チップそのものにダ
メージを与えることがある。
一方、TABテープを使用する場合やフリップチップを
使用する場合は、Auバンブ、半田バンブとインナーリ
ードとの金属接続であり、ワイヤボンディング接続より
も高温になることがあるため、加圧力による物理的ダメ
ージが残ることかある。この場合、パッド間隔は80μ
m程度まで縮小できるが、金属接合を行うため、バンブ
サイズの縮小には限界がある。しかも、多数箇所の接続
を一括して行うため、バンブ高さ、接続条件等、接続箇
所が多数になる程、接続の安定性を得るため難しく、プ
ロセス条件を安定化させる必要がある。
使用する場合は、Auバンブ、半田バンブとインナーリ
ードとの金属接続であり、ワイヤボンディング接続より
も高温になることがあるため、加圧力による物理的ダメ
ージが残ることかある。この場合、パッド間隔は80μ
m程度まで縮小できるが、金属接合を行うため、バンブ
サイズの縮小には限界がある。しかも、多数箇所の接続
を一括して行うため、バンブ高さ、接続条件等、接続箇
所が多数になる程、接続の安定性を得るため難しく、プ
ロセス条件を安定化させる必要がある。
また、上記のような問題は、半導体チップ上のバットや
バンブとインナーリードとの間の電気的接続のみではな
く、アウターリードと印刷配線基板上の配線パターンと
の間の電気的接続の場合等にも起こり得る。
バンブとインナーリードとの間の電気的接続のみではな
く、アウターリードと印刷配線基板上の配線パターンと
の間の電気的接続の場合等にも起こり得る。
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、相互に電気的接続を図る箇所の間隔
を従来よりも縮小することができ、かつ電気的接続を図
る際に加熱、加圧等の物理的ダメージを与えないで高い
信頼性を有する半導体装置を提供することにある。
あり、その目的は、相互に電気的接続を図る箇所の間隔
を従来よりも縮小することができ、かつ電気的接続を図
る際に加熱、加圧等の物理的ダメージを与えないで高い
信頼性を有する半導体装置を提供することにある。
[発明の構成]
(課題を解決するための手段)
この発明の半導体装置は、導電性材料からなるリードフ
レームと、表面に電極が形成された半導体チップと、上
記リードフレームの所定位置と上記半導体チップの電極
とを電気的に接続する金属メッキによる接続部とを具備
している。
レームと、表面に電極が形成された半導体チップと、上
記リードフレームの所定位置と上記半導体チップの電極
とを電気的に接続する金属メッキによる接続部とを具備
している。
この発明の半導体装置は、絶縁フィルムと、上記絶縁フ
ィルム上に形成された配線パターンと、表面に電極が形
成された半導体チップと、上記配線パターンの端面と上
記半導体チップの電極とを電気的に接続する金属メッキ
による接続部とを具備している。
ィルム上に形成された配線パターンと、表面に電極が形
成された半導体チップと、上記配線パターンの端面と上
記半導体チップの電極とを電気的に接続する金属メッキ
による接続部とを具備している。
また、この発明の半導体装置は、半導体チップが接続さ
れたリードフレームと、表面に配線パターンが形成され
た配線基板と、上記リードフレームと上記配線基板の配
線パターンとを電気的に接続する金属メッキによる接続
部とを具備している。
れたリードフレームと、表面に配線パターンが形成され
た配線基板と、上記リードフレームと上記配線基板の配
線パターンとを電気的に接続する金属メッキによる接続
部とを具備している。
さらにこの発明の半導体装置は、導電性材料からなるリ
ードフレームと、表面に電極が形成された半導体チップ
と、上記リードフレームの所定位置と上記半導体チップ
の電極とを電気的に接続する導電性の接着剤からなる第
1の接続部と、上記第1の接続部の周囲を覆うように設
けられ上記リードフレームと上記半導体チップの電極と
を電気的に接続する金属メッキによる第2の接続部とを
具備している。
ードフレームと、表面に電極が形成された半導体チップ
と、上記リードフレームの所定位置と上記半導体チップ
の電極とを電気的に接続する導電性の接着剤からなる第
1の接続部と、上記第1の接続部の周囲を覆うように設
けられ上記リードフレームと上記半導体チップの電極と
を電気的に接続する金属メッキによる第2の接続部とを
具備している。
この発明の半導体装置の製造方法は、導電性材料からな
るリードフレームの所定位置と半導体チップの表面に形
成された電極とを近接させた状態で該リードフレームに
半導体チップを貼着する工程と、両者を電界メッキ溶液
中に浸して上記リードフレームの所定位置と上記半導体
チップの電極とを電気的に接続する金属メッキ層を形成
する工程とを具備している。
るリードフレームの所定位置と半導体チップの表面に形
成された電極とを近接させた状態で該リードフレームに
半導体チップを貼着する工程と、両者を電界メッキ溶液
中に浸して上記リードフレームの所定位置と上記半導体
チップの電極とを電気的に接続する金属メッキ層を形成
する工程とを具備している。
(作 用)
相互に電気的に接続する必要があるリードフレームと半
導体チップの電極、又はリードフレームと配線基板の配
線パターンとの間を接続、金属メッキもしくは導電性の
接着剤と金属メッキとの併用によって行うことにより、
各接続間に十分なオーミツクンタクトが形成できるとと
もに十分な機械的強度を持たせることができる。しかも
、複数箇所を一括して接続することができ、接続時に加
熱や加圧は不要である。
導体チップの電極、又はリードフレームと配線基板の配
線パターンとの間を接続、金属メッキもしくは導電性の
接着剤と金属メッキとの併用によって行うことにより、
各接続間に十分なオーミツクンタクトが形成できるとと
もに十分な機械的強度を持たせることができる。しかも
、複数箇所を一括して接続することができ、接続時に加
熱や加圧は不要である。
(実施例)
以下、図面を参照してこの発明を実施例により説明する
。
。
第1図はこの発明を半導体チップ上の電極パッドとイン
ナーリードとの間の接続に実施した半導体装置の一部構
成を示す断面図であり、第2図はそのほぼ全体の構成を
示す断面図である。
ナーリードとの間の接続に実施した半導体装置の一部構
成を示す断面図であり、第2図はそのほぼ全体の構成を
示す断面図である。
図において、11はトランジスタ等の能動素子や、抵抗
、容量等の受動素子が形成されている半導体チップであ
る。この半導体チップ11の主面上の全周囲には、それ
ぞれ下層が例えばアルミニウム(AI)からなる金属層
12によって形成され、上層が少なくとも一層のニッケ
ル層を含む金属層13で構成された複数の電極パッド1
4が一定の間隔で一列に配列されている。そして、上記
各電極パッド14の形成位置以外では、半導体チップ1
1はシリコン酸化膜等の絶縁性の表面保護膜15で覆わ
れている。さらに、上記半導体チップ11はエポキシ系
の接着剤16によってTABテープ17の所定箇所に貼
着されている。
、容量等の受動素子が形成されている半導体チップであ
る。この半導体チップ11の主面上の全周囲には、それ
ぞれ下層が例えばアルミニウム(AI)からなる金属層
12によって形成され、上層が少なくとも一層のニッケ
ル層を含む金属層13で構成された複数の電極パッド1
4が一定の間隔で一列に配列されている。そして、上記
各電極パッド14の形成位置以外では、半導体チップ1
1はシリコン酸化膜等の絶縁性の表面保護膜15で覆わ
れている。さらに、上記半導体チップ11はエポキシ系
の接着剤16によってTABテープ17の所定箇所に貼
着されている。
上記TABテープ17は、第1図に示すように、エポキ
シやポリイミド系等の樹脂からなり膜厚が例えば75μ
m程度の有機フィルム基材18に、膜厚が例えば35μ
m程度の銅(Cu)等の導体層をラミネートし、その後
、選択エツチング技術によって上記複数の電極パッド1
4と接続すべき複数のインナーリード19及びこれら各
インナーリード19と接続された図示しないアウターリ
ードとを備えた配線パターンを形成することによって構
成されている。そして、この配線パターンの形成面が上
記接着剤16によって半導体チップ11に貼着されてい
る。
シやポリイミド系等の樹脂からなり膜厚が例えば75μ
m程度の有機フィルム基材18に、膜厚が例えば35μ
m程度の銅(Cu)等の導体層をラミネートし、その後
、選択エツチング技術によって上記複数の電極パッド1
4と接続すべき複数のインナーリード19及びこれら各
インナーリード19と接続された図示しないアウターリ
ードとを備えた配線パターンを形成することによって構
成されている。そして、この配線パターンの形成面が上
記接着剤16によって半導体チップ11に貼着されてい
る。
また、上記TABテープ17に半導体チップ11を貼着
する際は、上記複数のインナーリード19の先端部の各
端面が露出している付近に上記各電極パラド14が位置
するような状態で位置合わせが行われる。そして、半導
体チップll上の各電極パッド14とインナーリード1
9の各先端部とは、例えばニッケル(Ni)からなる金
属メッキ層20を介して電気的に接続されている。
する際は、上記複数のインナーリード19の先端部の各
端面が露出している付近に上記各電極パラド14が位置
するような状態で位置合わせが行われる。そして、半導
体チップll上の各電極パッド14とインナーリード1
9の各先端部とは、例えばニッケル(Ni)からなる金
属メッキ層20を介して電気的に接続されている。
第3図は上記各電極パッド14の詳細な構成を示す断面
図である。アルミニウム(A1)からなる金属層12上
に形成されている金属層13は少なくとも2層の金属層
で構成されている。すなわち、アルミニウムからなる金
属層12と接触する下層は例えば膜厚が1000人のチ
タン(Ti)層3工からなり、上層は例えば膜厚が30
00人のニッケル(Ni)層32からなっている。ここ
で上層のニッケル層32は、電極パッド14に対してニ
ッケルからなる金属メッキ層20の形成を可能にするた
めに設けられているものであり、下層のチタン層31は
バリアメタルの役割を持つ。
図である。アルミニウム(A1)からなる金属層12上
に形成されている金属層13は少なくとも2層の金属層
で構成されている。すなわち、アルミニウムからなる金
属層12と接触する下層は例えば膜厚が1000人のチ
タン(Ti)層3工からなり、上層は例えば膜厚が30
00人のニッケル(Ni)層32からなっている。ここ
で上層のニッケル層32は、電極パッド14に対してニ
ッケルからなる金属メッキ層20の形成を可能にするた
めに設けられているものであり、下層のチタン層31は
バリアメタルの役割を持つ。
第4図は上記複数の電極パッド14と、TABテープ1
7に形成された複数のインナーリード19との接続状態
を示す平面図であり、図中、斜線を施した領域が金属メ
ッキ層20を示している。
7に形成された複数のインナーリード19との接続状態
を示す平面図であり、図中、斜線を施した領域が金属メ
ッキ層20を示している。
上記実施例によれば、半導体チップ11上の各電極パッ
ド14とインナーリード17とを金属メッキ層20を用
いて接続するようにしているので、ワイヤボンディング
、TAB接続等に使用されるボンディング用キャビラリ
イ、TABツール治具の使用が不要になる。このため、
各電極パッド14相互の間隔は100μm以下の例えば
50μm程度にまで縮小することができる。また、各電
極パッド14と各インナーリード17とを電気的に接続
する際には物理的な加圧力が半導体チップ11に加わら
ないので、この加圧力のダメージによる信頼性の低下は
なくなる。そして、多数の接続箇所を一括してかつ同一
条件で行うことができるため、接続の信頼性が向上する
。さらに、接続時に加熱する必要がないので、半導体チ
ップ11を構成する各層の熱膨張係数のミスマツチから
くる熱応力による信頼性低下も防止することができる。
ド14とインナーリード17とを金属メッキ層20を用
いて接続するようにしているので、ワイヤボンディング
、TAB接続等に使用されるボンディング用キャビラリ
イ、TABツール治具の使用が不要になる。このため、
各電極パッド14相互の間隔は100μm以下の例えば
50μm程度にまで縮小することができる。また、各電
極パッド14と各インナーリード17とを電気的に接続
する際には物理的な加圧力が半導体チップ11に加わら
ないので、この加圧力のダメージによる信頼性の低下は
なくなる。そして、多数の接続箇所を一括してかつ同一
条件で行うことができるため、接続の信頼性が向上する
。さらに、接続時に加熱する必要がないので、半導体チ
ップ11を構成する各層の熱膨張係数のミスマツチから
くる熱応力による信頼性低下も防止することができる。
ところで、上記電極パッドとインナーリードとを電気的
に接続する金属メッキ層の形成は次のようにして行われ
る。すなわち、第5図のTABテープで示すように、前
記有機フィルム基材18に銅等の導体層をラミネートし
た後、選択エツチング技術により、前記インナーリード
及びこのインナーリードと接続されたアウターリードと
からなる複数のリード電極41を各半導体装置毎に形成
する。
に接続する金属メッキ層の形成は次のようにして行われ
る。すなわち、第5図のTABテープで示すように、前
記有機フィルム基材18に銅等の導体層をラミネートし
た後、選択エツチング技術により、前記インナーリード
及びこのインナーリードと接続されたアウターリードと
からなる複数のリード電極41を各半導体装置毎に形成
する。
このとき同時に、各半導体装置毎に複数のリード電極4
1全体を接続する共通電極42を周囲に形成すると共に
これら全ての共通電極42も共通に接続しておく。なお
、第5図において、43は上記有機フィルム基材18に
形成された開孔部である。第6図は上記第5図のTAB
テープにおける1つの半導体装置の部分を拡大して示す
平面図である。第6図中、−点鎖線で示した領域に半導
体チップ11か位置するように位置合わせした状態でT
ABテープに貼着される。このとき、前記したように、
複数のインナーリードの先端部の各端面が露出している
付近に半導体チップ上の各電極パッドが位置することに
なる。
1全体を接続する共通電極42を周囲に形成すると共に
これら全ての共通電極42も共通に接続しておく。なお
、第5図において、43は上記有機フィルム基材18に
形成された開孔部である。第6図は上記第5図のTAB
テープにおける1つの半導体装置の部分を拡大して示す
平面図である。第6図中、−点鎖線で示した領域に半導
体チップ11か位置するように位置合わせした状態でT
ABテープに貼着される。このとき、前記したように、
複数のインナーリードの先端部の各端面が露出している
付近に半導体チップ上の各電極パッドが位置することに
なる。
この後、TABテープをメッキ用電極と共にニッケル中
メッキ浴に浸す。このニッケル・メッキ浴としては、一
般にワット浴と称され、硫酸ニッケル、塩化ニッケル及
び添加剤等からなるものがある。上記の両者をこのワッ
ト浴に浸した後、前記共通電極42が正極性、メッキ用
電極が負極性となるように両者間に所定の直流電圧を印
加し、電界メッキを所定時間行う。例えば、印加する直
流電圧を2V、両者間に流す電流を60 m A sメ
ッキ時間を10分間としたところ、前記金属メッキ層2
0として10μmの膜厚のニッケル・メッキ層が得られ
た。このニッケル・メッキ層は始めはインナーリードの
先端部の各端面から成長する。これがチップ上の電極パ
ッドに接触すると、この後は電極パッド上にもメッキ層
が成長し、最終的には両者がメッキ層によって電気的に
接続されることになる。メッキ終了後は純水で洗浄され
、メッキ時に表面に付着した汚染物質が除去される。
メッキ浴に浸す。このニッケル・メッキ浴としては、一
般にワット浴と称され、硫酸ニッケル、塩化ニッケル及
び添加剤等からなるものがある。上記の両者をこのワッ
ト浴に浸した後、前記共通電極42が正極性、メッキ用
電極が負極性となるように両者間に所定の直流電圧を印
加し、電界メッキを所定時間行う。例えば、印加する直
流電圧を2V、両者間に流す電流を60 m A sメ
ッキ時間を10分間としたところ、前記金属メッキ層2
0として10μmの膜厚のニッケル・メッキ層が得られ
た。このニッケル・メッキ層は始めはインナーリードの
先端部の各端面から成長する。これがチップ上の電極パ
ッドに接触すると、この後は電極パッド上にもメッキ層
が成長し、最終的には両者がメッキ層によって電気的に
接続されることになる。メッキ終了後は純水で洗浄され
、メッキ時に表面に付着した汚染物質が除去される。
なお、予めインナーリード及びアウターリードからなる
各リード電極41の、インナーリードの先端部を除いた
大部分の表面を例えばグリーンコートと称されるエポキ
シ系の絶縁被膜を被着させておくことにより、必要部分
にのみメッキ層を形成することができ、メッキ時間の短
縮を図ることができる。
各リード電極41の、インナーリードの先端部を除いた
大部分の表面を例えばグリーンコートと称されるエポキ
シ系の絶縁被膜を被着させておくことにより、必要部分
にのみメッキ層を形成することができ、メッキ時間の短
縮を図ることができる。
次に上記実施例の種々の変形例を説明する。上記実施例
では半導体チップの主面上に電極パッドが一定の間隔で
一列に配列されている場合について説明したが、第7図
の変形例装置では、この発明を半導体チップ上の電極パ
ッド14が千鳥状に配列されたものに実施したものであ
る。なお、前記第4図と対応する箇所には同じ符号を付
してその説明は省略する。また、第8図の変形例装置で
は、この発明を半導体チップ上の電極パッドがチップ上
の全面にランダムに配置された、いわゆるフリー・アク
セス・パッド・レイアウト方式のものに実施したもので
ある。このようにこの発明は、チップ上の電極パッドの
配置状態にかかわらず、どのような方式のものにも実施
することができる。
では半導体チップの主面上に電極パッドが一定の間隔で
一列に配列されている場合について説明したが、第7図
の変形例装置では、この発明を半導体チップ上の電極パ
ッド14が千鳥状に配列されたものに実施したものであ
る。なお、前記第4図と対応する箇所には同じ符号を付
してその説明は省略する。また、第8図の変形例装置で
は、この発明を半導体チップ上の電極パッドがチップ上
の全面にランダムに配置された、いわゆるフリー・アク
セス・パッド・レイアウト方式のものに実施したもので
ある。このようにこの発明は、チップ上の電極パッドの
配置状態にかかわらず、どのような方式のものにも実施
することができる。
次にこの発明の他の実施例を説明する。
第9図はこの発明をリードフレームのアウターリードと
印刷配線基板上の配線パターンとの間の接続に実施した
半導体装置の構成を示す断面図である。図において、1
1は半導体チップ、17はTABテープである。この実
施例装置の場合、TABテープのインナーリードの先端
部と半導体チップ11上の電極パッドとは、上記実施例
の場合と同様に金属メッキ層20によって電気的に接続
されている。さらにこの実施例装置では、印刷配線基板
51上に形成されている配線パターン52と、TABテ
ープのアウターリードとの間も金属メッキ層20によっ
て電気的に接続されている。
印刷配線基板上の配線パターンとの間の接続に実施した
半導体装置の構成を示す断面図である。図において、1
1は半導体チップ、17はTABテープである。この実
施例装置の場合、TABテープのインナーリードの先端
部と半導体チップ11上の電極パッドとは、上記実施例
の場合と同様に金属メッキ層20によって電気的に接続
されている。さらにこの実施例装置では、印刷配線基板
51上に形成されている配線パターン52と、TABテ
ープのアウターリードとの間も金属メッキ層20によっ
て電気的に接続されている。
第10図はこの発明をリードフレームのアウターリード
と印刷配線基板上の配線パターンとの間の接続に実施し
た半導体装置の構成を示す断面図である。この実施例の
場合、リードフレームは例えば4−2アロイと称される
合金や銅等からなる金属薄膜をプレスにより打ち抜き加
工して得られたものであり、このリードフレームのイン
ナーリード53と、半導体チップll上の電極パッド1
4とは、導電性の接着剤54と金属メッキ層55とを併
用して電気的に接続されている。TABテープを使用す
る前記実施例の場合には、TABテープ上に半導体チッ
プを接着剤により予め固定した上で金属メッキ層を形成
することができる。しかし、金属薄膜を打ち抜き加工し
たリードフレームを使用する場合にも、各電極パッド1
4上にスクリーン印刷の手法により予め接着剤54を形
成しておき、これらの接着剤によってリードフレームと
接着した後、前記と同様の方法によりメッキ層を形成す
ることによって両者を電気的に接続することができる。
と印刷配線基板上の配線パターンとの間の接続に実施し
た半導体装置の構成を示す断面図である。この実施例の
場合、リードフレームは例えば4−2アロイと称される
合金や銅等からなる金属薄膜をプレスにより打ち抜き加
工して得られたものであり、このリードフレームのイン
ナーリード53と、半導体チップll上の電極パッド1
4とは、導電性の接着剤54と金属メッキ層55とを併
用して電気的に接続されている。TABテープを使用す
る前記実施例の場合には、TABテープ上に半導体チッ
プを接着剤により予め固定した上で金属メッキ層を形成
することができる。しかし、金属薄膜を打ち抜き加工し
たリードフレームを使用する場合にも、各電極パッド1
4上にスクリーン印刷の手法により予め接着剤54を形
成しておき、これらの接着剤によってリードフレームと
接着した後、前記と同様の方法によりメッキ層を形成す
ることによって両者を電気的に接続することができる。
このようにこの発明はリードフレームのインナーリード
と半導体チップ上の電極パッドとの接続のみではなく、
アウターリードと印刷配線基板上の配線パターンとの間
の接続にも実施することができ、それぞれ同様の効果を
得ることができる。
と半導体チップ上の電極パッドとの接続のみではなく、
アウターリードと印刷配線基板上の配線パターンとの間
の接続にも実施することができ、それぞれ同様の効果を
得ることができる。
また、さらには液晶表示装置とTABテープとの間の電
気的接続等にも実施することができる。
気的接続等にも実施することができる。
なお、この発明は上記各実施例に限定されるものではな
く、この他にも種々の変形が可能であることはいうまで
もない。例えば上記各実施例では金属メッキ層がニッケ
ル・メッキ層である場合について説明したが、これは他
に金(Au)メッキ層、銅メッキ層等も使用可能である
。
く、この他にも種々の変形が可能であることはいうまで
もない。例えば上記各実施例では金属メッキ層がニッケ
ル・メッキ層である場合について説明したが、これは他
に金(Au)メッキ層、銅メッキ層等も使用可能である
。
また、上記実施例では、予めインナーリードの先端部を
除いた大部分の表面に絶縁被膜を被着させておく場合に
ついて説明した。しかし、電界メッキを行うときに、イ
ンナーリードの先端部以外の箇所には先端部の約1/1
0以下の厚みにしがメッキ層が成長しないので、前記絶
縁被膜の被着を省略することもできる。
除いた大部分の表面に絶縁被膜を被着させておく場合に
ついて説明した。しかし、電界メッキを行うときに、イ
ンナーリードの先端部以外の箇所には先端部の約1/1
0以下の厚みにしがメッキ層が成長しないので、前記絶
縁被膜の被着を省略することもできる。
さらに上記実施例の方法では、上記メッキ層を電界メッ
キ法によって形成する場合について説明したが、これは
無電界メッキ法によって形成することも可能である。
キ法によって形成する場合について説明したが、これは
無電界メッキ法によって形成することも可能である。
[発明の効果]
以上説明したようにこの発明によれば、相互に電気的接
続を図る箇所の間隔を従来よりも縮小することができ、
かつ電気的接続を図る際に加熱、加圧等の物理的ダメー
ジを与えないで高い信頼性を有する半導体装置及びその
製造方法を提供することができる。
続を図る箇所の間隔を従来よりも縮小することができ、
かつ電気的接続を図る際に加熱、加圧等の物理的ダメー
ジを与えないで高い信頼性を有する半導体装置及びその
製造方法を提供することができる。
第1図はこの発明の一実施例装置の一部構成を示す断面
図、第2図は上記実施例装置のほぼ全体の構成を示す断
面図、第3図は上記実施例装置にお、ける電極パッドの
詳細な構成を示す断面図、第4図は上記実施例装置にお
ける複数の電極パッドと複数のインナーリードとの接続
状態を示す平面図、第5図及び第6図はそれぞれTAB
テープの平面図、第7図及び第8図はそれぞれ上記実施
例の変形例装置の平面図、第9図及び第10図はそれぞ
れこの発明の他の実施例装置の断面図である。 11・・・半導体チップ、12.13・・・金属層、1
4・・・電極パッド、15・・・絶縁性の表面保護膜、
1B・・・エポキシ系の接着剤、17・・・TABテー
プ、1B・・・有機フィルム基材、19・・・インナー
リード、20・・・金属メッキ層。 出願人代理人 弁理士 鈴江武彦 第 図 第 図 第 図 第 図 第 図 第 1゜ 図
図、第2図は上記実施例装置のほぼ全体の構成を示す断
面図、第3図は上記実施例装置にお、ける電極パッドの
詳細な構成を示す断面図、第4図は上記実施例装置にお
ける複数の電極パッドと複数のインナーリードとの接続
状態を示す平面図、第5図及び第6図はそれぞれTAB
テープの平面図、第7図及び第8図はそれぞれ上記実施
例の変形例装置の平面図、第9図及び第10図はそれぞ
れこの発明の他の実施例装置の断面図である。 11・・・半導体チップ、12.13・・・金属層、1
4・・・電極パッド、15・・・絶縁性の表面保護膜、
1B・・・エポキシ系の接着剤、17・・・TABテー
プ、1B・・・有機フィルム基材、19・・・インナー
リード、20・・・金属メッキ層。 出願人代理人 弁理士 鈴江武彦 第 図 第 図 第 図 第 図 第 図 第 1゜ 図
Claims (9)
- (1)導電性材料からなるリードフレームと、表面に電
極が形成された半導体チップと、 上記リードフレームの所定位置と上記半導体チップの電
極とを電気的に接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。 - (2)前記リードフレームが絶縁フィルム上に配線パタ
ーンが形成されたTAB方式のものである請求項1記載
の半導体装置。 - (3)前記リードフレームが金属薄膜を打ち抜き加工し
て得られるものである請求項1記載の半導体装置。 - (4)前記半導体チップの表面に形成された電極が アルミニウム層と、 上記アルミニウム層上に形成されたチタン層と上記チタ
ン層上に形成された金層又はニッケル層又は銅層のいず
れか一つの層とから構成されている請求項1記載の半導
体装置。 - (5)絶縁フィルムと、 上記絶縁フィルム上に形成された配線パターンと、 表面に電極が形成された半導体チップと、 上記配線パターンの端面と上記半導体チップの電極とを
電気的に接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。 - (6)前記半導体チップの表面に形成された電極が アルミニウム層と、 上記アルミニウム層上に形成されたチタン層と、上記チ
タン層上に形成された金層又はニッケル層又は銅層のい
ずれか一つの層とから構成されている請求項5記載の半
導体装置。 - (7)半導体チップが接続されたリードフレームと、 表面に配線パターンが形成された配線基板と、上記サー
ドフレームと上記配線基板の配線パターンとを電気的に
接続する金属メッキによる接続部と を具備したことを特徴とする半導体装置。 - (8)導電性材料からなるリードフレームと、表面に電
極が形成された半導体チップと、 上記リードフレームの所定位置と上記半導体チップの電
極とを電気的に接続する導電性の接着剤からなる第1の
接続部と、 上記第1の接続部の周囲を覆うように設けられ上記リー
ドフレームと上記半導体チップの電極とを電気的に接続
する金属メッキによる第2の接続部と を具備したことを特徴とする半導体装置。 - (9)導電性材料からなるリードフレームの所定位置と
半導体チップの表面に形成された電極とを近接させた状
態で該リードフレームに半導体チップを貼着する工程と
、 両者を電界メッキ溶液中に浸して上記リードフレームの
所定位置と上記半導体チップの電極とを電気的に接続す
る金属メッキ層を形成する工程とを具備したことを特徴
とする半導体装置の製造方法。
Priority Applications (13)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2141684A JP2540652B2 (ja) | 1990-06-01 | 1990-06-01 | 半導体装置 |
KR1019910009041A KR970000972B1 (ko) | 1990-06-01 | 1991-05-31 | 반도체 장치 및 그 제조 방법 |
DE69133497T DE69133497T2 (de) | 1990-06-01 | 1991-05-31 | Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren |
EP00103351A EP1020903B1 (en) | 1990-06-01 | 1991-05-31 | A semiconductor device using a lead frame and its manufacturing method |
EP91108886A EP0459493B1 (en) | 1990-06-01 | 1991-05-31 | A semiconductor device comprising a TAB tape and its manufacturing method |
DE69132685T DE69132685T2 (de) | 1990-06-01 | 1991-05-31 | Halbleiteranordnung bestehend aus einem TAB-Band und deren Herstellungsverfahren |
US08/344,605 US5654584A (en) | 1990-06-01 | 1994-11-18 | Semiconductor device having tape automated bonding leads |
US08/461,448 US5556810A (en) | 1990-06-01 | 1995-06-05 | Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating |
KR1019960058149A KR970005714B1 (ko) | 1990-06-01 | 1996-11-27 | 반도체 장치 및 그 제조 방법 |
KR1019960058150A KR970005715B1 (ko) | 1990-06-01 | 1996-11-27 | 반도체 장치 및 그 제조 방법 |
KR1019960058151A KR970005716B1 (ko) | 1990-06-01 | 1996-11-27 | 반도체 장치 및 그 제조 방법 |
KR96058153A KR970005718B1 (en) | 1990-06-01 | 1996-11-27 | A semiconductor device and its menufacture method |
KR1019960058152A KR970005717B1 (ko) | 1990-06-01 | 1996-11-27 | 반도체 장치 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2141684A JP2540652B2 (ja) | 1990-06-01 | 1990-06-01 | 半導体装置 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8011933A Division JP2777345B2 (ja) | 1996-01-26 | 1996-01-26 | 半導体装置 |
JP1193496A Division JP2736247B2 (ja) | 1996-01-26 | 1996-01-26 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0437149A true JPH0437149A (ja) | 1992-02-07 |
JP2540652B2 JP2540652B2 (ja) | 1996-10-09 |
Family
ID=15297809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2141684A Expired - Fee Related JP2540652B2 (ja) | 1990-06-01 | 1990-06-01 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5654584A (ja) |
EP (2) | EP1020903B1 (ja) |
JP (1) | JP2540652B2 (ja) |
KR (1) | KR970000972B1 (ja) |
DE (2) | DE69133497T2 (ja) |
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JPS61208245A (ja) * | 1985-03-13 | 1986-09-16 | Kyushu Hitachi Maxell Ltd | 半導体装置のリ−ドフレ−ム製造方法 |
JPS62108534A (ja) * | 1985-11-06 | 1987-05-19 | Nec Corp | 半導体装置 |
JPH01276750A (ja) * | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH0287538A (ja) * | 1988-09-26 | 1990-03-28 | Hitachi Ltd | テープキャリアモジュール |
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JPS53103659U (ja) * | 1977-01-25 | 1978-08-21 | ||
US4176443A (en) * | 1977-03-08 | 1979-12-04 | Sgs-Ates Componenti Elettronici S.P.A. | Method of connecting semiconductor structure to external circuits |
JPS5524479A (en) * | 1978-08-09 | 1980-02-21 | Nec Corp | Semiconductor |
JPS5750056A (en) * | 1980-09-09 | 1982-03-24 | Toshiba Corp | Information processor having branch trace function |
JPS57143848A (en) * | 1981-02-27 | 1982-09-06 | Nec Corp | Semiconductor device |
US4496965A (en) * | 1981-05-18 | 1985-01-29 | Texas Instruments Incorporated | Stacked interdigitated lead frame assembly |
JPS6092636A (ja) * | 1983-10-27 | 1985-05-24 | Toshiba Corp | 半導体装置の製造方法 |
JPS60115247A (ja) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | 半導体装置 |
US4977441A (en) * | 1985-12-25 | 1990-12-11 | Hitachi, Ltd. | Semiconductor device and tape carrier |
JPH0682705B2 (ja) * | 1986-03-10 | 1994-10-19 | 株式会社東芝 | 半導体装置の実装方法 |
JPS62296431A (ja) * | 1986-06-17 | 1987-12-23 | Alps Electric Co Ltd | フリツプチツプの接続方法 |
JPS6373644A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置の製造方法 |
US4885630A (en) * | 1986-10-27 | 1989-12-05 | Electric Power Research Institute | High power multi-layer semiconductive switching device having multiple parallel contacts with improved forward voltage drop |
US4839713A (en) * | 1987-02-20 | 1989-06-13 | Mitsubishi Denki Kabushiki Kaisha | Package structure for semiconductor device |
JP2623578B2 (ja) * | 1987-07-14 | 1997-06-25 | 日本電気株式会社 | 半導体集積回路装置 |
JPS6473734A (en) * | 1987-09-16 | 1989-03-20 | Nec Corp | Tape carrier |
JPH01207938A (ja) * | 1988-02-15 | 1989-08-21 | Nec Corp | 半導体装置 |
JPH0233929A (ja) * | 1988-07-23 | 1990-02-05 | Nec Corp | 半導体装置 |
JPH0266953A (ja) * | 1988-08-31 | 1990-03-07 | Nec Corp | 半導体素子の実装構造およびその製造方法 |
US5016082A (en) * | 1988-09-16 | 1991-05-14 | Delco Electronics Corporation | Integrated circuit interconnect design |
JP2651608B2 (ja) * | 1988-10-28 | 1997-09-10 | イビデン株式会社 | 電子部品搭載用基板 |
JPH02119252A (ja) * | 1988-10-28 | 1990-05-07 | Nec Corp | 混成集積回路装置 |
JPH02208957A (ja) * | 1989-02-09 | 1990-08-20 | Toshiba Corp | 電子機器用封着材料 |
US4922322A (en) * | 1989-02-09 | 1990-05-01 | National Semiconductor Corporation | Bump structure for reflow bonding of IC devices |
US4948645A (en) * | 1989-08-01 | 1990-08-14 | Rogers Corporation | Tape automated bonding and method of making the same |
-
1990
- 1990-06-01 JP JP2141684A patent/JP2540652B2/ja not_active Expired - Fee Related
-
1991
- 1991-05-31 EP EP00103351A patent/EP1020903B1/en not_active Expired - Lifetime
- 1991-05-31 EP EP91108886A patent/EP0459493B1/en not_active Expired - Lifetime
- 1991-05-31 DE DE69133497T patent/DE69133497T2/de not_active Expired - Fee Related
- 1991-05-31 DE DE69132685T patent/DE69132685T2/de not_active Expired - Fee Related
- 1991-05-31 KR KR1019910009041A patent/KR970000972B1/ko not_active IP Right Cessation
-
1994
- 1994-11-18 US US08/344,605 patent/US5654584A/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61208245A (ja) * | 1985-03-13 | 1986-09-16 | Kyushu Hitachi Maxell Ltd | 半導体装置のリ−ドフレ−ム製造方法 |
JPS62108534A (ja) * | 1985-11-06 | 1987-05-19 | Nec Corp | 半導体装置 |
JPH01276750A (ja) * | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH0287538A (ja) * | 1988-09-26 | 1990-03-28 | Hitachi Ltd | テープキャリアモジュール |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665652A (en) * | 1995-04-12 | 1997-09-09 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device wherein electrodes on a semiconductor chip are electrically connected to lead terminals by plating bonding |
US9417701B2 (en) | 2004-09-13 | 2016-08-16 | Microsoft Technology Licensing, Llc | Flick gesture |
JP2013138511A (ja) * | 2013-03-27 | 2013-07-11 | Taiyo Yuden Co Ltd | 弾性波装置 |
Also Published As
Publication number | Publication date |
---|---|
EP0459493A2 (en) | 1991-12-04 |
KR920001701A (ko) | 1992-01-30 |
DE69133497D1 (de) | 2006-01-19 |
DE69132685T2 (de) | 2002-06-13 |
EP0459493B1 (en) | 2001-08-16 |
EP1020903B1 (en) | 2005-12-14 |
DE69133497T2 (de) | 2006-08-24 |
JP2540652B2 (ja) | 1996-10-09 |
KR970000972B1 (ko) | 1997-01-21 |
EP1020903A1 (en) | 2000-07-19 |
DE69132685D1 (de) | 2001-09-20 |
EP0459493A3 (ja) | 1994-02-23 |
US5654584A (en) | 1997-08-05 |
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