JPH0114707B2 - - Google Patents

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Publication number
JPH0114707B2
JPH0114707B2 JP57111529A JP11152982A JPH0114707B2 JP H0114707 B2 JPH0114707 B2 JP H0114707B2 JP 57111529 A JP57111529 A JP 57111529A JP 11152982 A JP11152982 A JP 11152982A JP H0114707 B2 JPH0114707 B2 JP H0114707B2
Authority
JP
Japan
Prior art keywords
input
chip
wiring
cutting
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57111529A
Other languages
English (en)
Other versions
JPS593950A (ja
Inventor
Shinji Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57111529A priority Critical patent/JPS593950A/ja
Priority to EP83303760A priority patent/EP0098163B1/en
Priority to DE8383303760T priority patent/DE3380507D1/de
Publication of JPS593950A publication Critical patent/JPS593950A/ja
Priority to US06/828,097 priority patent/US4733288A/en
Publication of JPH0114707B2 publication Critical patent/JPH0114707B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明はチツプサイズ自在のゲート・アレイ
LSIチツプに関し、より詳しくは半導体集積回路
チツプの内部にも入出力回路を形成可能にして任
意の大きさおよび任意のゲート数のチツプに切断
可能にしたゲート・アレイLSIチツプに関する。
(2) 発明の背景 半導体集積回路の集積度の向上に伴なつて、必
要に応じて任意のゲート数および任意のチツプサ
イズを持つたゲート・アレイLSIチツプの実現が
要望されるようになつて来た。
(3) 従来技術と問題点 一般に、ゲート・アレイLSIチツプの内部は、
インバータ、NANDゲート、NORゲート等の所
望の回路を構成するための一方向に延びる多数の
ゲート・セル・アレイとこれらのゲート・セル・
アレイ相互に配線を施すために各ゲート・セル・
アレイの間に設けられた配線用領域とからなつて
おり、チツプの周辺には入出力パツドおよび入出
力回路を形成するための入力保護回路、入出力バ
ツフアー等が配列されている。
従来のゲート・アレイLSIチツプは内部に入出
力パツドや入出力回路を形成する領域を持たなか
つたのでチツプを切断することは不可能であり、
１つのバルクパターンからゲート数およびチツプ
サイズが同一の一種類のチツプしか実現できなか
つた。このため、必要なゲート数が少ない場合、
チツプ上に不使用のゲートが存在することにな
り、ゲートに無駄が生じるばかりかチツプサイズ
も不必要に大きなものとなつていた。
(4) 発明の目的 本発明の目的はゲート・アレイLSIチツプ内部
の配線領域に切断領域を設け、その切断領域の近
傍に入出力回路を形成するという構想に基づき、
１チツプのゲート・アレイLSIを切断して複数チ
ツプのゲート・アレイLSIを得ることを可能に
し、それにより設計に応じたゲート数およびチツ
プサイズを持つゲート・アレイLSIチツプを得る
ことにある。
(5) 発明の構成 上記の目的を達成するための本発明の要旨は、
半導体チツプ上に、配線領域と、該配線領域を介
して隔てられて互いに平行に配列された複数のベ
ーシツクセル列とを有し、該配線領域の一部が該
半導体チツプの切断可能領域となつており、該切
断可能領域に接してその両端に配置されたベーシ
ツクセル列と夫々隣接する配線領域の幅は入出力
パツドを配置し得る大きさであることを特徴とす
るゲートアレイチツプにある。
(6) 発明の実施例 以下、図面によつて本発明の実施例を従来例と
対比して説明する。
第１図は従来の１チツプのゲート・アレイLSI
を概略的に示す平面図である。同図において、ゲ
ート・アレイLSIチツプ１の周辺部に入出力パツ
ド２が多数配列されており、入出力パツドの内側
に入出力パツドに隣接して入出力回路３が形成さ
れている。入出力回路３の更に内側の領域には一
方向に延びる多数のベーシツク・セル・アレイ４
が間隔を置いて配列されている。入出力回路３と
ベーシツク・セル・アレイ４との間および各ベー
シツク・セル・アレイ間の領域は配線用領域５で
ある。入出力パツド２、入出力回路３、ベーシツ
ク・セル・アレイ４および配線領域５はバルク６
上に形成されている。
第２図は第１図に示したチツプ１の内側に配列
されているベーシツク・セル・アレイ４とその間
の配線用領域５を示す拡大平面図である。同図に
示されるように、ベーシツク・セル・アレイ４は
バルクパターンで形成された同一構造の多数のベ
ーシツク・セルBCを一方向に配列して構成され
ている。各配線領域５は一般にフイールド部と称
され、バルクパターンを持たない酸化膜の厚い場
所であり、各配線領域５の幅は同一である。この
ように狭い幅の配線領域に入出力パツドを形成す
ることは現在の技術では不可能なので、従来のチ
ツプの内側に入出力パツドや入出力回路を形成す
ることができず、従つてチツプを切断して所望の
ゲート数あるいは所望のチツプサイズのチツプを
得ることができなかつた。
第３図は本発明の一実施例によるゲート・アレ
イLSIチツプの概略を示す平面図である。同図に
おいて、チツプ１０の周辺部のバルク１５上には
従来同様に多数の周辺入出力パツド２０が配列さ
れており、周辺入出力パツド２０の内側には従来
同様に周辺入出力パツド２０に隣接して周辺入出
力回路３０が形成されている。各辺の入出力パツ
ドおよび入出力回路は、本発明により設けられた
切断領域（図の斜線部分）６１，６２によつて分
離されている。本実施例においては、チツプ１０
は切断領域６１，６２によつて４個の小チツプに
分断可能なようになつている。周辺入出力回路３
０の更に内側には、縦方向に延びるベーシツク・
セル・アレイ４０が配線領域５０を介して多数配
列されている。ベーシツク・セル・アレイ４０の
各々は、チツプの中央を横方向に延びている切断
領域６２によつて上下に分離されている。チツプ
中央部の上側を縦方向に走行する、隣接する２つ
のベーシツク・セル・アレイ４０1，４０2の間の
配線領域、およびチツプ中央部の下側を縦方向に
走行する、隣接する２つのベーシツク・セル・ア
レイ４０3，４０4の間の配線領域が縦方向に走行
する切断領域６１となつている。ベーシツク・セ
ル・アレイ４０1，４０3に隣接し、且つベーシツ
ク・セル・アレイ４０1に関して切断領域６１と
反対の側にある配線領域５０1は入出力パツド形
成領域となつている。同様にベーシツク・セル・
アレイ４０2，４０4に隣接する配線領域５０2も
入出力パツド形成領域となつている。配線領域５
０1に隣接する２つのベーシツク・セル・アレイ
４０5，４０6とその間の配線領域５０3とで入出
力回路IO1が形成される。同様に、配線領域５０2
に隣接する２つのベーシツク・セル・アレイ４０
７，４０8とその間の配線領域５０4とで入出力回
路IO2が形成される。下側にも同様にして配線領
域５０1，５０2にそれぞれ隣接して入出力回路
IO3，IO4がそれぞれ形成される。本実施例にお
いては、切断領域６１となる配線領域の幅を他の
配線領域の幅より小とし、入出力パツド形成領域
となる配線領域５０1および５０2の幅を他の配線
領域の幅より大として、入出力パツドの形成を可
能にしている。
一方、横方向に走行する切断領域６２内の上側
および下側にもそれぞれ入出力パツドが形成さ
れ、この切断領域６２の近傍の必要な数のベーシ
ツク・セルと必要な面積の配線領域５０とで入出
力回路IO5，IO6，IO7およびIO8が形成される。
切断領域の中央で切断することにより、ゲー
ト・アレイLSIチツプ１０は４個のチツプに分離
することができる。
入出力パツドおよび入出力回路が形成される分
離領域の近傍を第４図以下によつて更に詳細に説
明する。
第４図は第３図のチツプを縦方向に切断する前
と切断後のチツプの一部を示す拡大平面図であ
る。同図の上側は切断前のチツプの一部を示して
おり、下側は切断後のチツプの一部を示してい
る。各ベーシツク・セル・アレイは従来同様に、
同一構造の多数のベーシツク・セル（BC）を一
方向に配列して構成されている。各ベーシツク・
セル（BC）の寸法は従来と同一である。切断領
域６１と入出力パツド形成領域５０1以外の、ベ
ーシツク・セル・アレイ間の配線領域の幅は従来
と同一であるが、切断領域６１の幅は他の配線領
域の幅より狭く、入出力パツド形成領域５０1の
幅は他の配線領域の幅より広くしてある。入出力
パツド形成領域５０1の幅を他の配線領域の幅よ
り広くしたことにより、入出力パツド形成領域５
０1に入出力パツドを形成することができるよう
になつた。
入出力回路を形成する場合必要なものは、保護
ダイオード、入力バツフア、出力バツフア、およ
びトライステート出力回路である。このうち、入
力バツフアや、出力バツフア、またトライステー
ト出力回路などは入出力回路の種類により不要の
場合もある。出力バツフアとトライステート用出
力回路を構成するトランジスタのゲート幅はベー
シツクセル（BC）を構成するトランジスタのゲ
ート幅の整数倍なので、出力バツフアとトライス
テート用出力回路はベーシツク・セル・アレイ４
０5および４０6のベーシツクセルで構成される。
入力バツフアを構成するトランジスタのゲート幅
はベーシツク・セル・アレイのトランジスタのゲ
ート幅より小なので、ベーシツク・セル（BC）
で構成することができない。このため、ベーシツ
ク・セル・アレイ４０5と４０6の間の配線領域５
０3に予め、入力バツフアと保護ダイオードを形
成するための不純物領域からなるバルクパターン
B1を形成しておく。この、バルクパターンB1が
形成されている入出力回路用領域は、入力バツフ
アを構成するMOSトランジスタのソース、ドレ
イン領域、バイポーラトランジスタのベース、エ
ミツタ領域、および保護ダイオードの拡散領域と
なるものであり、チツプを切断線l1に沿つて切断
しない場合には窓あけを行わないことにより他の
配線領域と同様に配線領域として使用できる。
第４図の下側に、切断線l1に沿つてチツプ１０
を切断した状態が示されている。切断後は、ベー
シツク・セル・アレイ４０1は使用されないので
点線で示してある。配線領域５０1に入出力パツ
ドP1が形成されている。配線領域５０1の幅を、
入出力パツドP1の一辺の長さとその周辺の有効
パターン禁止領域の和より大にしておけば、入出
力パツドＰを配線領域５０1に形成することが可
能である。ベーシツク・セル・アレイ４０5，４
０6のベーシツク・セル（BC）と、その間の配線
領域５０3に形成された入力バツフアおよび保護
ダイオードのためのバルクパターンB1とで、入
出力回路IOXが形成されている。
第５図は第３図のチツプを横方向に切断する前
と切断後のチツプの一部を示す拡大平面図であ
る。同図の左側は切断前のチツプの一部を示して
おり、右側は切断後のチツプの一部を示してい
る。切断領域６２は、その中に入出力パツドを形
成可能なように充分に広い幅を持つている。切断
領域６２に近い領域において、ベイシツクセルア
レイ４０の間の配線領域５０の各々に、入力バツ
フアおよび保護ダイオードのための不純物領域の
バルクパターンB2を、第４図に示したバルクパ
ターンB1と同様に形成しておく。切断線l2に沿つ
てチツプを切断した状態が同図右側に示されてい
る。切断領域６２内に入出力パツドP2が形成さ
れており、この入出力パツドP2の近傍のベーシ
ツク・セル・アレイ４０内の必要なベーシツク・
セル（BC）とその隣りに形成されているバルク
パターンB2とで入出力回路IOYが形成されてい
る。
第６図は第４図の平面図において、切断後に配
線を施した状態を示す図、第７図は第４図の平面
図において、チツプを切断しないで用いる場合の
配線を施した図である。第６図に示されているよ
うに、チツプを縦方向に切断する場合は、切断領
域６１に隣接するベーシツク・セル・アレイ４０
１に対しては配線が施されず、またバルクパター
ンB1に対しては窓あけが行われて配線が施され
て入出力回路が形成される。チツプを切断しない
で使用する場合は、第７図に示されるように、切
断領域６１は通常の配線領域として使用され、バ
ルクパターンB1に対しては窓あけがなされない
ので領域５０3も通常の配線領域として使用でき
る。
以上の実施例の説明においてはゲート・アレイ
LSIチツプを４等分に切断する例を示したが、本
発明はこれに限らず、縦方向の切断領域６１およ
び横方向の切断領域６２は必要に応じて任意の位
置に設けることが可能である。また、切断領域は
同一方向に２つ以上設けてもよい。
(7) 発明の効果 以上説明したように、本発明によれば、ゲー
ト・アレイLSIチツプ内部の配線領域に切断領域
を設け、その切断領域の近傍に入出力回路を形成
することにより、１チツプのゲート・アレイLSI
を切断して複数チツプのゲート・アレイLSIを得
ることができるので、設計に応じて無駄のないゲ
ート数およびチツプサイズを有するゲート・アレ
イLSIチツプが得られる。
【図面の簡単な説明】
第１図は従来の１チツプのゲート・アレイLSI
を概略的に示す平面図、第２図は第１図の平面図
の一部拡大図、第３図は本発明の一実施例による
ゲート・アレイLSIチツプの概略を示す平面図、
第４図は第３図のチツプを縦方向に切断する前と
切断後のチツプの一部を示す拡大平面図、第５図
は第３図のチツプを横方向に切断する前と切断後
のチツプの一部を示す拡大平面図、第６図は第４
図において、チツプ切断後に配線を施した状態を
示す平面図、そして第７図は第４図において、チ
ツプを切断しないで用いる場合の配線を施した状
態を示す平面図である。 １０……ゲート・アレイLSIチツプ、１５……
バルク、２０……入出力パツド、３０……入出力
回路、４０……ベーシツク・セル・アレイ、５０
……配線領域、５０1，５０2……入出力パツド形
成領域、５０3……入出力回路用不純物領域、６
１，６２……切断領域、IO1〜IO8……入出力回
路。

Claims (1)

    【特許請求の範囲】
  1. １ 半導体チツプ上に、配線領域と、該配線領域
    を介して隔てられて互いに平行に配列された複数
    のベーシツクセル列とを有し、該配線領域の一部
    が該半導体チツプの切断可能領域６１となつてお
    り、該切断可能領域に接してその両端に配置され
    たベーシツクセル列４０1，４０2と夫々隣接する
    配線領域の幅は入出力パツドを配置し得る大きさ
    であることを特徴とするゲートアレイチツプ。
JP57111529A 1982-06-30 1982-06-30 ゲ−トアレイチツプ Granted JPS593950A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57111529A JPS593950A (ja) 1982-06-30 1982-06-30 ゲ−トアレイチツプ
EP83303760A EP0098163B1 (en) 1982-06-30 1983-06-29 Gate-array chip
DE8383303760T DE3380507D1 (en) 1982-06-30 1983-06-29 Gate-array chip
US06/828,097 US4733288A (en) 1982-06-30 1986-02-10 Gate-array chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57111529A JPS593950A (ja) 1982-06-30 1982-06-30 ゲ−トアレイチツプ

Publications (2)

Publication Number Publication Date
JPS593950A JPS593950A (ja) 1984-01-10
JPH0114707B2 true JPH0114707B2 (ja) 1989-03-14

Family

ID=14563643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57111529A Granted JPS593950A (ja) 1982-06-30 1982-06-30 ゲ−トアレイチツプ

Country Status (4)

Country Link
US (1) US4733288A (ja)
EP (1) EP0098163B1 (ja)
JP (1) JPS593950A (ja)
DE (1) DE3380507D1 (ja)

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JPS593950A (ja) 1984-01-10
DE3380507D1 (en) 1989-10-05
US4733288A (en) 1988-03-22
EP0098163A2 (en) 1984-01-11
EP0098163B1 (en) 1989-08-30
EP0098163A3 (en) 1986-04-16

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