JPS5779655A - Manufacture of integrated circuit chip - Google Patents

Manufacture of integrated circuit chip

Info

Publication number
JPS5779655A
JPS5779655A JP15543580A JP15543580A JPS5779655A JP S5779655 A JPS5779655 A JP S5779655A JP 15543580 A JP15543580 A JP 15543580A JP 15543580 A JP15543580 A JP 15543580A JP S5779655 A JPS5779655 A JP S5779655A
Authority
JP
Japan
Prior art keywords
manufacture
mask
integrated circuit
circuit chip
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15543580A
Other languages
Japanese (ja)
Inventor
Joichi Fuwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP15543580A priority Critical patent/JPS5779655A/en
Publication of JPS5779655A publication Critical patent/JPS5779655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture IC chips of different integration degrees in common with a mask except a field mask, by forming a scribing line with a use of a field mask which makes a plurality of unit regions a chip region. CONSTITUTION:A unit region 1a forms a basic unit of a master slice to be manufactured. A certain electronic element is formed in it. A scribing line shown in a dotted or solid line is defined by a field mask. A chip is obtained by cutting by LASER or with a cutter after wafer-processing. Chips of different integration degrees can easily be formed only by changing field masks.
JP15543580A 1980-11-05 1980-11-05 Manufacture of integrated circuit chip Pending JPS5779655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15543580A JPS5779655A (en) 1980-11-05 1980-11-05 Manufacture of integrated circuit chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15543580A JPS5779655A (en) 1980-11-05 1980-11-05 Manufacture of integrated circuit chip

Publications (1)

Publication Number Publication Date
JPS5779655A true JPS5779655A (en) 1982-05-18

Family

ID=15605957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15543580A Pending JPS5779655A (en) 1980-11-05 1980-11-05 Manufacture of integrated circuit chip

Country Status (1)

Country Link
JP (1) JPS5779655A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207653A (en) * 1982-05-28 1983-12-03 Toshiba Corp Master wafer for semiconductor integrated circuit
JPS593950A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Gate array chip
JPH03136368A (en) * 1989-10-23 1991-06-11 Nec Corp Master slice system in semiconductor integrated circuit
US5138419A (en) * 1988-06-01 1992-08-11 Fujitsu Limited Wafer scale integration device with dummy chips and relay pads

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207653A (en) * 1982-05-28 1983-12-03 Toshiba Corp Master wafer for semiconductor integrated circuit
JPS593950A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Gate array chip
JPH0114707B2 (en) * 1982-06-30 1989-03-14 Fujitsu Ltd
US5138419A (en) * 1988-06-01 1992-08-11 Fujitsu Limited Wafer scale integration device with dummy chips and relay pads
JPH03136368A (en) * 1989-10-23 1991-06-11 Nec Corp Master slice system in semiconductor integrated circuit

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