GB2215512A - Semiconductor integrated circuits - Google Patents
Semiconductor integrated circuits Download PDFInfo
- Publication number
- GB2215512A GB2215512A GB8804300A GB8804300A GB2215512A GB 2215512 A GB2215512 A GB 2215512A GB 8804300 A GB8804300 A GB 8804300A GB 8804300 A GB8804300 A GB 8804300A GB 2215512 A GB2215512 A GB 2215512A
- Authority
- GB
- United Kingdom
- Prior art keywords
- arrays
- array
- array structure
- lanes
- scribe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A semiconductor array structure, such as a bipolar analogue array, is provided as a plurality of arrays on a substrate wafer, two or more of which arrays may be interconnected across a scribe lane or lanes (12) to provide larger composite arrays (11b). This allows the manufacturer to provide a single basic array structure which can then be configured by the customer to provide a desired array size. <IMAGE>
Description
IMPROVEMENTS IN INTEGRATED CIRCUITS.
This invention relates to integrated circuits, and in particular to semi-custom circuits in which an array of devices is interconnected in a particular way by the customer to provide a desired circuit function.
Semi-custom semiconductor arrays, for example bipolar analogue arrays, comprise a plurality of devices provided on a substrate chip by the manufacturer. Those devices are then interconnected, using customer determined masks, to provide desired circuit functions.
Because of varying customer requirements, the semiconductor array manufacturer produces a variety of array sizes to allow functions of varying complexity to be integrated efficiently. This practice carries the penalty that the manufacturer must run a variety of base wafers on his production line with the attendant logistic and inventory problems.
The object of the invention is to minimise or to overcome this disadvantage.
According to the invention there is provided a semiconductor array structure disposed on a semiconductor wafer and comprising a regular arrangement of arrays, and scribe lanes between adjacent arrays, the arrangement being such that two or more adjacent arrays may be interconnected across the scribe lane or lanes therebetween to provide a composite array.
An embodiment of the ivention will now be described with reference to the accompanying drawings in which:
Figure 1 shows an array structure disposed on a
semiconductor wafer;
Figure 2 shows the array structure of Figure 1
configured as a plurality of individual arrays; and Figures 3 and 4 illustrate the manner of
coupling array to form a composite array
struture.
Referring to Figure 1, this shows a plurality of arrays 11, e.g. bipolar analogue arrays, disposed on a semiconductor wafer. Each array comprises a number of cells (not shown) which, in use, may be interconnected by one or more custom masks to provide a desired circuit function . The individual arrays 11 use mutually separated by scribe lanes or corridors 12. These lanes are relatively wide to allow the provision of bonding pads adjacent the arrays. Typically the scribe lanes are provided with an insulating oxide film to permit interconnection across the scribe lanes of adjacent arrays. In some applications the scribe lanes may contain active and/or passive devices.
Figure 2 shows the array structure of Figure 1 after processing with one or more custom masks to form a plurality of individual arrays Ila. Each array lla is provided with a set of bonding pads 21. The arrays may be separated from the wafer by cutting along the scribe lanes 12. In this arrangement no connection is made between adjacent arrays.
Figure 3 shows the method of coupling adjacent pairs of arrays to form a double sized array llb. No bond pads are provided between the adjacent halves of the array, but the halves of the array may be interconnected, e.g. by metal of polysilicon tracks (not shown) across the scribe lane therebetween. The chip space released by omission of the bond pads may be occupied by additional devices.
Figure 4 shows a modification of the structure of Figure 3 wherein further bonding pads are omitted and four adjacent arrays are interconnected to provide a quadruple array llc. It will be appreciated that the technique can be extended to provide larger rectangular or square arrays. The particular array size is determined by the customer, based on the array structure of Figure 1 provided as a single stock item by the manufacturer.
Whilst it is preferred to employ this technique in the production of bipolar analogue arrays, it will be understood that other transistor technologies can also be treated in a similar manner.
Claims (4)
1. A semiconductor array structure disposed on a semiconductor wafer and comprising a regular arrangement of arrays, and scribe lanes between adjacent arrays, the arrangement being such that two or more adjacent arrays may be interconnected across the scribe lane or lanes therebetween to provide a composite array.
2. An array structure as claimed in claim 1, wherein said scribe lanes are provide with an insulating oxide coating.
3. An array structure as claimed in claim 1 or 2, wherein active and/or passive devices are provided in said scribe lanes.
4. A semiconductor array structure substantially as described herein with reference to and as shown in
Figure 1 or Figures 1 to 4 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8804300A GB2215512A (en) | 1988-02-24 | 1988-02-24 | Semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8804300A GB2215512A (en) | 1988-02-24 | 1988-02-24 | Semiconductor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8804300D0 GB8804300D0 (en) | 1988-03-23 |
| GB2215512A true GB2215512A (en) | 1989-09-20 |
Family
ID=10632275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8804300A Withdrawn GB2215512A (en) | 1988-02-24 | 1988-02-24 | Semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2215512A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0742589A1 (en) * | 1995-05-09 | 1996-11-13 | United Memories, Inc. | Bond pad option for integrated circuits |
| KR101539255B1 (en) * | 2012-03-30 | 2015-07-24 | 사빅 글로벌 테크놀러지스 비.브이. | Compressing members including a polymeric material, compressors, and method of making the compressing members |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1254365A (en) * | 1968-12-02 | 1971-11-24 | Telefunken Patent | Method of dividing a semiconductor wafer |
| EP0098163A2 (en) * | 1982-06-30 | 1984-01-11 | Fujitsu Limited | Gate-array chip |
| GB2168840A (en) * | 1984-08-22 | 1986-06-25 | Plessey Co Plc | Customerisation of integrated logic devices |
| US4612408A (en) * | 1984-10-22 | 1986-09-16 | Sera Solar Corporation | Electrically isolated semiconductor integrated photodiode circuits and method |
-
1988
- 1988-02-24 GB GB8804300A patent/GB2215512A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1254365A (en) * | 1968-12-02 | 1971-11-24 | Telefunken Patent | Method of dividing a semiconductor wafer |
| EP0098163A2 (en) * | 1982-06-30 | 1984-01-11 | Fujitsu Limited | Gate-array chip |
| GB2168840A (en) * | 1984-08-22 | 1986-06-25 | Plessey Co Plc | Customerisation of integrated logic devices |
| US4612408A (en) * | 1984-10-22 | 1986-09-16 | Sera Solar Corporation | Electrically isolated semiconductor integrated photodiode circuits and method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0742589A1 (en) * | 1995-05-09 | 1996-11-13 | United Memories, Inc. | Bond pad option for integrated circuits |
| US5698903A (en) * | 1995-05-09 | 1997-12-16 | United Memories, Inc. | Bond pad option for integrated circuits |
| US5763298A (en) * | 1995-05-09 | 1998-06-09 | United Memories, Inc. | Bond pad option for integrated circuits |
| KR101539255B1 (en) * | 2012-03-30 | 2015-07-24 | 사빅 글로벌 테크놀러지스 비.브이. | Compressing members including a polymeric material, compressors, and method of making the compressing members |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8804300D0 (en) | 1988-03-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |