GB2168840A - Customerisation of integrated logic devices - Google Patents

Abstract

A method of manufacturing integrated logic devices in which a relatively large general array of gates and/or other devices is produced by a diffusion and/or other process over the surface of a stock wafer (e.g. silicon) without scribe lanes or with scribe lanes provided in one direction only. The wafer is then customerised by metallisation and scribing into the chosen sizes.

Description

SPECIFICATION Improvements relating to integrated logic devices This invention relates to the manufacture of integrated logic devices and is especially, but not exclusively, concerned with an improved method of manufacturing semiconductor logic arrays or chips.

Semiconductor logic arrays or chips are presently fabricated by a fairly protracted diffusion process during which a multiplicity of logic arrays each comprising a gate array with associated components (eg. input/qutput buffers and diode protection devices) are produced on a wafer (e.g.

circular) of semiconductor material, commonly silicon. The diffusion process is followed by a shorter term metallisation process by which metal (e.g. aluminium) interconnections are provided between predetermined gates of each logic array and their associated components and bonding pads are also formed on the wafer to facilitate the making of external electrical connections to the final logic array product.

The multiplicity of logic arrays are arranged to occupy respective surface areas of the wafer defined by scribe lanes which normally serve to delineate chips on the wafer and which delineation is built up through successive layers of processing in the diffusion and metallisation processes. These scribe lanes determine how the wafer is to be divided, as by sawing, into individual rectangular chips each of which carries a logic array. The logic arrays produced on a wafer will usually be identical with one another but the metal interconnections made between the gates and their associated components during the metallisation process will often vary from wafer to wafer according to specific circuit requirements.

In practice it has been found that as many as 30of the gates of each gate array may not be utilised in the logic array provided on each chip.

The present invention seeks to obviate this undesirable wastage of gates by providing a manufacturing method in which a relatively large general array of gates and/or other devices is produced by a diffusion and/or other process over the surface of a diffusion stock wafer (eg. silicon) without scribe lanes or with scribe lanes in one direction only being provided. Appropriate selected groups of these gates and/or other devices may subsequently be subjected to a metallisation process for producing according to specific circuit requirements metal interconnections between gates and/or other devices of the groups after which the wafer will be appropriately divided into chips embodying the individual logic devices as determined by scribe lanes provided during metallisation.

It will readily be apparent that by omitting all scribe lanes or the scribes lanes in one direction until the metallisation process during which the specific content of the logic arrays including associated components is finally determined, the size of chip can be varied not only to accommodate specific logic arrays according to requirements but also to avoid wastage of gates.

The method according to the present invention may be better understood from the accompanying drawings.

Figure 1 shows purely in diagrammatic form a semiconductor wafer having a multiplicity of chips constituting logic arrays produced thereon in known manner.

Referring to Figure 1, the semiconductor wafer or substrate 1 may be of silicon but other semiconductor materials, such as gallium arsenide, could be used or the wafer or substrate could be made of an inert substance and provided with thin coating of semiconductor (e.g. silicon on sapphire). By means of a diffusion process which may last several months followed by a metallisation process a multiplicity of logic arrays including identical gate arrays and associated diffused devices are formed over the wafer 1 so that they occupy the areas 2 between horizontal and vertical scribe lanes 3 and 4 which serve to delineate chips and which are build up through successive layers of processing in the diffusion and metallisation processes.The metallisation process in which metal (usually aluminium) interconnections are deposited, as by the sputtering of metal through suitable masks on to the wafer 1, interconnects some of the gates of each array according to circuit requirements as well as laying down metal bond pads for subsequently making external electrical connections to the logic arrays or chips. Using the scribe lanes 3 and 4 the wafer 1 is finally sawn into rectangular chips, each comprising a logic array.

One disadvantage with this known method for the fabrication of logic arrays is that the chip size and shape are predetermined by the scribe lanes of the diffusion stock wafer 1. Consequently, a significant number of the gates in each logic array carried by a chip may be ununsed and the specific logic array circuit requirements are determined by the chip dimensions.

The present invention is based on the realisation that by leaving the diffusion stock wafer without scribe lanes or with scribe lanes in one direction (e.g. horizontal), the final size and shape of chips may then be chosen according to specific circuit requirements and thereby facilitate more economical use of gates.

Figure 2 shows, also in purely diagrammatic form, a semiconductor wafer without scribe lanes and provided with a general array of gates and associated components produced thereon in readiness for a metallisation treatment and subsequent scribing in accordance with the present invention.

Referring now to Figure 2, this illustrates diagrammatically the principle of the invention. As can be seen, the wafer 5 (e.g. silicon) is left without scribe lanes but as before the wafer has a multiplicity of gate arrays 6 including associated diffused devices formed thereon by a diffusion process. Such wafers may then be retained in stock until specific logic array circuit arrangements utilising these gate arrays are called for. These specific logic arrays may be produced by applying metallisation techniques to the wafer 5 for the provision of interconnections between gates and asso ciated diffused devices and thus this metallisation procedure determines the size and shape of the chip required.When the chip size for maximum utilisation of the gates is thus determined, the wafer 5 can then be formed with scribe lanes during the metallisation process to facilitate the division, as by sawing, of the wafer into individual logic arrays or chips.

In another embodiment of the invention the wafer may be provided with scribe lanes in one direction (e.g. horizontal) during the diffusion process before the metallisation process in order to provide elongate fingers which can finally be divided into smaller lengths, as dictated by the specific circuit requirements, facilitated by the provision of scribe lanes on the wafer in a vertical direction.

As will be appreciated from the foregoing description, the process according to the invention provides the following advantages.

1) improved gate utilisation - the chip size and shape are adapted to the specific circuit thereby enabling a chip to be produced with a negligible number of unused gates; 2) yield improvement - by producing chips without redundant gates, the chip size is reduced and the number of chips per wafer is proportionately increased; 3) simplified product line - only one form of wafer (without scribe lanes) is needed, not an entire family of different sizes. Consequently, savings are made in design and mask procurement; and 4) reduced stock - only one form of wafer (without scribe lanes) needs to be stocked, not an entire family.

Although in the specific description the invention is described as applied to semiconductor logic devices it should be understood that the invention is also applicable to other devices providing integrated logic functions (e.g. superconducting logic devices) which involve different manufacturing processes.

Claims (4)

1. A method of manufacturing integrated logic devices in which a relatively large general array of gates and/or other devices is produced by a diffusion and/or other process over the surface of a diffusion stock wafer (e.g. silicon) without scribe lanes or with scribe lanes provided in one direction only.

2. A method as claimed in claim 1, in which selected groups of the gates and/or other devices are subjected to a metallisation process for producing according to specific circuit requirements metal interconnections between gates and/or other devices of the groups after which the wafer will be appropriately divided into chips embodying the individual logic devices as determined by scribe lanes provided during metallisation.

3. Semiconductor logic arrays or chips manufactured by the method according to claim 1 or claim 2.

4. A method of manufacturing a semiconductor logic array or chip substantially or hereinbefore described with reference to the accompanying drawing.