GB2122417A - Integrated circuits - Google Patents

Abstract

An uncommitted logic array (ULA) integrated circuit comprises cells of different complexity in order to provide flexibility of interconnection and enable the integrated circuit chip size to be minimised. The integrated circuit chip (31) may be provided with a plurality of sets (30) of cells (32, 33, 34). The cells 32, which are the smallest, are committed to a specific function and have a high transistor density per unit area. The cells 33 have the same type and number of transistors as the cells 32 but are of a larger area. The transistors of cells 33 are only partially interconnected but can be interconnected, by means of a customised metallisation pattern, to provide the same specific function as cells 32, or can be interconnected to provide lower complexity logic functions if the specific function is not required. The largest cells 34 contain unconnected or only partially interconnected transistor arrays, have the lowest transistor density per unit area of the three sizes of cells, and may be interconnected merely to provide required low complexity logic functions. <IMAGE>

Description

SPECIFICATION Integrated circuits This invention relates to integrated circuits and in particular to integrated circuits including uncommitted logic arrays.

According to the present invention there is provided an integrated circuit chip adapted to be committed to provide a desired function in dependence on the configuration of an electrically-conductive interconnection pattern to be applied thereto, the chip including a plurality of transistor array cells of at least two types.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which Figure 1 shows, schematically, the lay-out of an integrated circuit including a plurality of islands for transistor arrays and input/output buffer cells; Figure 2 shows a block circuit diagram of a committed D-type bistable latch with gated set and reset; Figure 3 shows a block circuit diagram of a so-called uncommitted D-type bistable; Figures 4, 5 and 6 show schematically three groups of different function which can be obtained from the uncommitted D-type of Fig. 3; Figure 7 shows a specific circuit diagram for the D-type bistable latch of Figs. 2 and 3, the connections required to provide the committed form from the uncommitted form being indicated by thickened link lines 41 to 61;; Figures 8a, b and C show the relevant portion A' of Fig. 7 and the interconnections required to make the different functions of Figs. 4a, b and C, respectively; Figures 9a and b show the relevant portion B' of Fig. 7 as the interconnections required to make the different functions of Figs. 5a and b, respectively, and Figures 10a and b show the relevant portion C' of Fig. 7 and the interconnections required to make the different functions of Figs. 6a and b, respectively.

Uncommitted logic (transistor) arrays are employed in integrated circuit manufacture in order to minimise the number of specific fabrication masks required, and thus the cost, for low volume orders of specific function devices. Thus for each of a family of devices the same fabrication masks are employed up to the metallisation (interconnection) stage but different metallisation masks are employed.

Therefore, the component lay-out is standardised and fixed, but for each new application the final metallisation (electrically-conductive) pattern is customised. It is, therefore essential that the fixed component lay-out is such that the elements thereof can be interconnected in a sufficient number of different ways to provide design flexibility with efficient use of integrated circuit chip area.

Generally uncommitted logic arrays comprise, for example, a plurality of spaced-apart cells arrayed in rows and columns, each cell being identical and comprising a plurality of transistors which are not, or which are only partially, interconnected. In dependence on the metallisation (interconnection) patterns used the transistors within the cells can be interconnected to provide a required logic function and larger functions can be created by interconnecting adjacent cells.

In certain applications, for example telecommunications, it may always be necessary to interconnect pluralities of the transistors to provide specific functions, for instance timing latches comprised by D-type bistable circuits, whereas other functions are not always required. A specific function, such as a timing latch, can be provided on a smaller chip area than a plurality of transistors in an array which can be interconnected to provide that and other functions. Thus we now propose to have cells of varying complexity on the chip.However, in certain cases if the chip includes only two types of cell, a number of specific function cells together with a number of transistor array cells, there is a ratio limitation between the specific function cells and the transistor array cells, since it is undesirable to have to create too many additional ones of the specific function from the separate transistors of the arrays.

An embodiment of the present invention solves this particular problem by having three types of cell on an integrated circuit chip. As shown in Fig. 1, an integrated circuit chip 31 has a plurality of sets 30 of islands 32, 33 and 34 containing specific logic elements, formed from transistors, or transistor arrays.

Each island of the chip 31 is surrounded by corridors in which interconnections (not shown) are arranged, the islands have metallic connection contacts arranged at least on their sides adjacent a major horizontal corridor to which the interconnections are to be applied.

In the arrangement shown there are seven major horizontal corridors 35, two major vertical corridors 36 and minor vertical corridors 37 between each island. Around the periphery of the circuit are input/output buffer cells 38.

The five major horizontal corridors 35 between the rows of islands may include an interconnect bus structure as described in our co-pending Application No. 821 5942 (Serial No. ) (D.J.Rogers 3) and which may comprise, for example, eight metallic bus tracks arranged, in groups of four, in bus subcorridors, on an insulating layer overlying the integrated circuit substrate. Under the insulating layer and extending at right angles to the bus tracks are conductive tracks of various lengths. The ends of the tracks are accessible from the surface of the insulating layer by metallic contacts extending in apertures through the insulating layer.In order to gain access to the innermost pair of each group of four bus tracks the spacing between these two bus tracks increases at intervals to allow underlying conductive tracks to be contacted via apertures in the insulating layer and metal contacts disposed therein. In dependence on the configuration of a single layer metallisation pattern applied to connect the contacts, the bus tracks, and contacts of the cells arranged adjacent the interconnect corridor, any one of the cell contacts can be connected to any one of the bus tracks.

Initially-empty sub-corridors adjacent the bus sub-corridors facilitate joining of conductive tracks spaced along the length of the corridor by means of appropriate metal tracks arranged on the insulating layer in the initially-empty sub-corridors. Other suitable bus structures may alternatively be employed to interconnect the logic functions within the cells on a chip.

The islands 32, 33 and 34 of a set 30 are of different sizes, island 32 being smaller than island 33, which is in turn smaller than island 34. Each island is divided into two portions (cells), each containing an identical transistor array or specific function and being symmetrical about the indicated central dividing line 39.

The specific function cells, for example Dtype bistable (latch circuits) are arranged within the smaller islands 32, two per island, whereas the transistor arrays necessary to provide flexibility of the overall circuit are arrayed within the largest islands 34, which despite their size contain fewer transistors than the islands 34. The intermediate-sized islands 33 contain the same number of transistors as the smaller islands 32 and can if required be connected to provide exactly the same logic function as the smaller islands 32.

However, the transistors of the islands 33 are only partly interconnected so that certain ones thereof can be interconnected otherwise than as required for the islands 32 to provide logic elements of lower complexity than the islands 32, if that function is not required in the islands 33. The following description illustrates various of such possibilities when the specific logic functions of islands 32 are Dtype bistables (latching circuits), referred to as committed D-types, and the transistors of the islands 33 can be interconnected, in accordance with the metallisation (electrically-conductive) pattern applied thereto, to provide Dtype bistables, thus referred to as uncommitted D-types, or other logic elements, such as inverters, NOR or NAND functions. The transistor arrays of islands 34 may be as described in our co-pending Application No.

8215940 (Serial No. ) (D.J.Rogers 1) and which comprise a plurality of transistor sub-arrays each including a series connection of two, first and second, p-channel MOS transistors and a series connection of two, first and second, n-channel transistors. The gate electrode of the first p-channel transistor is connected to the gate electrode of the first nchannel transistor, and the gate electrode of the second p-channel transistor is connected to the gate electrode of the second n-channel transistor. The transistor pairs are otherwise unconnected, at least initially, so that the transistor array is uncommitted. Depending on the pattern thereof a single layer metallisation (electrically-conductive; layer can be employed to interconnect the transistors within the array boundary in order to provide a particular logic function.The islands 33 are generally bigger than the islands 32, despite being interconnectible to provide exactly the same logic function, since extra chip surface area is required for the additional transistor interconnection possibilities and thus the transistors of islands 33 may be spaced further apart than these of islands 32 or laid out in a manner to provide the required extra surface area for interconnection purposes within the islands.

Fig. 2 shows the circuit diagram of a committed D-type bistable circuit which is particularly useful for telecommunications purposes.

The circuit comprises inverters G1, G2, G3 and G5, NAND gates G7, G8, G9 and G10 and gates G4 and G6. Inverters G3 and G5 provide the necessary clock signals CLK' and CLK' from a clock signal CLK. Gates G4 and G6 comprise transistor arrays T4A and T4B, and T6A and T6B, respectively. Each transistor array, such as T4A, comprises a respective N and P transistor as will be apparent from Fig. 7 described in detail hereinafter.

Fig. 3 shows an uncommitted D-type circuit. The individual elements are the same as in Fig. 2 but they are only partially interconnected, by solid lines, the additional connections required to commit the circuit to the Dtype being indicated by dashed lines. NAND gate G8 is effectively separate from the remainder of the circuit and has input terminals 1 and 2, and an output terminal 6; similarly NAND gate G9 is effectively separate and has inputs 14, 15 and output 16. The inverters G1, G2, G3 and G5 are also effectively separate from the rest of the circuit with input terminals 7, 8, 17 and 18 and output terminals 9, 10, 19 and 20, respectively. Output terminals 9 and 10 corresponding to the 0 and 0 outputs of the bistable circuit, respectively.

The inverters G3 and G5 of the uncommitted D-type of Fig. 3 may be inter connected, by the use of appropriate metallisation patterns for the constituent transistors, to provide, for example, a two input NAND gate as indicated in Fig. 4a or a two input NOR gate as indicated in Fig. 4b or the inverter G3 and G5 may be employed independently of the clock signal, as indicated in Fig. 4c, for example.

The two input NAND gates G8 and G9 of the uncommitted D-type of Fig. 3 may be used independently of the remaining gates thereof, as indicated in Fig. 5a, or combined by means of a suitable metallisation pattern to provide a four input NAND, as indicated in Fig. 5b.

The inverters G1 and G2 of the uncommitted D-type of Fig. 3 may be used independently of the remaining gates thereof, as indicated in Fig. 6a, or combined by means of a suitable metallisation pattern to provide a two input NOR gate, as indicated in Fig. 6b.

The circuit diagram of Fig. 7 corresponds to the D-type block circuit diagrams of Figs. 2 and 3. The committed D-type configuration (Fig. 2) is obtained by including all of the links 41 to 71 (thickened lines) in the interconnection metallisation pattern for the gates, whereas the uncommitted D-type configuration (Fig. 3) is obtained by excluding all of the links 41 to 71.

The inverters G3 and G5 are arranged in a portion of the circuit of Fig. 7 labelled A'. The transistors in the portion A' in the uncommitted D-type version are capable of being interconnected in the arrangements shown in Fig. 4 by means of additional links F, G, H, J, K and L, shown by dotted lines, and in some cases use of one or more of the links which commit the portion A' to the form of the Dtype configuration. Fig. 8a shows the transistors of portion A' interconnected to form the two-input NAND gate of Fig. 4a. This requires the use of links L, K, H and J; links 64, 65, 66, 67, 68, 70 and 71 being omitted Fig.

8b shows the transistors of portion A' interconnected to form the two-input NOR of Fig.

4b. This requires the use of links G, F, L and 71; links 60, 61, 62, 64, 65, 66, 67, 68, 69 and 70 being omitted. Similarly Fig. 8c shows the transistors of gate G5 intercon nected to form the inverter of Fig. 4c. This requires the use of links L, H and 71; links 61, 62, 64, 65, 66, 67, 68, 69 and 70 being omitted. In Figs. 8a, band cthe input lines for terminals 17 and 18, where appropriate, have also been shown extended and redirected to facilitate interconnection to other circuit elements, in different islands, for example.

The NAND gates G8 and G9 are arranged in portion B' of the circuit of Fig. 7. The transistors in this portion B' are capable of being interconnected, otherwise than to form part of the D-type, in the arrangements of Figs. 9a and 9b by means of additional links C, D and E, shown by dotted lines, and the use of one or more of the links which commit the portion B' to the form of the D-type configuration. Fig. 9a shows the transistors of portion B' interconnected to form the two two input NAND gates of Fig. 5a. This requires the use of links E, 48, 49, 54 and 63; with links 44, 50, 51, 52, 53, 55, 56, 57, 58 and 59 being omitted. Fig. 9b shows the transistors of portion B' interconnected to form the four input NAND gate of Fig. 5b.

This requires the use of links C, D, E and 63; links 44, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57 and 58 being omitted.

The inverters G1 and G2 are arranged in portion C' of the circuit of Fig. 7. The transistors in this portion C' are capable of being interconnected, otherwise than to form part of the D-type, in the arrangements of Figs. 1 Oa and 1 Ob by means of some of the D-type committing links or by means of additional links A and B, shown by dotted lines. Fig.

1 Oa shows the transistors of portion C' interconnected to provide the two inverters of Fig.

6a. This requires the use of links 41 and 45; links 42, 43, 44, 46 and 47 being omitted.

Fig. 1 Ob shows the transistors of portion C' interconnected to provide the two-input NOR gate of Fig. 6b. This requires the use of links A A and B: links 41, 42, 43, 44, 45, 46 and 47 being omitted.

Each set 30 of islands, which sets are repeated a number of times over the chip surface area, thus comprises a first island providing a specific logic function or functions (specific function committed island) and thus having a high density of transistors per unit area; a second island comprising an uncommitted version of the specific logic function or functions of the first island, and such that the specific logic function or functions can be but need not be provided, since lower complexity logic functions, for example, may be obtained by suitable interconnection of constituent transistors of the second island (specific function uncommitted island); and a third island comprising an uncommitted transistor array in which pluralities of transistors are arranged and from which it is generally only required to obtain lower complexity logic functions by suitable interconnection thereof (transistor array uncommitted island). The third island has a low density of transistors per unit area for high flexibility of interconnection possibilities, whereas the second island has a transistor density intermediate that of the first and third islands. On the overall chip the transistor density thus achieved approaches that of a fully customised integrated circuit for a particular application whilst maintaining a degree of flexibility. Examples of the actual transistor layouts in the islands 32 and 33 on an integrated circuit are not shown. There are, however, many practical possibilities, as will be apparent to the man skilled in the art.

Using the transistor array of our co-pending Application No. 821 5940 (Serial No.

) (D.J.Rogers 1) for the third (largest islands) it is possible to provide an integrated circuit with a ratio of one D-type to four gates without requiring huge chips and thus keeping the unit price down. Previously the ratio was one D-type to six to eight gates.

Whilst the invention has been specifically described with respect to committed and un committed D-type bistables for the specific functions, it is not so limited and other circuits in committed and uncommitted form may be similarly employed. Transistor arrays for the largest islands 34 may also be other than those described in the abovementioned copending application. In addition there may be two or more types of specific function in committed and uncommitted form on a single chip, if required. An uncommitted integrated circuit thus formed may be committed by means of an autorouting technique comprising applying a single layer metallisation pattern which serves to interconnect transistors within the cells (islands) and to interconnect the different cells via the overall bus structure to themselves and to the input/output buffer cells 38 as appropriate. The single metallisation layer may comprise a computerdesigned pattern, the computer having been programmed so that it knows where the islands are, which type of island is which, where the contact points are, what bus interconnect structure and power feed structure there is etc., so that it can then appropriately place the required functions o the chip from a description of a required circuit, committing uncommitted functions as appropriate, and determine the optimum interconnection pattern between them and determine the pattern for the necessary device committment.

Claims (10)

1. An integrated circuit chip adapted to be committed to provide a desired function in dependence on the configuration of an electrically-conductive interconnection pattern to be applied thereto, the chip including a plurality of transistor array cells of at least two types.

2. An integrated circuit chip as claimed in claim 1, wherein the transistor array cells are arranged in sets, at least one of the sets including a first cell pre-commited to a first logic function and a second cell comprising an uncommitted transistor array.

3. An integrated circuit chip as claimed in claim 2, wherein the at least one set further includes a third cell having the same number and type of transistors as the first cell, which third cell transistors may be interconnected, in dependence on the configuration of the electrically-conductive pattern, to provide a logic function equivalent to the first logic function, or one or more other logic functions.

4. An integrated circuit chip as claimed in claim 3, wherein the first logic function comprises a D-type bistable.

5. An integrated circuit chip as claimed in claim 2, wherein at least another one of the sets includes a respective first cell pre-committed to a second logic function and a respective second cell comprising an uncommitted transistor array.

6. An integrated circuit chip as claimed in claim 3 or claim 4, wherein the transistor density in the first cell is greater than the transistor density in the second cell, and wherein the transistor density in the second cell is greater than the transistor density in the third cell.

7. An integrated circuit chip as claimed in any one of claims 2 to 6, wherein in the at least one set there are a pair of cells of each type, which pairs of cells are arranged adjacent one another in respective cell pair islands of the chip.

8. An integrated circuit chip as claimed in claim 7, wherein the islands are separated from one another and input/output buffer cells therefo by respective interconnection corridors.

9. An integrated circuit chip substantially as herein described with reference to and as illustrated in Fig. 1, with or without reference to Figs. 2 to 1 0a and 1 Ob, of the accompanying drawings.

10. An integrated circuit including a committed integrated circuit chip formed by the application of an electrically-conductive interconnection pattern to an integrated circuit chip as claimed in any one of the preceding claims.