GB2035688A - A multi-function large scale integrated circuit - Google Patents

Abstract

In a multi-function LSI circuit comprising a number of transistors formed in three circuit regions, the circuit elements in a first region are capable of being interconnected in a number of different ways to define different circuit functions, and the circuits in the three regions are also capable of being interconnected in different ways.

Description

SPECIFICATION Improvements in and relating to logic circuits Background of the invention This invention relates to logic circuits and more particularly to logic circuits adapted more readily to a wide range of specific functions and realizable as large scale integrated circuits.

Over the past several decades the trend in logic network design in computers has been toward the utilization of integrated circuits (IC's) with more and more logic functions on a given IC chip. What began as circuits of discrete components proceeded to networks of small scale integrated (SSl) circuits, medium scale integrated (MSI) circuits and ultimately to so called large scale integrated (LSI) circuits and very large scale integrated (VLSl) circuits. Each step upward has decreased the parts count, eliminated interconnections, and the delays and fabrication expenses related thereto in digital equipment and also in general, simplified the entire logic design process.

With MSI and especially SSI, when there was a need for more complex interconnections to realize a given logicfunction and where more complex functions were required, more logic gates were coupled together; and whereas coupling more and more gates together allows one to realize any desired logic function, performance is degraded and complexity increased. These factors result in increased network costs which, in general, are proportional to parts count and interconnect complexity.

Obviously, "off-the-shelf" integrated circuits are available and can be employed for a great number of the more commonly encountered "small" logic functions and a very few LSI functions, such as memories.

In the past, elaborate procedures and rules have been employed for determining the manner and means of connecting gates or IC's so that the minimum number of gates or IC's are used to do a given job. These methods include the use of such tools as Karnaugh mapping, Boolean algebra, and other related techniques. With the trend, however, to using large scale integrated parts, these techniques have become less important at the macroscopic network design level. It is now possible to select a large scale integrated circuit function from a catalog of a number of such circuits and through specification "customize" itto realize any of a wide number of functions. Then, finished LSI parts can be used or applied in a simplified circuit. Thus, this step of "customizing" LSI parts becomes important in simplifying logical design techniques for large digital networks.

With specialized gate arrays, customizing an LSI part can be effected through selection of all functions from a catalog and specification of cell on-chip interconnection.

This technique saves both time and money, since one LSi chip can, through judicious "customizing" perform the function of a number of prior art parts.

In addition to the advantages inherent in the use of LSI parts in general, the use of multi-purpose LSI chips has other synergistic advantages. These include the cost and reliability improvements due to the wider use of fewer different parts. Also, if logically powerful cells are used on chip, LSI performance (speed) is improved.

Multi-purpose LSI gate arrays with substantially fixed diffusion patterns and discretionary metal interconnect patterns have been previously developed. In most cases these arrays are composed of small scale integrated logic circuits such as ANDgates and OR-gates (or in TTL technology, NANDgates). These arrays are used to reduce the cost of developing a family of functionally different parts by requiring only the design of new metal interconnect patterns for each part.However, it is generally recognized that a part built using a gate array requires greater integrated circuit die silicon area than would be required by a functionally identical part which is laid out as a custom integrated circuit It is an object of the present invention to provide a high-degree of functional flexibility in a multipurpose LSI array while at the same time conserving the die silicon area.

One example of a prior art logic array can be found in U. S. Patent No. 3,808,475, which issued to F. K.

Buelow, et al., on April 30, 1974. This patent described an array composed of a plurality of cells made up of current-switch and emitter-follower circuits. These individual circuits are well-known and in common usage in the Emitter Coupled Logic (ECL) family. With the LSI device of this patent and with other known multi-purpose LSI arrays each cell contains but a small number of basic gates. Thus, to "customize" a given logic function with such logic arrays, a great many intercell interconnects are required. Other disadvantages which accrue with such arrays include lower speed and greater power requirements.

It is another object of the present invention to provide a protean logic circuit which comprises the basic cell of a LSI logic array.

Recent attempts to improve the flexibility of LSI digital arrays have been reported in the literature.

See, for example, a brief description in the /SSCC Digest of Technical Papers, entitled "A Master Slice LSI for Sub-nanosecond Random Logic" by Walter Braeckelmann, et al., Pages 108, 109, and 242, 17 February 1977.

A second LSI array of cascode circuits is described in the 1977 Government Microcircuit Applications Conference Digest of Technical Papers, in a paper entitled "A Flexible Sub-nanosecond ECL Gate Array" by J. I. Raffel, et al. The above-cited arrays, while offering advantages not enjoyed by the arrays composed of basic gates still fall short of the performance which should be obtainable because only a small catalog of cell functions can be performed.

It is a further object of the present invention to provide a logic circuit which, when completed by discretionary interconnection means, can alterna tivelyfunction as a wide range of flip-flops, a universal logic gate or as a plurality of further programmable independent current-switches.

It is yet another object of the present invention to provide a protean emitter-coupled logic circuit and a set of discretionary interconnection means wherein a first subset of discretionary interconnection means is used to determine the primary circuit function and a second subset of discretionary interconnection means is used to further define its specific circuit functions.

It is still another object of the present invention to provide a multi-function LSI array comprised of a plurality of cells utilizing such logic circuits.

Summary of the invention In keeping with the principles of the present invention the above objects are accomplished by the selection and layout of a minimal number of transistor gates, current switches and associated passive linear and non-linear circuit components. The array, henceforth referred to as the Universal Digital Array (UDA), is composed of a plurality of so-called Universal Digital Cells (UDC) plus separate currentswitch cells, large output emitter-follower transistors and other components which may be incorporated into a large scale integrated (LSI) circuit. Each of the UDC's in turn, comprises a specific set of elements and specific discretionary connections which are used to program the UDC's function and operation.

Although the UDC may be used itself as a single integrated circuit it is more conveniently and more commonly used in the LSI array with other UDC's and other current-switch elements.

A protean UDC can be discretionarily interconnected to form any one of three diverse classes of basic ECL circuits. Again, these circuits are flip-flops triple current-switch networks and a two-level seriesgates Universal Logic Gate such as that disclosed in U. S. Patent No. 3,925,684. A second set of discretionary connections further defined more specific logic functions of each of the basic circuit classes.

Such secondary discretionary interconnections, for example, can be employed to define the types and number of input and outputs or if desired, other sequential or combinational alternatives.

Brief description of the drawings In order that the invention may be clearly understood and readily carried into effect, it will now be described with reference by way of example to the accompanying drawings, wherein like reference numerals refer to like elements and in which: Figure 1 is a simplified plan view of a large scale integrated (LSI) circuit representing a Universal Digital Array of the present invention; Figure 2 is a detailed schematic diagram of a protean Universal Digital Cell in accordance with the present invention; Figure 3a is a schematic representation of a peripheral current-switch utilized in the UDA of Figure 1; Figure 36 is the logic symbol representation of the circuit of Figure 3a;; Figure 4 is a table depicting the various classes of basic logic circuits and optional variations which can be realized in accordance with the present invention Figure is a simplified schematic representation of the protean UDC of Figure 2; Figure 6 is a simplified schematic diagram of the UDC showing first level discretionary interconnections for realizing a basic flip-flop logic circuit; Figures 7, 8, 9, 10, 11 and 12 are logic diagrams illustrating the optional circuit variations obtainable with the basic flip-flop of Figure 6; Figure 13 is a simplified schematic representation of an implementation of a portion of the optional circuit of Figure 12; Figure 14 is a simplified schematic representation of the UDC of Figure 5 with partial discretionary interconnections for realizing a triple current-switch logic circuit;; Figure 15 is a logic diagram illustrating the output interconnect area and load cell utilization ofthetriple current-switch implementation of Figure 14; Figures 16a, 166 and 16c jointly depict the various combinations of load cell interconnections available with the logic circuits of Figure 15; Figure 17 is a simplified schematic representation of the UDC with primary and secondary discretionary interconnections for implementing an exempliary Universal Logic Gate embodiment; Figure 18 is a logic diagram illustrating the ULG embodiment realized by the secondary discretionary interconnects depiected in Figure 17; and Figure 19 is a logic diagram illustrating the ULG embodiment of Figure 17 in an alternative logic representation.

Description ofthe preferred embodiments Referring more specifically to the drawings, there is shown in Figure 1 a greatly simplified plan view of a large scale integrated (LSI) circuit representing a Universal Digital Array (UDA) of the present invention. The large square outline 100 represents the semiconductor substrate. Within the general semiconductor substrate there is shown in dashed line a plurality of smaller squares identified U1, U2, U3...U36. These squares represent regions or cells within the Universal Digital Array. Each of the cells U1-U36 is conveniently termed a Universal Digital Cell. With differences which are to be described in greater detail hereinbelow, each of the UDC's are substantially identical.Also as will be described in greater detail hereinbelow, it is as a result of the discretionary interconnection steps that the UDA becomes a "customized" LSI chip. It is understood, of course, that the 36-cell UDA configuration of Figure 1 is merely illustrative. Typical UDA's can comprise any useful and feasible number of UDC's.

Returning to the description of the simplified UDA of Figure 1, an upper region 101 and lower region 102 located adjacent to the UDC's are provided for auxiliary circuit elements to be described hereinbelow. These auxiliary circuits are not associated initially with any particular UDC. Finally, a plurality of pads 103 are shown spaced completely around the periphery of the Universal Digital Array. These pads are conductive regions provided to facilitate the connection of DC power and signal voltages to and from the UDA. Input pull down pinch resistors 104 are located adjacent to selected pads.

The Universal Digital Array (UDA), of the present invention thus comprises a plurality of Universal Digital Cells (described in Figure 2); plus separate current-switch cells (as depicted in Figures 3a and 3b) and a number of so-called large output emitterfollower transistors all incorporated in a large scale integrated circuit. The UDC itself is a particular set of circuit elements which with certain specific discretionary interconnections is selectively programmed in both its function and operation. As previously indicated, the UDC can be used by itself as a single integrated circuit, but is more conveniently employed in an LSI array such as the UDA.

The protean UDC can be discretionarily connected to implement any of three basic classes of prototype ECL circuits. These are flip-flops, triple currentswitches and two-level series gated Universal Logic Gate (ULG). These basic prototype circuits are realized with the UDA die of Figure 1 by means of a first selected subset of two-layer metalization pattern interconnecting portions of the protean circuits within themselves, with others, and with auxiliary circuits on the periphery of the chip. Separate species of each of the prototype circuits are further realized by a secondary subset of interconnections which may either be a part of the first or second layer metalization or a combination of both. In any event, the particular implementation of the prototype circuit or specific species thereof will be realizable with no more than two layers of metalization on the basic UDA.

Referring now to Figure 2 there is shown in schematic diagram form the protean Universal Digital Cell (UDC). The UDC is comprised of a bias circuit plus transistors and resistors which are used for different purposes in each of the three primary or prototype cell configurations depending upon subsequent interconnection. A representative bias circuit is shown with most of its elements interconnected within dotted block 200 at the bottom of Figure 2. With one minor exception for masterislave flip-flop applications to be described hereinbelow, the bias portion 200 of the circuit of Figure 2 remains the same regardless of the specific cell option.

A single voltage divider, comprising resistors R24, R23, R19, R18, R28, and diodes CR4 and CR5, is shared by two adjacent cells (i.e. U1 and U2 or U3 or U4, etc. of Figure 1). The voltages generated by the bias network are buffered for use in each cell through additional bias network elements. These include Q23, the emitter outputs of which provide clamping voltages for setting the logic levels in certain applications involving specific WIRE-AND outputs. Also, buffered reference voltages VR1 and VR2M are provided at the emitter of Q24 and at the collector of transistor Q7 respectively. An additional buffered referenced voltage VR2S can be obtained at the collector of transistor 07.With selective connection of resistor R12 another reference voltage can be obtained at the emitter of transistor 07 for setting the current value of the current sources of the UDC's to be discussed hereinbelow. Again, it is to be emphasized that the bias circuit 200 shown in Figure 2 is merely exempliary and that other bias sources differing in design can be readily devised. Alternative bias sources can be shared by a number of UDC's according to design choice.

Also shown in Figure 2 are three load transistors 016, Q17 and Q18 and associated load resistors R20, R21 and R22. In the protean circuits the collectors of each of the transistors 016,017,018, Q23 and 024 and one end of resistors R20-R23 are connected to a primary voltage source Vcc. The load transistors and load resistors taken together can be characterized as the load cell portion of the UDC.

Shown just below the load cell region of Figure 2 are a plurality of transistors some of which are interconnected to provide parallel current paths.

Transistors 03, Q4, Q5 and Q6 are connected in a so-called quad-OR multi-base configuration. Likewise transistors Q19, Q20, 021 and Q22 form a quad-OR multi-base transistor. Transistors 011 and Q12 and Q13 and Q14 each form a dual-OR multi base transistor. Transistors Q1 and Q15 are shown unconnected in the protean UDC.

Transistors Q2 and Q8 are depicted on the next lower level of the protean circuit with the collector of transistor Q2 being connected through a pinch resistor R9 to common potential source VEE. The emitter of transistor 02 is connected to the collector of 01. Transistor 08, as shown in Figure 2, is unconnected although a second pinch resistor R10 is provided for use as will be described hereinbelow.

Transistor Q1 connected between the emitter of transistor 02 and common potential VEE generally serves as a current source in those specific applications requiring a current source between the emitter of transistors 02 and Q8 and ground.

The use of pinch resistors such as resistors R9 and R10 for cascode node idle current injection follows the teachings of U.S. Patent No. 3,925,691. Basically, idle current injection is adventageously employed in the flip-flop and ULG implementations of the UDC to speed circuit operation.

Also provided in the protean UDC are resistors R6, R7, R8 and R14 each of which having one terminal thereof connected to VEE. Diode CR1 and resistors R3 and R4 are also shown in Figure 2 unconnected except for the end of resistor R4 connected to VEE.

This combination of components is employed, as needed, in specific embodiments for shifting certain voltage levels as will be described hereinbelow.

Referring now to Figures 3a and 3b there is shown a schematic diagram and logic diagram respectively of a so-called peripheral or auxiliary current-switch cell. A plurality of such current-switch cells are located in the upper and lower regions 101 and 102 of the UDA shown in Figure 1. Depending upon the specific interconnection employed, peripheral current-switches may be WIRE-AND orWIRE-OR connected with UDC current-switches or cascode circuits also as will be explained hereinbelow.

As shown, the circuit of Figure 3a includes a bias circuit for creating a reference voltage VR1. Many similar bias circuits may be used. The one shown in Figure 3a is an illustrative example. The reference voltage VR1 is coupled to the base of a first transistor of a current-switch pair. The other transistor of the pair is depicted as a quad-OR transistor whose multiple base inputs can be utilized if desired by implementing the optional common emitter connection. The circuit also includes load resistors RL and emitter-follower transistors QL which can be connected in various combinations for specific output configurations. Pulldown resistors Rp are also provided for use at the inputs.

As in the case of the UDC of Figure 2, the few interconnections needed to configure the peripheral current-switch of Figure 3a are made by means of the two layer metalization pattern in the LSI fabrication process. When configured as a multiple-input current-switch the logic diagram of the circuit is as shown in Figure 3b with four inputs and complementary outputs.

In Figure 4 there is shown a table describing the various prototype and optional circuits which can be realized with each of the Universal Digital Cells within the Universal Digital Array. The protean Universal Digital Cell is represented by the top box.

Three basic circuit types which may be formed using the UDC cells are designated in the next level of Figure 4. These are flip-flops, current-switches, and two-level cascode series gates cells. It is noted that the flip-flop. although only regarded as one basic type, can be configured for either master or slave operation. Also, when current-switches are configured, three separate and independent currentswitch emitter-followers are obtained. The more complex logic functions are realized using the primary discretionary connections to implement the Universal Logic Gate (ULG) cascode cells.

Each of the basic circuit types may be further defined by selectively executing the secondary discretionary interconnections to obtain the numerous specific optional circuits listed in Figure 4. Although the various optional circuits realized by the secondary set of discretionary interconnections will be described in greater detail individually, they can be considered as falling into one of two general catagories. The first catagory of optional circuit concerns options for sequential operation while the second concerns those for asynchronous or combinational operation.

The various optional connections specific to sequential operations are depicted in the lower lefthand box of Figure 4. Basically, these options comprise the possibilities of: 1. Providing multiple (OR-connected single ended inputs for clock and data inputs 2. Implementing a differential input for either clock or data.

3. Realizing asynchronous jam set and reset inputs which allow forcing the flip-flop state between clocktransistion.

4. Filtering the clock and level shifting 5. Buffering and level shifting the clock for distribution to sequential circuits elsewhere on the Universal Digital Array The combinational options are highlighted in the remaining boxes of Figure 4.

In general, multiple OR-inputs are available through use of the multi-base input transistors.

Hardware-free or power-free logic functions can be generated at the UDC outputs through the use of WIRE-AND and WIRE-OR connections. Load cells are provided with available options including voltage clamps for use in multi-cell WIRE-AND connections; load resistors for conversion of output current to ECL-level voltages; and emitter-followers for level shifting and buffering the output signals to insure adequate drive for subsequent states. Off-chip outputs are implemented through connection of a load cell resistor to a large output emitter-followertransistor. An output emitter-follower can be connected instead of one of the internal-emitter followers associated with the individual Universal Digital Cell or if desired, both internal and external emitterfollowers can be connected in parallel.

As indicted hereinabove, these various options are realized by executing the secondary set of discretionary connections. The various options will be described individually.

Turning now to Figure 5, there is shown a simplified schematic representation of the protean UDC which has been redrawn in a way which facilitates the description of the discretionary connections necessary to realize the various primary circuits and the optional species thereof. In Figure 5 the bias circuit has been replaced by voltage generators VCLAMP, VR1 VR2M and VR2S. Clamping transistor 023, not actually a part of the bias circuit, has been retained and carried over to Figure 5 from Figure 2. Where appropriate, reference numerals from Figure 2 have been carried over to Figure 5 to designate like circuit elements. The multiple-base transistors Q3-Q6, 019-022 and Q11 -Q14 are shown in Figure 5 as simple transistors Q3', Q19' and 011'.

The omission of the multiple-OR inputs is for the sake of simplicity only and it is understood that plural inputs are, in general, anticipated to these multiple base transistors and, in fact, are necessary to realize some of the optional circuits described hereinafter. Also in Figure 5, transistor 01 has been redrawn as a current source 150. Pinch resistors R9 and R10 have been omitted as have the various pull down resistors. Itis understood howeverthatthese components are employed and their omission from the simplified schematic diagram of Figure 5 is purely for the sake of facilitating the operational description thereof.

In Figure 5 the terminals representing the various discretionary connections are shown arbitrarily separated into one of three inteconnection areas.

These interconnection areas are depicted by the broken lines boxes and are labeled Area "A", Area "B" and Area "C". The arbitrary designation of these areas is again forthe sake of facilitating the description to follow. In general, however, the input and clock connections are made to terminals within Area "A", whereas output connections are made by means of terminals within Area "B".

The various interconnection terminals within each of the interconnection areas are also numbered to aide in the descriptions to follow. The terminals in Area "A" are numbered consecutively from 1 to 13; those in Area "B" from 20 to 41 and those in Area "C" from 50 to 61.

For the sake of the operational description to follow, it is convenient to think of the Universal Digital Cell as composed of a discrete circuit ele menus with interconnections which can be made by means of wired bridges. In practice, however, the Universal Digital Cell is preferably realized as part of a Universal Digital Array and the interconnections are by selective metalization patterns are deposited on a semiconductor substrate.

In any event, the basic flip-flop circuit can be realized with the protean UDC circuit of Figure 5 by modifying it in a manner depicted in Figure 6. Again, where appropriate, like reference numerals have been carried over from Figure 2 and Figure 5 to designate alike structural elements. To realize the flip-flop of Figure 6 the following interconnections are made in Area "A". First, the clock input CLK is applied to the base of transistor Q3' by means of terminal 1. The data input labeled DATA is applied to the base of transistor Q11 ' through terminal 2. The level shift stage is completed by interconnecting terminals 7-8,9-10 and 11-12 in Area "A" thereby serially connecting diode CR1 and resistors R3 and R4. The reference voltage VR1 is applied to the base of transistor 010' by completing the interconnection between terminals 5-6.

Transistors Q2 and 08 are connected by means of the selective interconnection terminals in Area "C" as a lower current switch pair. That is, the emitters of transistors 02 and 08 are connected together and the common mode connected to current source 150.

The collectors of transistors Q2 and Q8 are connected respectively to the common nodes of upper current switch pairs formed by Q11 ' and 010' and Q15' and Q19'. The reference voltage to the base of transistor Q8 of the lower current switch pair is connected by means of terminal 54 to either VR2M or VR2S for master or slave flip-flop operation as indicated by the dotted line convention.

In interconnection Area "B" the collector of clock input transistor Q3' is connected to VCC. The transistors of the upper current switch pair are cross-coupled in the manner of a flip-flop with collectors of Q11' and 015' being connected to the input of a load cell, for example, formed by load transistors Q16 and load resistor R20. The output of load cell 016 comprising the 0 output of the flip-flop is connected through R7 to VEE and also to the base of transistor 01 9'. The collectors oftransistors 010' and Q19' are connected together and to the load cell made up of transistor Q18 and resistor R22.The emitter output of load transistor 018 comprises the 0 output of the flip-flop and in a manner similar to the other load cell is connected through R6 to VEE and cross-coupled to the base of transistor R15'. The particular load cell connections depicted in Figure 6 are representative but not unique or limiting. Other equivalent connections of upper current-switch transistors-to-load cells may be implemented in the UDC to form functionally identical flip-flops.

The flip-flop of Figure 6 is thus configured through the first of the primary interconnection options. It functions as a level triggered D latch with data and clock input and Q and Q outputs. The basic latch in the flip-flop is formed by transistors 015' and 019' which are cross-coupled through the emitterfollower load transistors Q16-and 018. Latch operation is illustrated for a master latch configuration with the base of transistor Q8 being connected to voltage source VR2M by means ofterminals 54 and 56.

Referring now to Figure 7 there is shown a logic diagram of the basic flip-flop of Figure 6 and its associated input gates and level shift circuit. In Figure 7 the flip-flop is indicated by block 170 with both D and D inputs and Q and Q outputs. The voltages VR1 and VR2 are available at terminals at the bottom of block 170 as are the clock CLK and CLK inputs. The two quad-input OR-gates 171 and 172 are indicative of the multi-base transistors 03 through Q5 (03') and Q11 through 014(011'). In the basic embodiment of Figure 6 only one data input and one clock input are shown. In the logic diagram of Figure 7 the CLK input to flip-flop 170 actually conforms to the level shifted or LS input. In Figure 6 this corresponds to interconnected terminals 9-10 in Area "A".As indicated in Figure 6 a level shifted clock output is available to drive additional stages, if desired.

Also as shown in Figure 7 reference voltage VR1 is connected to the D input of flip-flop 170. This corresponds to the connection (5-6) between VR1 and the base of Q10' in Figure 6. Also, the reference voltage VR2 is shown connected to the clock CLK input. This corresponds with the interconnection of this reference voltage to the base of transistor 08. As previously noted, the reference voltage VR2 may be either one of two separate levels which levels may vary by approximately 100 milivolts for ECL circuitry.

The slight difference between the two reference voltage levels VR2M and VR2S is required for master or slave operation.

As noted from the table of Figure 4, a plurality of options are available with the prototype flip-flop circuit of Figures 6 and 7. The selective utilization of secondary discretionary interconnections to implement the options are depicted in greater detail in the logic diagrams of Figures 8 through 13. These options can be described also with additional reference to the schematic diagrams of Figures 2, 3a and 6. The first three options depicted in the table of Figure 4 in connection with the flip-flop prototype circuit are the options implementing multiple parallel outputs, multiple clock OR-inputs, and multiple data OR-inputs. These options are illustrated in the logic diagram of Figure 8, a portion of which is shown schematically.

In Figure 8 the multiple parallel outputs are indicated by emitter-follower transistors 180 and 181 having their respective bases connected to the 0 output of flip-flop 170 and their collectors connected to voltage source VCC. Parallel outputs are derived from the emitters of these transistors. Transistor 180, as shown, can comprise one of the loadtransistors of the UDC such as 017, a load transistor of a neighboring UDC in the Universal Digital Array, or one of the emitter4ollowers QL associated with the peripheral switches such as shown in Figure 3a.

Transistor 181 is shown as one of the large output transistors which, as mentioned above, are disposed on the top and bottom of the Universal Digital Array.

It is obvious, of course, that additional output transistors can be employed as needed and that other transistors can be utilized for multiple Q outputs if desired.

The first option allows the distribution of the latch output to other cells in the UDA through an additional internal emitter-follower. This configuration is used to increase the fan out of the flip-flop without greatly degrading regeneration time. Another use of this option is to provide parallel independent outputs for WIRE-OR connections. When WIRE-OR connections are used, direct access to the emitter of load transistor Q16 or the emitter of Q18 could cause unwanted data to be written into the latch because external signals would be connected to one of the latch regeneration loads. To prevent this, a second parallel emitter-follower is connected in accordance with this option to drive a WIRE-OR node.

The multiple-OR input options provide the capability of logical OR-gating flip-flop input signals without requiring additional power or significantly increasing delay. This capability is achieved through the use of additional input transistors--one for each signal to be included in the OR function--up to a maximum of four signal inputs. OR-input are achieved by connecting additional input lines to the bases of the quad-OR clock and data input transistors Q3' and 011' respectively. As mentioned hereinabove, these transistors Q3' and 011' are multi-base transistors having multiple base junctions available for OR-ing multiple inputs.These multiple base inputs have baen omitted from the schematic diagram of Figure 6 but are shown in Figure 8 as inputs to the fcur-input OR-gates 171 and 172 which drive the D input and clock level shift circuit 173, respectively.

Another option shown in the table of Figure 4 under the flip-flop prototype is the provision for jam set:reset operation. This option is shown in the logic diagram of Figure 9 wherein S and R inputs are drawn to the top of block 170. The S and R or set and reset inputs are made to OR-inputs to secondary bases of transistors 019' and Q15'.

The set"reset option provides asynchronous set and reset inputs to the flip-flop. The added transistors in this case, are in parallel with the basic flip-flop latch transistors and therefore can be used to override the normal latch operation. It is to be noted, however, that these asynchronous S and R inputs have no effect when the lower current switch composed of transistors QS and Q2 has switched the current from the latch to the data input currentswitch section composed of transistors Q11 ' and Q10'. Thus, the set and reset inputs are inoperative when the clock is low, in the case of the master flip-fiop and high in the case of the slave flip-flop.

Two further options shown in the table of Figure 4 provide for the use of differential signals on the data input and clock input, respectively. When these options are exercised markedly improved transient performance can be obtained. The improvement is not without penalty, however, in that it requires twice the number of signal routing lines used with the single-ended input options described above. It also precludes the use of logical-OR inputs which are otherwise available in connection with the multiple clock or multiple data inputs. The differential data input option is shown in the logic diagram of Figure 10. In Figure 10 the differential data is applied to the D ano D inputsano#Dinputs of flip-flop block 170. The multiple input-OR gate 171 is disconnected from the circuit.

This option is exercised by eliminating the interconnection between terminals 5-6, in Figure 6, and applying the differential data between the bases of transistors 011' and Q10'. That is, terminal 2 remains the D input and terminal 5 comprises the 5 input. In the case of the differential data input option Q11' and 010' are preferably implemented as singlebase transistors.

Also shown in Figure 10 is the level shifted clock input option. In accordance with operation under this option a level shifted clock such as derived from another stage on the UDA is applied to the CLK input of flip-flop 170. In this case, the clock input level has already been shifted to the logic level necessary to drive clock input transistor 02 and therefore the level shift circuit 173 and its input-OR gate 172 are not used. The option is exercised in Figure 6 by omitting the discretionary inteconnections between terminals 9-10 and 11-12; by providing the LS CLK signal input to terminal 9.

The use of a differential clock is depicted in this logic diagram of Figure 11. In Figure 11 a differential clock which has been level shifted is shown being applied to the CLK and CLK inputs of flip-flop 170. As mentioned hereinabove, when this option is exercised, the level shift circuit 173 and multiple input OR gate 172 are not used. Again, this option is exercised in Figure 6 by applying the differential clock signal to the bases of transistors Q2 and Q8.

This is done by means of terminals 9 and 54 in Areas "A" and "C", respectively. When this interconnect option is exercised, the LS voltage divider chain is not implemented and the reference voltage input VR2 is not connected.

The remaining flip-flop option depicted in the table of Figure 4 is shown in the logic diagram of Figure 12 and in more detail in the schematic diagram of Figure 13. In Figure 12 a low-pass filter 175 is shown connected in series with one of the clock inputs to quad-OR gate 172. The purpose of the low-pass filter is to slow the rise time of clock pulses which in some cases are too fast. The low-pass filter 175 is shown as a simple RC network with the resistor in series with the external clock and capacitor from the resistor to VEE. In practice such a low-pass filter is readily realized on the Universal Digital Array by application of the circuit shown in Figure 14. In Figure 14 a load resistor Rv which is available on the UDA provides the resistive portion of the filter. The capacitance is provided by the junction capacitance of a large on-chip output emitter-follower transistor 195 which has its collector and emitter junction interconnected and connected to one end of resistor RL. Specifically, the base of transistor 195 is connected to VEE with the combined collector-base and emitter-base junction capacitances providing the necessary capacitance for the low-pass filter.

In general, operation of the UDC in a master-slave flip-flop configuration is straight-forward. As mentioned hereinabove, a master flip-flop tracks input data when the clock is low. When the clock changes from low to high, new input data is captured in the master latch and held as long as the clock remains high. Because lower current switch clock inputs are reversed in the slave, the input differential pair (011', Q10') is active when the clock is high. When the clock is low, the latch feedback pair (015', 019') with emitter followers (016,018) regenerate and slave input data is captured.

A master-slave flip-flop is formed by connecting a master latch output to the D-input of a slave-latch and driving both latches with a common clock. The external data input is fed to the master; slave Q and Q outputs are used as the external outputs from the 2-latch network.

The 2-latch network operates in the following manner. When the clock is low the master latch upper current-switch input differential pair is active and tracks the external data input. Also when the clock is low the slave upper current switch feedback pair is active and holds previously input data.

As the clock rises, the master latch lower currentswitch transfers switch-current to the upper currentswitch feedback pair. This regenerates and stores the D input. As the clock rises further switch current is transferred by the slave lower current-switch. This makes the slave input upper current-switch active and simultaneously turns off the slave upper current-switch feedback pair. When this occurs the external input data state now held in the master is transferred through the slave to the external flip-flop outputs. At this point, as the slave latch releases, the outputs will change state if the new input data value differs from the value of data held previously in the slave.

While the clock is high the master latch remains locked up and thus freezes the data input to the slave. Therefore, even though the slave is not latched, its outputs are held fixed while the clock is high.

As the clock falls, the lower current-switch in the slave transfers switch current to the slave upper current-switch feedback pair. This latches data input from the master. Then as the clock falls further, the master lower current-switch transfers current from the master upper current-switch feedback pair to the active input pair. Thus the master latch releases and subsequently tracks the external D input.

The sequence in which the master locks up then the slave releases as the clock rises ensures that the output will change state only if the new data and the data stored previously have different logic values.

The inverse sequence, slave lockup then master release as the clock falls ensures that data stored in the master will be transferred to the slave and captured before the master releases to track the new D input.

As previously mentioned, the master-slave sequence relationships are caused by using different lower current-switch reference voltages VR2 in master and slave latches. VR2 used in a master is approximately 100 mV higher than VR2 used in a slave. These different VR2 values are generated by using slightly different connections in the bias circuit. Referring to Figure 2, the master option, resistors R1 3 and R1 2 are inserted between the VR1 node (the emitter of Q24) and the two level-shift diodes CR3 and CR2. With the typical bias circuit shown these resistors lower the voltage references VR2 fed to master latches. This lowers the threshold voltage at which the master changes from its data tracking mode to its hold mode. In the slave option resistor R12 is omitted so that VR2 fed to the slave is approximately 100 mV higher than VR2 fed to the master.The differences between the lower current switch reference voltages assures the master-slave sequence relationships, e.g., that on a falling clock edge, the slave latches before the master releases to acquire new data. (Again note that other bias circuits may be used providing options for connecting VRM and VR2S).

Still further optional connections allow the use of resistors R8 and R14 to sink currents from output emitter-followers. These are used for discharging interconnect and next stage input capacitances.

Turning now to the schematic diagram of Figure 14, there is shown the UDC together with the primary set of discretionary interconnections to realize the trip current-switch embodiment which is the second basic prototype configuration of the Universal Digital Cell. In general, the triple currentswitch is a circuit comprising three separate currentswitches, three load cells and the bias circuit. The classical ECL circuit, the so-called current-switch emitter-follower (CSEF) ORINOR gate is formed when two load cells are connected to a current switch. CSEF OR-gates and alternatively CSEF NORgates may be formed using only one load cell with a current-switch.

In the simplified schematic diagram of Figure 14, a preferred set of primary discretionary interconnections to realize a triple current-switch from the protean UDC is shown. For convenience, the three separate current-switch stages are designated X, Y and Z. In Area "A" the X-input is connected to terminal 2 and thereby to the base of multi-base transistor 011'. The Y input at terminal 3 is connected to the base of transistor 015' and the Z input at terminal 1 is connected to the base of transistor Q3'.With this combination, the transistor pairs comprising the X current-switch are transistors 011' and 010'; those comprising the Y current-switch are 015 and Q19' and those comprising the Z currentswitch pair are transistors 03' and 08. It is understood, of course, that this is only one possible combination which can be made to realize the triple current-switch. This pairing of transistors is accomplished by means of a minimal number of discretion- ary interconnections and is therefore illustrated in Figure 14.

Reference voltage VR1 is applied to the bases of transistors Q10' and Q19' by means of the discretionary connections 4-5-6 in Area "A". In Area "C" VR1 is also applied to the base of transistor 08. The emitters of the transistor pairs comprising each of the triple current-switches are tied to VEE each through its own resistor. In the case of the transistor pair 03', 08 resistor R3 is shown as forming this connection. A jumper from terminal 58 in Area "C" and to terminal 10 in interconnection Area "A" facilitates this connection. Also transistor pair 011' and Q10' utilize resistor R4 as indicated by the interconnection between terminal 50 in Area "C" and terminal 12 in Area "A". Transistor pair Q15' and Q19' are connected to VEE through resistor R14.

The collectors of the various transistor pairs comprising the triple current-switch are brought out in to Area "B". Forthe X current switch pairthe collectors are brought out to terminals 21 and 22; for the Y current-switch the collectors are brought out to terminals 24 and 25 and for the Z current-switch to terminals 20 and 53.

The remaining discretionary connections terminals of Area "B" in Figure 14 are not indicated as connected. In general, connections are made in Area "B" but the sake of clarity, the interconnections are more readily described in connection with Figures 15 and 16a, 16b, and 16c.

When the Universal Digital Cell (and therefore the Universal Digital Array) is designed to operate with standard ECL signal levels, current-switch common emitter node voltages range from approximately -1.7 volts to -2-1 volts. Thus, a substantially constant 3.3 volt level is impressed across the current-switch emitter resistors R3, R4 and R14 and an approximately constant switch-current is generated through each. The use of resistors to set switch-currents in the triple current-switch UDC configuration shown in Figure 14 simplifies intra-cell circuit connection patterns and makes available more metal routing space in the semiconductor chip for cell programming. It is noted, however, that active current source circuits may readily be employed in alternative UDC embodiments in which reduced signal levels are used.It is noted that active sources such as source 150 in Figure 5 are mandatory in the flip-flop prototype and specific circuits described hereinabove, and also in the cascode ULG configurations to be described hereinbelow. Twolevel series gating is used in those configurations and thus only a small voltage is available to set the switch-currents.

As described hereinabove in connection with Figures 6 through 13 the flip-flop connection options shown in the table of Figure 4 fall generally into three catagories. These are: (1) input options (e.g., for connecting multiple input transistors for input OR-gating), (2) output options (e.g., for connecting parallel emitter-followers for WIRE-OR gating) and (3) internal reconfiguration options (e.g., for adding jam/set-reset features, etc.). The situation is less complex in the triple current-switch and cascode UDC configurations. In both cases, the basic cell function is fixed and only input and output options are used to refine or program cell operation.

The current-switch options shown in Figure 4 include, for the most part, all those input output options available with the flip-flop prototype plus additional options as well. The input-OR options achieved by use of the multiple base transistors employed in the UDC and shown in Figure 2, of course are available and are used in the triple current-switch. The input transistors of each of the current-switch pairs comprise multi-base transistors in the arrangement shown. That is, input transistor 011', Q15' and Q3' comprising the input transistors of switches X, Y and Z all permit OR-ing of input signals.

The other current switch option provide for WIRE AND connection of two or more current-switch collector-nodes. This option may be used to connect current-switch collectors within a cell or from several cells, orto connect current-switch collectors with UDC cascode cell upper current-switch collectors.

A clamp circuit is required when two or more switched currents are fed through a common load resistor. The clamp voltage is provided by 023 by means of terminals 33 and 37 in interconnection Area "B". The clamp prevents more than about one switch current from flowing through the load resistor and thus controls collector and corresponding load cell output voltage excursions. If the clamp were not used, the collector node voltage could fall far enough to cause saturation of the current-switch transistors thereby slowing the circuit operation significantly. Another current-switch option provides for WIRE OR output connections (this was also provided in the flip-flop as an option). An implicit logical-OR function is performed when emitter-follower outputs are wired together, because each emitter-follower acts as a substantially ideal voltage source.Thus any emitter-follower can pull the common output node up to a high level making the output node high if any of the individual outputs is high.

Still another option permits connecting a collector node to a large output emitter-follower for driving an off-chip output. As in the corresponding flip-flop optional connection an internal emitter-follower may also be connected in parallel with a large emitterfollower if the output signal is to be fed to both on-chip and off-chip circuitry.

These various output options are more clearly appreciated with reference to Figure 15 and Figures 16a, and 16c. In Figure 15 the triple current switches X, Y and Z are shown as multiple input ORINOR gates. The output connections again correspond to the terminology of Figure 2 and Figure 14.

On the right side of Figure 16 are the elements of the load cell region of Figure 14. Box CL designates the clamp, box R designates load resistors and box EF designates the internal emitter-follower. The triple current-switch load cell logic diagram showing the load cell connection options is shown in Figures 16a, 16band 16c. Again, the same designationsforthe individual load cells are carried over from Figure 15.

In Figure 16a the various optional interconnections are designated a, b, and with a designating an interconnection between the base of an internal emitter-follower to the load resistor; b representing an interconnection between the clamp voltage and the load resistor and c representing clamp load resistor to emitter-follower base interconnection.

These interconnections are also shown by the dotted line convention in Figure 16b.

The remaining set of primary discretionary interconnections indicated in the table of Figure 4 implements a two-level series-gated Universal Logic Gate (ULG) cascode circuit of the type defined in U.

S. Patent No. 3,925,684. The schematic diagram of the Universal Logic Gate is shown in Figure 17. In Figure 17 the primary discretionary interconnections in Area "C" are substantially the same as for the flip-flop of Figure 6. The collectors of transistors Q2 and 08 are connected to the common emitter nodes of transistors 011' and 010' and 015' and Q19', respectively. Also the base of transistor 08 is connected to reference voltage VR2M. The emitters of transistors Q2 and Q8 are tied together and connected to current source 150. In interconnection Area "A" the level shift circuit is implemented as before by tying the emitter of transistor Q3' and diode CR1 and resistors R3 and R4 in a series circuit to VEE. The X-input is applied to transistor 011' by means of terminal 2.The Y-input is applied to the base of transistor Q19' and the Z-input is tied to the base of transistor 03' through terminals 4 and 1, respectively. Reference voltage VR1 is applied not only to the base of transistor Q10' but by virtue of interconnection 3-5-6 in Area "A", to the base of transistor Q15'.

In interconnection Area "B" the optional outputs are selected by first tying the collector of transistor Q3' to VCC and by implementing the load cell connections between the base of load transistor 016 and its corresponding load resistor R20 and connecting this node to the common node formed by the collectors of transistor 011' and 019'. The base of transistor Q17 is connected to load resistor R21 and this node tied to the common node formed by the collectors of transistor Q10' and 015'. The two outputs of the ULG are taken from the emitters of the two aforementioned load transistors Q16 and 017.

These outputs are designed f, f.

The operation of the ULG is described in great detail in U.S. Patent No. 3,925,684 which issued on December 9, 1975 to J.R. Gaskill, Jr. and D.C.

Devendorf. The particular output interconnection depicted in Figure 17 (and Figures 18 and 19, below) represent only one specific logic function of the hundreds which are available with the ULG.

For the sake of clarity it is preferrable to use logic diagrams instead of schematic diagrams, such as Figure 17, to describe the ULG and its discretionary interconnections. A ULG can be depicted by a cascode gate equivalent logic diagram such as Figure 18, or as a cascode cell equivalent logic element such as Figure 19. Both Figures 18 and 19 represent a ULG interconnected to perform the function of the ULG of Figure 17.

In Figure 18 the gate equivalent logic diagram comprises a two-input OR NOR gate 300 having its inputs fed by the respective outputs of two two-input AND gates 301 and 302. The inputs of AND gate 301 are taken from the output of the X-input OR gate 303 and the output of the Z-input OR gate 304. The inputs of AND gate 302, on the other hand, are derived from the output of the Y-input OR gate 305 and the complemented output of gate 304.

The output of gate equivalent circuit VBD and VAC are given by the expressions: V50=XZ+Yz [ Eq. 1 ] VAC=XZ+YZ, [ Eq.2 ] Where, X, Y and Z represent the logical-OR of the multiple X, Y and z inputs and X, Y, and Z, of course, are the logical complements thereof.

To more closely tie the teachings of the aboveidentified Patent No. 3,925,684 with the teachings of the present invention, the cascode cell equivalent logic diagram of Figure 19 is included. The logic diagram of Figure 19, as mentioned above, is an alternative representation of the ULG implementation of Figure 17. This ULG representation can be used to advantage with some of the more complex ULG or multiple-ULG functions. In Figure 19, block 310 represents the portion of the Universal Logic Gate implementation with interconnections to load cells 311 and 312 being shown externally.

As mentioned hereinabove, the specific discretion- ary interconnections shown in Figure 17, 18 and 19 represent only one of the several hundred possible configurations of the ULG. These configurations are described in exhaustive detail in the abovementioned Patent 3,925,684.

The various options depicted in the table of Figure 4 are also similar to those described in connection with the previous flip-flop and triple current-switch configurations. In general, multiple-OR inputs are allowed by virtue of the multiple base transistors as previously described and as shown in the more detailed UDC schematic diagram of Figure 2. Level shifted or non-level shifted Z-input options are available by virtue of the level shifting circuit comprising transistors 03', diode CR1 and resistors R3 and R4. The level shifting circuit is similar in operation to the aforementioned level shifted clock circuit of the flip-flop.

In all cases, it is understood that the abovedescribed arrangements are merely illustrative of but a few of the many possible specific embodiments which can represent applications of the principles of the present invention. Numerous and varied other arrangements can be readily devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention.

Claims (12)

1. A multi-function large scale integrated (LSI) array comprising, in combination, a semiconductor body, said semiconductor body having a planarsurface; said semiconductor body being divided into a plurality of first, second, and third regions; a first plurality of transistors formed in the semiconductor body in each of said first regions to define a Universal Digital Cell, each of said Universal Digital Cells including at least a load cell region and a current-switch region; a second plurality of transistors formed in the semiconductor body in each of said second regions to define peripheral current-switch circuits, each of said peripheral current-switch circuits including at least a load cell region and a current-switch region; a third plurality of transistors formed in the semiconductor body in each of said third regions;; first discretionary interconnection means for interconnecting portions of said first regions to define the primary circuit functions of said Universal Digital Cells; and second discretionary interconnection means for interconnecting portions of said first, second and third regions to define the secondary circuitfunctions of said Universal Digital Cells.

2. The LSI array accoding to claim 1 wherein the primary circuit function of at least one of said Universal Digital Cells is defined as a flip-flop

3. The LSI array according to claim 1 wherein the primary circuit function of at least one of said Universal Digital Cells is defined as a multiple independent current-switch.

4. The LSI array according to claim 1 wherein the primary circuit function of at least one of said Universal Digital Cells is defined as a two-level series-gated Universal Logic Gate.

5. The LSI array according to claim 1 wherein at least some of said Universal Digital Cells additionally include a bias supply region.

6. The LSI array according to claim 1 wherein at least some of said peripheral current-switch circuits additionally include a bias supply region.

7. The LSI array according to claim 1 wherein said first discretionary interconnection means comprises a first selected subset of a two-layer metalization pattern on the planar surface of said semiconductor body.

8. The LSI array according to claim 7 wherein said second discretionary interconnection means comprises a second selected subset of said twolayer metalization pattern.

9. A method of making a large scale integrated circuit from a multifunction large scale integrated array, the array comprising a semiconductor body including a plurality of first second and third circuit regions, a first plurality of transistors formed in the semi-conductor body in each of said first regions to define in each thereof a Universal Digital Cell which includes a load cell region and a current switch region which are so arranged that they can be interconnected in a plurality of different ways to define different predetermined primary circuit functions for said Cell, a second plurality of transistors formed in the semi-conductor body in each of said second regions to define peripheral current switch circuits each of which includes at least a load cell region and a current switch region, each of said third regions including a third plurality of transistors, the method including the steps of providing on the array a preselected first set of electrical interconnections to said first regions such as to define the primary circuit functions of said Universal Digital Cells, and providing on the array a second set of electrical connections interconnecting portions of said first second and third regions in a preselected manner such as to define the secondary circuit functions of said Digital Universal Cells.

10. A multifunction large scale integrated array comprising a semiconductor body including a plural- ity of first second and third circuit regions; a first plurality of transistors formed in the semiconductor body in each of said first regions to define in each thereof a circuit cell which includes a load cell region and a current switch region so arranged that said regions can be subsequently interconnected in one of a number of different predetermined ways which make the cell perform different logic functions; a second plurality of transistors formed in the semiconductor body in each of said second regions to define peripheral current switch circuits each of which includes a load cell region and a current switch region, and each of said third regions including a third plurality of transistors, the circuits of said first second and third regions being so arranged that by providing subsequent predetermined electrical connections between said regions the array can be dedicated to define a predetermined circuit of a logic selected in dependence upon the selected connections.

11. An array according to claim 10 wherein for each said first region the load cell region includes a plurality of load transistors and resistors, and the current switch region includes a plurality of transistors and resistors and a source of reference voltages, each said first region incruding terminals to permit selective connection of said load transistors as common emitter differential pairs and for connecting selected ones of the reference voltages to the differential pairs, said terminals also being so arranged to permit selective connection between collectors of said transistors and said load resistors.

12. A multifunction large scale integrated array substantially as hereinbefore described with reference to the accompanying drawings.