JP7089067B2 - 3次元メモリデバイスおよびその形成方法 - Google Patents
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- 229910052721 tungsten Inorganic materials 0.000 claims description 8
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- 238000004544 sputter deposition Methods 0.000 claims description 4
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
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Description
Claims (22)
- 3Dメモリデバイスを形成する方法であって、
基板上に配置された複数の誘電体層ペアを含む交互層スタックを形成することと、
複数の階段領域を形成することであって、前記複数の階段領域のそれぞれは、前記複数の階段領域のそれぞれの第2の方向における両側に第1の数(M)の段を有する階段構造を有し、前記M段のそれぞれは、前記交互層スタックの層スタックの表面の一部分を露出し、前記第1の数Mは正の数であり、前記複数の階段領域は、複数の第1の階段領域を含む、複数の階段領域を形成することと、
前記複数の第1の階段領域のそれぞれで前記交互層スタックのM個の層スタックを除去することと、
第1のマスクスタックを使用して、前記複数の階段領域のそれぞれで前記交互層スタックの前記第1の数Mの2倍である2M個の層スタックの一部分を除去することと、
前記第1のマスクスタックをトリミングすることと、
前記第1のマスクスタックを使用して、前記複数の階段領域のそれぞれで前記交互層スタックの2M個の層スタックの一部分を前記除去すること、および前記第1のマスクスタックを前記トリミングすることを順次繰り返すことと、
を含む、方法。 - 前記複数の階段領域を前記形成することが、
前記交互層スタック上に第2のマスクスタックを形成することと、
リソグラフィプロセスを使用して、前記交互層スタックの上に前記複数の階段領域を画定する前記第2のマスクスタックをパターニングすることと、
前記第2のマスクスタックを使用して、最上部の誘電体層ペアの一部分を除去することと、
前記第2のマスクスタックをトリミングすることと、
前記M段が形成されるまで、前記誘電体層ペアの一部分を除去することおよび前記第2のマスクスタックをトリミングすることを順次繰り返すことと、
をさらに含む、請求項1に記載の方法。 - 前記交互層スタックのM個の層スタックを前記除去することが、ドライエッチング、ウェットエッチング、またはそれらの組み合わせを含む、請求項1に記載の方法。
- 前記第1のマスクスタックを前記トリミングすることが、等方性ドライエッチング、ウェットエッチング、またはそれらの組み合わせを使用して、前記第1のマスクスタックを漸進的かつ内向きにエッチングすることを含む、請求項1に記載の方法。
- 前記第1のマスクスタックが、リソグラフィプロセスによってパターニングされて、第1の方向で前記複数の階段領域のそれぞれの少なくとも1つの縁部を露出し、前記第2の方向で広範囲に前記複数の階段領域のそれぞれを覆う、請求項1に記載の方法。
- 前記第1の方向が前記第2の方向に垂直であり、前記第1および第2の方向の両方が前記基板の上面に平行である、請求項5に記載の方法。
- 前記基板上のスタック格納領域に複数の垂直半導体チャネルを形成することをさらに含み、前記階段領域のそれぞれは、前記スタック格納領域に隣接する、請求項1に記載の方法。
- リソグラフィプロセスは前記複数の階段領域として前記複数の第1の階段領域および他の階段領域を画定することであり、前記複数の第1の階段領域および前記他の階段領域は、前記スタック格納領域によって分離される、請求項7に記載の方法。
- 3Dメモリデバイスを形成する方法であって、
基板上に交互層スタックを形成することと、
前記交互層スタックの表面の第1の部分上の前記交互層スタックの第1の数(M)の層スタックを除去することであって、Mは1より大きい、第1の数(M)の層スタックを除去することと、
前記交互層スタックの前記表面の複数の第2の部分のそれぞれの上に複数の階段構造を形成することであって、前記表面の前記複数の第2の部分は前記表面の前記第1の部分を含み、前記複数の階段構造のそれぞれは第2の方向にM段を有し、前記M段のそれぞれは1レベルで、前記交互層スタックの層スタックの表面の一部分を露出し、前記複数の階段構造は、前記複数の第2の部分のそれぞれの前記第2の方向における両側に形成される階段構造を含む、複数の階段構造を形成することと、
を含む、方法。 - 第1のマスクスタックを使用して、前記複数の階段構造のそれぞれにおいて前記交互層スタックの2M個の層スタックを除去すること、および前記第1のマスクスタックをトリミングすることを順次繰り返すことをさらに含む、請求項9に記載の方法。
- 前記第1のマスクスタックが、前記複数の階段構造のそれぞれの一部分を覆うようにリソグラフィプロセスによってパターニングされる、請求項10に記載の方法。
- 前記交互層スタックを形成することが、化学蒸着、物理蒸着、プラズマ促進CVD、スパッタリング、有機金属化学蒸着、原子層堆積、またはそれらの組み合わせを使用して層を堆積することを含む、請求項9に記載の方法。
- 前記基板上に前記交互層スタックを形成することが、前記基板上に複数の誘電体層ペアを配置することを含む、請求項9に記載の方法。
- 前記交互層スタックを形成することが、前記基板の上面の垂直方向に交互導体/誘電体層ペアを配置することを含む、請求項9に記載の方法。
- 基板上に配置された交互層スタックと、
複数の垂直半導体チャネルを含む格納構造と、
前記格納構造に隣接する第1の階段領域と、
前記格納構造に隣接する第2の階段領域であって、前記第2の階段領域は、前記格納構造によって前記第1の階段領域から水平に分離されている、第2の階段領域と、
前記交互層スタックの複数の層スタックの一部分を露出させるように、前記第1および前記第2の階段領域のそれぞれに配置された複数の階段構造であって、前記複数の階段構造はそれぞれ、前記第1および前記第2の階段領域のうち対応する階段領域の第1の方向に複数の段および第2の方向における両側に第1の数(M)の段を含み、前記第1の方向の前記複数の段のそれぞれは2Mレベルを有する、複数の階段構造と、
を備える、3Dメモリデバイス。 - 前記第1の方向が前記第2の方向に垂直であり、前記第1および前記第2の方向の両方が前記基板の上面に平行である、請求項15に記載の3Dメモリデバイス。
- 前記複数の階段構造の前記第2の方向における両側の前記M段のそれぞれが1レベルである、請求項15に記載の3Dメモリデバイス。
- 前記第2の階段領域における階段構造の最上層スタックが、前記第1の階段領域における階段構造の最上層スタックよりもMレベル低い、請求項15に記載の3Dメモリデバイス。
- 前記交互層スタックの各層スタックが、絶縁材料層および犠牲材料層を含む、請求項15に記載の3Dメモリデバイス。
- 前記交互層スタックの各層スタックが、絶縁材料層および導電性材料層を含む、請求項15に記載の3Dメモリデバイス。
- 前記絶縁材料層が酸化シリコンまたは酸化アルミニウムを含み、前記犠牲材料層が多結晶シリコン、窒化シリコン、多結晶ゲルマニウム、多結晶ゲルマニウムシリコン、またはそれらの組み合わせを含む、請求項19に記載の3Dメモリデバイス。
- 前記導電性材料層が、多結晶シリコン、ケイ化物、ニッケル、チタン、白金、アルミニウム、窒化チタン、窒化タンタル、窒化タングステン、またはそれらの組み合わせを含む、請求項20に記載の3Dメモリデバイス。
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