JP7078099B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP7078099B2 JP7078099B2 JP2020209220A JP2020209220A JP7078099B2 JP 7078099 B2 JP7078099 B2 JP 7078099B2 JP 2020209220 A JP2020209220 A JP 2020209220A JP 2020209220 A JP2020209220 A JP 2020209220A JP 7078099 B2 JP7078099 B2 JP 7078099B2
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Description
[特許文献]
[特許文献1] 特開2008-53648号公報
[特許文献2] 特開2003-188378号公報
第1方向におけるダイオード部の幅は、320μmより小さくてよい。
第1方向におけるトランジスタ部の幅は、第1方向におけるダイオード部の幅の2倍以上3倍以下であってよい。
Claims (26)
- 第1導電型のドリフト領域を有する半導体基板と、
前記半導体基板の内部において、前記半導体基板のおもて面に平行な第1方向に沿って交互に配置されており、前記半導体基板の裏面側に第2導電型のコレクタ領域を有するトランジスタ部と、前記半導体基板の裏面側に、前記ドリフト領域よりもドーピング濃度の高い第1導電型のカソード領域を有するダイオード部と、
前記トランジスタ部および前記ダイオード部の上方に設けられて、前記トランジスタ部および前記ダイオード部に電気的に接続される表面電極と、
前記表面電極に接合されており、前記第1方向における前記表面電極との接触幅が、前記第1方向における前記ダイオード部の幅より大きい外部配線と、を備えており、
前記ダイオード部は、前記半導体基板のおもて面から見て、前記外部配線が前記表面電極と接触している領域と、接触していない領域とで、前記第1方向の幅が同じであり、
それぞれの前記ダイオード部は、前記半導体基板のおもて面側の内部において前記第1方向に並んで形成された複数のトレンチ部を有し、
それぞれの前記ダイオード部は、2つの前記トレンチ部に挟まれたメサ部を前記第1方向に複数有する
半導体装置。 - 前記接触幅は、前記第1方向における前記トランジスタ部の幅および前記第1方向における前記ダイオード部の幅のそれぞれより大きい
請求項1に記載の半導体装置。 - 前記第1方向における前記トランジスタ部の幅は、前記第1方向における前記ダイオード部の幅より大きい
請求項1または2に記載の半導体装置。 - 前記半導体基板の厚みは、前記第1方向における前記ダイオード部の幅の半分より大きい
請求項1から3の何れか1項に記載の半導体装置。 - 前記半導体基板の厚みは、前記第1方向における前記トランジスタ部の幅の半分より大きい
請求項1から4の何れか1項に記載の半導体装置。 - 前記外部配線は、前記第1方向に沿って延伸している
請求項1から5の何れか1項に記載の半導体装置。 - 前記外部配線が前記表面電極と接触する領域と、前記トランジスタ部と前記ダイオード部との境界とが、前記半導体基板のおもて面側から見たときに重なるように前記外部配線が設けられている
請求項1から6の何れか1項に記載の半導体装置。 - 前記表面電極を、前記半導体基板のおもて面から見て、中央部と前記中央部を取り囲む外周部とに区別した場合に、前記外部配線は、前記外周部に接合されている
請求項1から7の何れか1項に記載の半導体装置。 - 前記外部配線は、少なくとも一つの第1外部配線と、少なくとも一つの第2外部配線とを含んでおり、
前記第1外部配線と前記第2外部配線とは、前記半導体基板のおもて面から見て、前記表面電極の対角に接合されている
請求項1から8の何れか1項に記載の半導体装置。 - 前記半導体基板の下方に、はんだ層を更に備え、
前記半導体基板の厚みと前記はんだ層の厚みとの合計が、前記第1方向における前記トランジスタ部の幅よりも大きい
請求項1から9の何れか1項に記載の半導体装置。 - 前記半導体基板の下方に、はんだ層を更に備え、
前記半導体基板の厚みと前記はんだ層の厚みとの合計が、前記第1方向における前記ダイオード部の幅よりも大きい
請求項1から9の何れか1項に記載の半導体装置。 - 前記第1方向における前記ダイオード部の幅は、540μmより小さい
請求項1から11の何れか1項に記載の半導体装置。 - 前記第1方向における前記ダイオード部の幅は、320μmより小さい
請求項1から11の何れか1項に記載の半導体装置。 - 前記第1方向における前記トランジスタ部の幅は、前記第1方向における前記ダイオード部の幅の2倍以上3倍以下である
請求項1から13の何れか1項に記載の半導体装置。 - 前記外部配線が前記表面電極と接触する接合部は、前記トランジスタ部と前記ダイオード部の領域にまたがっている
請求項1から14の何れか1項に記載の半導体装置。 - 前記外部配線が前記表面電極と接触する接合部の前記第1方向における中心が、前記トランジスタ部と前記ダイオード部の境界の上方に配置される
請求項1から14の何れか1項に記載の半導体装置。 - 前記外部配線が前記表面電極と接触する接合部は、前記第1方向に直交して延伸している
請求項1から5の何れか1項に記載の半導体装置。 - 前記外部配線が前記表面電極と接触する接合部は、前記第1方向に平行に延伸している
請求項1から5の何れか1項に記載の半導体装置。 - 前記表面電極は、アルミニウムを含む導電材料である
請求項1から18の何れか1項に記載の半導体装置。 - 前記外部配線は、一つの外部配線あたり複数の接合部において前記表面電極と接触しつつ延伸する
請求項1から19の何れか1項に記載の半導体装置。 - 前記複数の接合部のそれぞれと、前記トランジスタ部と前記ダイオード部との境界とが、前記半導体基板のおもて面側から見たときに重なる
請求項20に記載の半導体装置。 - 前記表面電極の上面に保護膜を備え、
前記保護膜は、前記表面電極を露出する第1開口部を備え、
前記第1開口部は平面視で凸部を有し、
前記凸部の突出した部分は前記第1方向に平行な方向に配置され、
前記凸部の前記第1方向に垂直な端部は前記トランジスタ部と前記ダイオード部の境界に沿って配置されている
請求項16に記載の半導体装置。 - 前記表面電極の上面に保護膜を備え、
前記保護膜は、前記表面電極を露出する第1開口部を備え、
前記第1開口部は平面視で凹部を有し、
前記凹部の底部は前記第1方向に平行な方向に配置され、
前記凹部の前記第1方向に垂直な端部は前記トランジスタ部と前記ダイオード部の境界に沿って配置されている
請求項16に記載の半導体装置。 - 第1導電型のドリフト領域を有する半導体基板と、前記半導体基板の内部において、前記半導体基板のおもて面に平行な第1方向に沿って交互に配置されており、前記半導体基板の裏面側に第2導電型のコレクタ領域を有するトランジスタ部と、前記半導体基板の裏面側に、前記ドリフト領域よりもドーピング濃度の高い第1導電型のカソード領域を有するダイオード部と、前記トランジスタ部および前記ダイオード部の上方に設けられて、前記トランジスタ部および前記ダイオード部に電気的に接続される表面電極と、前記表面電極に接合されており、前記第1方向における前記表面電極との接触幅が、前記第1方向における前記ダイオード部の幅より大きい外部配線と、を備える半導体装置の製造方法において、
前記表面電極の上面に保護膜を形成する工程と、
前記保護膜を形成する工程後に前記保護膜に前記表面電極を露出する第1開口部を形成する工程と、を有し、
前記外部配線は、前記第1開口部を用いて位置決めを行って前記表面電極に接続し、
前記ダイオード部は、前記半導体基板のおもて面から見て、前記外部配線が前記表面電極と接触している領域と、接触していない領域とで、前記第1方向の幅が同じであり、
それぞれの前記ダイオード部は、前記半導体基板のおもて面側の内部において前記第1方向に並んで形成された複数のトレンチ部を有し、
それぞれの前記ダイオード部は、2つの前記トレンチ部に挟まれたメサ部を前記第1方向に複数有する
半導体装置の製造方法。 - 前記第1開口部は平面視で凸部を有し、
前記凸部の突出部は前記第1方向に平行な方向に形成され、
前記凸部の前記第1方向に垂直な端部は前記トランジスタ部と前記ダイオード部の境界に沿って形成される
請求項24に記載の半導体装置の製造方法。 - 前記第1開口部は平面視で凹部を有し、
前記凹部の底部は前記第1方向に平行な方向に形成され、
前記凹部の前記第1方向に垂直な端部は前記トランジスタ部と前記ダイオード部の境界に沿って形成される
請求項24に記載の半導体装置の製造方法。
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