CN114902407A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN114902407A
CN114902407A CN202180008032.4A CN202180008032A CN114902407A CN 114902407 A CN114902407 A CN 114902407A CN 202180008032 A CN202180008032 A CN 202180008032A CN 114902407 A CN114902407 A CN 114902407A
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CN
China
Prior art keywords
wiring member
semiconductor element
semiconductor module
plan
igbt
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CN202180008032.4A
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English (en)
Inventor
山野彰生
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Publication of CN114902407A publication Critical patent/CN114902407A/zh
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Abstract

确保主布线的连接根数来提高对热的耐性。半导体模块(1)具备：层叠基板(2)，在所述层叠基板(2)中，在绝缘板(20)的上表面配置有多个电路板(22、23)；半导体元件(3)，其配置在规定的电路板(22)上，在所述半导体元件(3)的上表面具有主电极、栅极焊盘(30)以及与栅极焊盘电连接的栅极流道(31)；以及布线构件(4)，其将主电极与其它电路板(23)电连接。栅极流道以将主电极分割为一方侧和另一方侧的方式延伸。布线构件以跨越栅极流道的上方的方式配置。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
半导体装置具有设置有IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)、功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)、FWD(Free Wheeling Diode：续流二极管)等半导体元件的基板，该半导体装置被利用于逆变器装置等。
在这种半导体模块中，配置在规定的基板上的半导体元件在上表面形成有主电极(也可以称为表面电极)以及栅极电极。主电极和栅极电极以相互分离的方式设置。在主电极连接接合引线等主布线(主电流布线)，在栅极电极连接控制布线(例如，参照专利文献1-3)。
现有技术文献
专利文献
专利文献1：国际公开第2020/059285号
专利文献2：国际公开第2018/225571号
专利文献3：日本特开2010-016103号公报
发明内容
发明要解决的问题
另外，设想伴随着半导体模块的大容量化、与主电极连接的主布线的根数增加。在该情况下，根据主电极与栅极电极之间的配置关系，有可能使主布线的根数受到限制。如果主布线的根数变少，则每一根主布线的发热量变大，有可能对半导体模块的耐性造成影响。
本发明是鉴于这样的方面而完成的，其目的之一在于提供一种能够确保主布线的连接根数来提高对热的耐性的半导体模块。
用于解决问题的方案
本发明的一个方式的半导体模块具备：层叠基板，在所述层叠基板中，在绝缘板的上表面配置有多个电路板；半导体元件，其配置在规定的电路板上，在所述半导体元件的上表面具有主电极、栅极焊盘以及与所述栅极焊盘电连接的栅极流道；以及布线构件，其将所述主电极与其它电路板电连接，所述栅极流道以将所述主电极分割为一方侧和另一方侧的方式延伸，所述布线构件以跨越所述栅极流道的上方的方式配置。
发明的效果
根据本发明，能够确保主布线的连接根数来提高对热的耐性。
附图说明
图1是本实施方式所涉及的半导体模块的俯视图。
图2是图1的层叠基板单位的局部放大图。
图3是示出本实施方式所涉及的电路的示意图。
图4是参考例所涉及的半导体元件周边的俯视图。
图5是本实施方式所涉及的半导体元件周边的俯视图。
图6是沿着图5的ZX平面切断的截面图。
图7是图6的A部放大图。
图8是变形例所涉及的半导体元件周边的俯视图。
图9是变形例所涉及的半导体元件周边的俯视图。
图10是变形例所涉及的半导体元件周边的俯视图。
图11是变形例所涉及的半导体元件周边的俯视图。
图12是变形例所涉及的半导体元件周边的俯视图。
图13是第二实施方式所涉及的半导体元件周边的俯视图。
图14是图14的局部放大图。
图15是第二实施方式的变形例所涉及的半导体元件周边的俯视图。
具体实施方式
以下，对能够应用本发明的半导体模块进行说明。图1是本实施方式所涉及的半导体模块的俯视图。图2是图1的层叠基板单位的局部放大图。图3是示出本实施方式所涉及的电路的示意图。在图1中，为了便于说明，省略了壳体和芯片上的主布线。另外，在图2中，仅示出主布线，省略了控制布线。此外，以下所示的半导体模块只是一例，不限定于此，能够适当进行变更。
另外，在以下的图中，将半导体模块的长边方向(多个层叠基板排列的方向)定义为X方向，将半导体模块的短边方向定义为Y方向，将高度方向(基板的厚度方向)定义为Z方向。图示出的X、Y、Z的各轴相互正交，形成右手系。另外，根据情况，有时将X方向称为左右方向，将Y方向称为前后方向，将Z方向称为上下方向。这些方向(前后左右上下方向)是为了便于说明而使用的用语，根据半导体模块的安装姿势，与XYZ方向的各方向的对应关系有时会改变。例如，将半导体模块的散热面侧(冷却器侧)称为下表面侧，将其相反一侧称为上表面侧。另外，在本说明书中，俯视是指从Z方向正侧观察半导体模块的上表面的情况。另外，在本说明书中，方向、角度的表述只要大致是该方向、角度即可，在±10度以内是可以被容许的。
本实施方式所涉及的半导体模块例如应用于功率模块等电力转换装置，是构成逆变器电路的功率模块。如图1和图2所示，半导体模块1构成为包括基底板10、配置在基底板10上的多个层叠基板2、以及配置在层叠基板2上的多个半导体元件3。虽然没有特别图示，但半导体模块1除此之外还可以包括收容层叠基板2和多个半导体元件3的壳体、以及填充到壳体内的密封树脂(均未图示)。
基底板10是具有上表面和下表面的长方形的板。基底板10作为散热板发挥功能。另外，基底板10具有在X方向上具备长边、在Y方向上具备短边的俯视时呈矩形的形状。基底板10例如是由铜、铝或者它们的合金等构成的金属板，基底板10的表面也可以被实施有电镀处理。
在基底板10的上表面配置有俯视时呈矩形的形状的壳体。壳体形成为下方开口以覆盖基底板10的上方及多个半导体元件的箱型。壳体划定出收容层叠基板2、半导体元件、密封树脂等的空间。
另外，在壳体设置有外部端子。例如，外部端子包括正极端子(P端子)、负极端子(N端子)以及输出端子(M端子)，除此之外还可以包括控制端子。正极端子、负极端子以及输出端子也可以称为主端子。另外，外部端子也可以包括多个控制端子。各外部端子是对铜材料、铜合金系材料、铝合金系材料、铁合金系材料等的金属板进行压力加工等而形成的。
另外，在壳体11的内侧且基底板10的上表面配置有6个层叠基板2。层叠基板2例如形成为俯视时呈矩形的形状。6个层叠基板2以沿X方向排列的方式配置。层叠基板2是将金属层和绝缘层层叠而形成的，例如由DCB(Direct Copper Bonding：直接铜键合)基板、AMB(Active Metal Brazing：活性金属钎焊)基板或者金属基底基板构成。具体而言，层叠基板2具有绝缘板20、配置在绝缘板20的下表面的散热板(未图示)、以及配置在绝缘板20的上表面的电路板21-24。
绝缘板20在Z方向上具有规定的厚度，形成为具有上表面和下表面的平板状。绝缘板20例如由氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等陶瓷材料、环氧等树脂材料、或者使用陶瓷材料作为了填料的环氧树脂材料等绝缘材料形成。此外，绝缘板20也可以被称为绝缘层或绝缘膜。
散热板在Z方向上具有规定的厚度，形成为覆盖绝缘板的下表面的大致整体。散热板例如由铜、铝等导热性良好的金属板形成。
在绝缘板20的上表面(主表面)，多个电路板21-24(在本实施方式中为4个)以相互电绝缘的状态独立地形成为岛状。其中，3个电路板21-23构成供主电流流通的主布线。另外，电路板24构成控制用的控制布线。这些电路板由用铜箔等形成的规定厚度的金属层构成。例如，电路板21-23也可以被称为主布线层，电路板24也可以被称为控制布线层。
电路板21以偏向X方向负侧的方式配置在绝缘板20的上表面。电路板21沿着绝缘板20的一边在Y方向上延伸，具有Y方向负侧的端部向X方向正侧弯曲的在俯视时呈L字的形状。在电路板21的Y方向负侧且X方向正侧的端部配置有被连接了上臂的集电极电极的外部连接用的焊盘部C1。焊盘部C1与外部的电源正电位点(P端子)连接(参照图3)。即，电路板21构成上臂的主布线层。
电路板22以偏向X方向正侧的方式配置在绝缘板20的上表面。电路板22沿着绝缘板20的一边在Y方向上延伸，具有Y方向正侧的端部向X方向负侧弯曲的俯视时呈L字的形状。在电路板22的L字的角部配置有被连接了上臂的发射极电极及下臂的集电极电极的外部连接用的焊盘部E1C2。焊盘部E1C2作为中间电位点(M端子)与外部的负载连接(参照图3)。即，电路板22构成下臂的主布线层的一部分。
电路板23以比电路板22更偏向X方向正侧的方式配置在绝缘板20的上表面。电路板23沿着绝缘板20的一边在Y方向上延伸，具有Y方向负侧的端部向X方向负侧弯曲的俯视时呈L字的形状。在电路板23的L字的角部配置有被连接了下臂的发射极电极的外部连接用的焊盘部E2。焊盘部E2与外部的电源正电位点(N端子)连接(参见图3)。即，电路板23构成下臂的主布线层的一部分。
电路板24以偏向Y方向负侧的方式配置在绝缘板20的上表面。电路板24沿着绝缘板20的一边在X方向上延伸，具有X方向负侧的端部稍微向Y方向正侧弯曲的俯视时呈L字的形状。
在这些电路板的上表面连接上述的外部端子的端部。这些外部端子各自的端部通过超声波接合、激光接合等直接连接到规定的电路板的上表面，或者借助焊料、烧结金属等接合材料来连接到规定的电路板的上表面。由此，各外部端子的端部与规定的电路板导电连接。为了方便，省略各外部端子与电路板之间的连接关系的说明。
在规定的电路板的上表面，借助焊料等接合材料S(参照图6)配置有半导体元件3。半导体元件3例如由硅(Si)、碳化硅(SiC)、氮化镓(GaN)等半导体基板以在俯视时呈方形的形状(或者呈矩形的形状)形成。此外，作为半导体元件3，使用IGBT(Insulated GateBipolar Transistor)、功率MOSFET(Metal Oxide Semiconductor Field EffectTransistor)等开关元件、FWD(Free Wheeling Diode)等二极管。
在本实施方式中，说明作为半导体元件3使用将IGBT与FWD一体化而成的RC(Reverse Conducting：逆导)-IGBT元件的情况。另外，半导体元件3也可以使用功率MOSFET元件、或者对反向偏置具有充分的耐压的RB(Reverse Blocking：反向阻断)-IGBT等。另外，对半导体元件3的形状、配置数量、配置位置等能够适当变更。此外，本实施方式中的半导体元件3是在半导体基板形成晶体管等功能元件而得到的纵向的开关元件。
在半导体元件3中，在上表面以及下表面分别形成有电极(参照图6)。例如，上表面侧的电极(上表面电极T1)由发射极电极(源极电极)构成。下表面侧的电极(下表面电极B1)由集电极电极(漏极电极)构成。上表面电极T1和下表面电极B2也可以被称为主电极。另外，在半导体元件3的上表面形成有栅极焊盘30和栅极流道31(参照图5、图6)。
栅极焊盘30表示针对半导体元件3的主电流的入口。栅极焊盘30形成于与上述的上表面电极分离(独立)的区域。栅极焊盘30配置于半导体元件3的上表面的外周侧。更具体而言，栅极焊盘30配置于半导体元件3的一边的中央。在图2中，栅极焊盘30配置在半导体元件3的位于X方向负侧的一边上。此外，栅极焊盘30也可以被称为栅极电极。
栅极流道31构成与栅极焊盘30相连的栅极布线。即，栅极流道31构成用于使电流流向半导体元件3内的电流路径的一部分。栅极流道31以将半导体元件3的中央在X方向上分割为2个的方式沿Y方向延伸而形成。栅极流道31以及半导体元件3的表面的详细构造在后文描述。
多个半导体元件3借助焊料等接合材料(未图示)配置在电路板21、22的上表面。由此，半导体元件3的各下表面电极与电路板21、22导电连接。其结果，各外部端子与各半导体元件成为导电连接的状态。
在本实施方式中，在电路板21、22各自的上表面各配置有2个、合计配置有4个半导体元件3。在电路板21中，2个半导体元件3沿Y方向排列地配置。电路板21上的2个半导体元件3构成上臂。在电路板22中，2个半导体元件3沿Y方向排列地配置。电路板22上的2个半导体元件3构成下臂。上臂和下臂配置为在X方向上相向。上臂位于X方向负侧，下臂位于X方向正侧。
半导体元件3的上表面电极和规定的电路板通过引线等布线构件4电连接。例如，构成上臂的半导体元件3的上表面电极经由布线构件4来与电路板22连接。构成下臂的半导体元件3的上表面电极经由布线构件4来与电路板23电连接。
半导体元件3通过所谓的针脚式接合(stitch bonding)来与规定的电路板连接，针脚式接合是在每1个接合点处不将引线切断地对多个接合点连续地实施接合的接合方式。具体而言，如图2所示，布线构件4在半导体元件3的上表面具有2个连接点40、41(参照图4、图5)，在规定的电路板(电路板22或电路板23)上具有1个连接点42(参照图4、图5)。此外，连接点的个数不限于此，能够适当变更。
布线构件4配置为在俯视时沿X方向延伸。另外，布线构件4以在当从Y方向观察时相邻的连接点之间形成拱(arch)的方式延伸。详细情况在后文描述，布线构件4以跨越沿Y方向延伸的栅极流道31的方式配置。即，栅极流道31配置为在连接点40、41之间从布线构件4下穿过。
另外，对每1个半导体元件3配置有多个布线构件4。更具体而言，沿Y方向排列地配置有例如7个布线构件4。另外，布线构件4的数量不限于此，能够适当变更。
这些布线构件4使用导体线(接合引线)。导体线的材质能够使用金、铜、铝、金合金、铜合金、铝合金中的任一者或它们的组合。另外，也能够使用除导体线以外的构件来作为布线构件4。例如，能够使用带(ribbon)作为布线构件4。另外，布线构件4不限于由引线等形成，也可以由铜材料、铜合金系材料、铝合金系材料、铁合金系材料等的带或金属板形成。
另外，设想随着半导体模块的大容量化、与半导体元件的上表面电极(主电极)连接的布线构件(主布线)的根数增加。在该情况下，根据主电极与栅极电极(栅极焊盘)之间的配置关系，有可能使布线构件的根数受到限制。如果布线构件的根数变少，则每一根布线构件的发热量变大，有可能对半导体模块的耐性造成影响。
因此，本申请发明人着眼于半导体元件的内部构造与表面的栅极流道、进一步与布线构件之间的位置关系，想到了本发明。
在此，参照图4至图7，来详细地说明本实施方式所涉及的半导体元件的表面构造。图4是参考例所涉及的半导体元件周边的俯视图。图5是本实施方式所涉及的半导体元件周边的俯视图。此外，在图4和图5中，设为省略半导体元件的上表面电极从而以俯视的方式表现出内部的构造(后述的IGBT区和FWD区)来进行说明。实际的内部构造被上表面电极覆盖，因此不会表现在表面。另外，在图4至图7中，内部构造的布局仅一部分不同，基本具备的结构是共同的。因此，对共同名称的结构标注相同的附图标记并适当省略说明。另外，在以下的图中，以下臂侧为一例进行说明。即，在上臂侧也可以具有与以下相同的构造。
如上所述，半导体元件3是将IGBT与FWD一体化而成的RC-IGBT元件。RC-IGBT元件在上表面电极的下方具有俯视时呈带状的IGBT区3a和FWD区3b。
如图4所示，半导体元件3具有沿Y方向延伸的多个IGBT区3a和沿Y方向延伸的多个FWD区3b。IGBT区3a和FWD区3b在X方向上交替地排列地配置。在图4中，配置有4个IGBT区3a，配置有3个FWD区3b。
另外，如上所述，在半导体元件3的位于X方向负侧的一边上配置有栅极焊盘30。即，栅极焊盘30偏向地配置在半导体元件3的位于外周缘的一边上。另外，在半导体元件3的上表面配置有与栅极焊盘30相连的栅极流道31。
栅极流道31从位于X方向负侧的栅极焊盘30起向X方向正侧延伸。栅极流道31将半导体元件3的上表面中央在Y方向上分割为2个。栅极流道31的延伸方向与IGBT区3a及FWD区3b的延伸方向正交。
另外，在比半导体元件3的与配置有栅极焊盘30的一边相向的一边靠外侧的位置配置有电路板23。即，电路板23隔着半导体元件3的另一边配置于栅极焊盘30的相反侧。
另外，半导体元件3的上表面电极与电路板23通过布线构件4连接。布线构件4在半导体元件3的上表面具有2个连接点40、41，在电路板23上具有1个连接点42。另外，布线构件4在俯视时沿X方向延伸。布线构件4与栅极流道31平行地延伸。另外，布线构件4的延伸方向与IGBT区3a及FWD区3b的延伸方向正交。
如图4所示，在参考例中，在Y方向上排列地配置有2个沿X方向延伸的布线构件4。布线构件4无法以与栅极流道31重叠的方式配置连接点。如上所述，在参考例中，布线构件4与栅极流道31并行。因此，如果想要以避开栅极流道31的方式配置布线构件4，则对布线构件4的根数产生限制。
另外，不限于图4，还设想栅极流道31的延伸方向与IGBT区3a及FWD区3b的延伸方向平行的情况。在该情况下，存在电流难以从栅极流道均等地流向各区的担忧。其结果，产生电流不平衡，从而开关的定时容易产生偏移(日语：ズレ)。
与此相对，在本实施方式中，如图5所示，栅极流道31形成为包围半导体元件3的外周缘整体的矩形框状。具体而言，栅极流道31具有外周部32和直线部33。
外周部32从栅极焊盘30起沿着半导体元件3的外周缘延伸。更具体而言，外周部32从栅极焊盘30的Y方向上的两端部起沿着半导体元件3的外周缘延伸，以包围半导体元件3的外周缘(上表面电极的外周缘)的方式形成为矩形框状。直线部33将外周部32的在Y方向上相向的一边彼此在X方向中央处相连。另外，直线部33以将半导体元件3的中央分割的方式沿Y方向延伸。即，直线部33将半导体元件的上表面(上表面电极)分割为一方侧(X方向负侧)和另一方侧(X方向正侧)。
此外，外周部32不限于包围半导体元件3的外周缘整体的结构。例如，外周部32只要处于至少一方侧(X方向负侧)、即比直线部33靠X方向负侧的位置即可。
在此，对栅极流道31的截面形状进行说明。如图6和图7所示，栅极流道31(外周部32和直线部33)具备栅极布线层34和绝缘膜35。栅极布线层34与上表面电极T1独立地形成，例如由与上表面电极T1相同材质的金属层构成。绝缘膜35用于蒙覆栅极布线层34，例如由聚酰亚胺等树脂形成。绝缘膜35覆盖栅极布线层34的上方，并且还覆盖上表面电极T1的缘部。因此，绝缘膜35具有比栅极布线层34及上表面电极T1向上方鼓起的外表面形状。
另外，与上述同样，布线构件4在俯视时沿X方向延伸。布线构件4在半导体元件3的上表面具有2个连接点40、41，在电路板23上具有1个连接点42。优选像这样，多个布线构件4在半导体元件3的上表面的由直线部33分割出的一方侧和另一方侧的区域中至少各具有1个连接点。另外，详情在后文叙述，优选的是，各连接点与IGBT区3a及FWD区3b这双方重叠。
特别是，在本实施方式中，直线部33以从布线构件4的下方穿过的方式延伸。即，布线构件4以跨越直线部33的上方的方式配置。具体而言，布线构件4还具有第一拱部4a和第二拱部4b(参照图6)。
第一拱部4a与连接点40、41相连，形成为在连接点40、41之间向上方凸的拱状。第二拱部4b与连接点41、42相连，形成为在连接点41、42之间向上方凸的拱状。第一拱部4a跨越栅极流道31的一部分(直线部33)的上方。同样，第二拱部4b跨越栅极流道31的一部分(外周部32的一部分)的上方。
通过像这样使布线构件4与栅极流道31(直线部33)在俯视时交叉，不用在意布线构件4的配置位置，能够在上表面电极上配置更多的布线构件4。例如在图5中，在上表面电极上配置有比图4多的3个布线构件4。
像这样，根据本实施方式，能够确保布线构件4(主布线)的连接根数，增加布线构件4与上表面电极的连接点40、41的数量。其结果，能够减小每一位置连接点的发热量，从而能够减小热分布的不均衡(日语：偏り)。因而，能够提高半导体模块1对热的耐性。
另外，在本实施方式中，半导体元件3具有在俯视时呈矩形的形状，具有配置在呈矩形的形状的一边上(半导体元件3的与作为一方侧的X方向负侧对应的一边上)的栅极焊盘30。另外，相对于电路板22，电路板23(其它电路板)隔着半导体元件3的另一边(半导体元件3的与作为另一方侧的X方向正侧对应的一边)配置于栅极焊盘30的相反侧。根据该结构，能够将与栅极焊盘30连接的控制布线(未图示)配置在作为一方侧的X方向负侧。与此相对，能够将作为主布线的布线构件4配置在比控制布线靠作为另一方侧的X方向正侧的位置。即，控制布线和主布线能够不重叠地分别配置。
另外，在本实施方式中，半导体元件3是将IGBT与FWD一体化而成的RC-IGBT元件。RC-IGBT元件在上表面电极的下方具有在俯视时呈带状的IGBT区3a和FWD区3b。
如图5所示，半导体元件3具有沿X方向延伸的多个IGBT区3a以及沿X方向延伸的多个FWD区3b。IGBT区3a和FWD区3b在Y方向上交替地排列配置。在图5中，配置有4个IGBT区3a，配置有3个FWD区3b。
特别是，在图5中，IGBT区3a及FWD区3b沿与栅极流道31的直线部33交叉的方向(X方向)延伸。即，IGBT区3a及FWD区3b与布线构件4在俯视时沿相同的X方向延伸。此外，IGBT区3a及FWD区3b的延伸方向也可以被称为沟槽方向。
在RC-IGBT元件中，电流容易沿沟槽方向流动。即，在RC-IGBT元件中，电流的流动方向具有指向性。具体而言，主电流从栅极焊盘30流入栅极流道31的外周部32及直线部33。然后，主电流从直线部33在各IGBT区3a及FWD区3b中沿着沟槽方向流向X方向两侧。
另外，由于供主电流流动的布线构件4沿与上述沟槽方向相同的方向延伸，因此，作为模块整体，主电流流动的方向被统一为一个方向(X方向)。其结果，电流的流动分布变得均匀，从而能够抑制噪声、振荡，并且能够进一步防止局部发热。
另外，在本实施方式中，优选IGBT区3a具有比FWD区3b的宽度大的宽度。根据该结构，能够将各个区域中的电流分担(日语：電流分担)平准化，从而能够抑制任一方的异常加热、破坏。
另外，在本实施方式中，优选布线构件4具有至少1个在俯视时与IGBT区3a及FWD区3b这双方重叠的连接点。例如，在IGBT和FWD中，接通断开的定时相反，电流流动的定时也不同。如果连接点仅与一方的区重叠，则存在局部发热的担忧。因此，通过使连接点与双方的区重叠，能够使热分布均匀而抑制局部的发热。
如以上说明的那样，根据本实施方式，通过以从拱状的布线构件4的下方穿过的方式配置栅极流道31(直线部33)，能够确保布线的连接根数来提高对热的耐性。
以下，参照图8至图12来对变形例进行说明。图8至图12是变形例所涉及的半导体元件周边的俯视图。
例如，在上述实施方式中，说明了布线构件4与IGBT区3a及FWD区3b的延伸方向平行地延伸的情况，但不限定于该结构。例如图8所示，布线构件4也可以在俯视时相对于IGBT区3a及FWD区3b的延伸方向倾斜。即，布线构件4只要跨越栅极流道31(直线部33)的上方即可。
另外，在上述实施方式中，说明了布线构件4的各连接点在俯视时与IGBT区3a及FWD区3b重叠的情况，但不限定于该结构。例如图9所示，也可以存在仅与IGBT区3a及FWD区3b中的任一方重叠的连接点。
另外，在上述实施方式中，说明了布线构件4被针脚式接合的情况，但不限定于该结构。例如图10所示，也可以是，针对每1个布线构件，半导体元件3上的连接点仅为1个。在图10中，除了配置有布线构件4以外，还配置有比布线构件4短的布线构件5(第二布线构件)。布线构件4跨越外周部32的位于X方向负侧的一部分及直线部33的上方。布线构件4的连接点40位于比直线部33靠X方向负侧的位置。与此相对，布线构件5不跨越直线部33的上方，跨越外周部32的位于X方向负侧的一部分的上方。布线构件5的连接点51位于比直线部33靠X方向正侧的位置。另外，布线构件构件5的连接点52配置在电路板23上。
另外，在上述实施方式中，说明了在半导体元件3上、布线构件的在比直线部33靠X方向负侧的连接点的数量和比直线部33靠X方向正侧的连接点的数量相同的情况，但不限定于该结构。例如图11所示，布线构件4、5的在作为另一方侧的X方向正侧的连接点的数量也可以比在作为一方侧的X方向负侧的连接点的数量多。
另外，在上述实施方式中，说明了作为栅极流道31的一部分的直线部33在外周部32的中央沿Y方向延伸而将上表面电极分割为2个的情况，但不限定于该结构。例如，也可以是图12所示的结构。在图12中，沿Y方向延伸的2个直线部33与外周部32的在Y方向上相向的一边彼此相连。由2个直线部33将上表面电极在X方向上分割为3个区域。布线构件4也可以在分割出的各区域中配置有连接点40～42。另外，作为布线构件4的端部的连接点43配置在电路板23上。
接着，参照图13至图15来对第二实施方式进行说明。图13是第二实施方式所涉及的半导体元件周边的俯视图。图14是图14的局部放大图。图15是第二实施方式的变形例所涉及的半导体元件周边的俯视图。此外，以下，仅是布线构件(特别是接合位置)的布局与上述实施方式不同，因此对共同的结构标注相同的附图标记并适当省略说明。
如上所述，为了确保半导体模块的耐性，需要考虑布线构件的发热量。例如，即使在半导体模块的动作启动所需的数msec左右的短时间内，也会在芯片附近产生局部的发热(散热)。在芯片背面侧经由焊料和绝缘基板散热，在芯片表面侧经由布线构件(接合引线)散热。在该情况下，设想如果在芯片的外周附近存在布线构件的连接点(接合点)则无法充分地确保散热面积的情况。
特别是在将IGBT与FWD一体化而成的RC-IGBT元件中，如上所述，IGBT区和FWD区形成为沿规定方向延伸的带状。因此，在启动的数msec左右的短时间内，不是在芯片整个表面进行散热，而是偏向呈带状散热。即，与IGBT及FWD独立的情况相比，存在短时间内的散热面积变小、瞬态热阻变大这样的问题。
因此，本申请发明人进一步着眼于RC-IGBT元件中的散热分布及布线构件的布局，想到了本发明。
如图13所示，在第二实施方式中，呈带状地延伸的多个IGBT区3a以及FWD区3b沿着Y方向交替地排列配置。另外，以包围半导体元件3的外周的方式配置有栅极流道31。如上所述，栅极流道31形成为包围半导体元件3的外周缘整体的矩形框状。具体而言，栅极流道31具有外周部32和直线部33。
外周部32从栅极焊盘30起沿着半导体元件3的外周缘延伸。更具体而言，外周部32从栅极焊盘30的Y方向上的两端部起沿着半导体元件3的外周缘延伸，以包围半导体元件3的外周缘(上表面电极的外周缘)的方式形成为矩形框状。直线部33将外周部32的在Y方向上相向的一边彼此在X方向中央处相连。另外，直线部33以将半导体元件3的中央分割的方式沿Y方向延伸。即，直线部33将半导体元件的上表面(上表面电极)分割为一方侧(X方向负侧)和另一方侧(X方向正侧)。
在此，将直线部33称为第一直线部33，将与该第一直线部33相向配置的外周部32的2个直线部称为第二直线部32a。第二直线部32a由从栅极焊盘30起沿着半导体元件3的外周缘延伸的外周部32的一部分构成。这样的外周部32构成半导体元件3的耐热构造部。
如上所述，第一直线部33与外周部32相连，以将半导体元件3的中央分割的方式延伸。另外，第一直线部33位于2个第二直线部32a之间的中央。第一直线部33及2个第二直线部32a相互沿着Y方向而平行，沿与IGBT区3a及FWD区3b的延伸方向(X方向)交叉的方向延伸。
另外，布线构件4配置为在半导体元件3的上方沿X方向延伸，跨越第一直线部33及第二直线部32a的上方。如上所述，布线构件4通过针脚式接合与主电极及规定的电路板23电连接，具有多个连接点40、41、42(接合点)。另外，在图13中，沿Y方向排列地配置有3个布线构件4。
连接点40配置于由栅极流道31包围的在俯视时呈矩形的形状的区域中的、X方向负侧的矩形区域。另外，连接点40配置为在俯视时与位于距第一直线部33及第二直线部32a等距离的位置的中心线C重叠。中心线C在第一直线部33与第二直线部32a之间与第一直线部33及第二直线部32a平行地延伸。
连接点41配置于由栅极流道31包围的在俯视时呈矩形的形状的区域中的、X方向正侧的矩形区域。连接点41与连接点40同样，也配置为在俯视时与位于距第一直线部33及第二直线部32a等距离的位置的中心线C重叠。
通过像这样在距沿Y方向延伸的栅极流道31(第一直线部33、第二直线部32a)等距离的位置设置连接点40、41，能够使散热面积均匀最大化。其结果，能够降低瞬态热阻，进一步能够降低温度纹波。
另外，在图13中，连接点40、41的整体或大部分在俯视时与IGBT区3a重叠。在半导体模块的动作开始时，电流从IGBT区3a流过，因此能够抑制短时间内的瞬态热阻，从而能够防止启动时的局部的发热。
另外，在上述中，说明了连接点40、41形成为在俯视时呈矩形的形状(大致正方形)的情况，但不限定于该结构。例如图14的A、图14的B所示，连接点40、41也可以具有在俯视时在布线构件4的延伸方向(X方向)上长的长圆形状。
另外，在上述中，如图14的A所示，说明了中心线C与连接点40、41的中心线重叠(一致)的情况，但不限定于此，能够适当变更。例如图14的B所示，只要连接点40、41中的至少一部分与中心线C重叠即可，连接点40、41的X方向(长边方向)上的中心线C1与中心线C也可以不必一致。
例如，当将中心线C与中心线C1之间的距离设为dx、将连接点40、41的长边方向上的宽度设为X1时，优选满足0≤dx≤X1的关系。如果处于该范围，则能够充分地享受上述的作用效果。
另外，在图13中，说明了连接点40、41的整体或大部分在俯视时与IGBT区3a重叠的情况，但不限定于该结构。例如图15所示，也可以配置为连接点40、41的整体或大部分在俯视时与FWD区3b重叠。在该情况下，能够抑制因反电动势而在FWD区3b中流有电流的情况下的局部的发热。
另外，在上述实施方式中，电路板的个数及布局不限定于上述结构，能够适当变更。
另外，在上述实施方式中，设为层叠基板2、半导体元件形成为在俯视时呈矩形的形状或者方形形状的结构，但不限定于该结构。层叠基板2、半导体元件也可以形成为除上述形状以外的多边形形状。
另外，对本实施方式及变形例进行了说明，但作为其它实施方式，也可以是将上述实施方式及变形例整体或部分地组合而得到的方式。
另外，本实施方式并不限定于上述的实施方式及变形例，也可以在不脱离技术思想的主旨的范围内进行各种变更、置换、变形。并且，如果由于技术的进步或派生的其它技术而能够以其它方式实现技术思想，则也可以使用该方法来实施。因而，权利要求书涵盖了技术思想的范围内所能包括的全部实施方式。
下面，对上述实施方式中的特征点进行整理。
上述实施方式所记载的半导体模块具备：层叠基板，在所述层叠基板中，在绝缘板的上表面配置有多个电路板；半导体元件，其配置在规定的电路板上，在所述半导体元件的上表面具有主电极、栅极焊盘以及与所述栅极焊盘电连接的栅极流道；以及布线构件，其将所述主电极与其它电路板电连接，所述栅极流道以将所述主电极分割为一方侧和另一方侧的方式延伸，所述布线构件以跨越所述栅极流道的上方的方式配置。
另外，在上述实施方式所记载的半导体模块中，所述半导体元件具有在俯视时呈矩形的形状，所述栅极焊盘配置在所述半导体元件的与所述一方侧对应的一边上，所述其它电路板隔着所述半导体元件的与所述另一方侧对应的另一边配置于所述栅极焊盘的相反侧，所述栅极流道与所述布线构件在俯视时交叉。
另外，在上述实施方式所记载的半导体模块中，所述栅极流道以将所述半导体元件的上表面中央分割的方式延伸，将所述主电极分割为至少2个。
另外，在上述实施方式所记载的半导体模块中，所述布线构件由多个导体线构成。
另外，在上述实施方式所记载的半导体模块中，还具备第二布线构件，所述第二布线构件比所述布线构件短，且在所述另一方侧具有至少1个连接点。
另外，在上述实施方式所记载的半导体模块中，所述布线构件在所述半导体元件的上表面的所述一方侧具有至少1个连接点。
另外，在上述实施方式所记载的半导体模块中，所述布线构件和所述第二布线构件的在所述另一方侧的连接点的数量比在所述一方侧的连接点的数量多。
另外，在上述实施方式所记载的半导体模块中，所述布线构件和所述第二布线构件的在所述一方侧的连接点的数量与在所述另一方侧的连接点的数量相同。
另外，在上述实施方式所记载的半导体模块中，所述半导体元件是将IGBT(Insulated Gate Bipolar Transistor)与FWD(Free Wheeling Diode)一体化而成的RC(Reverse Conducting)-IGBT元件，所述半导体元件还具有在俯视时呈带状地延伸的多个IGBT区和FWD区，多个所述IGBT区与所述FWD区交替地配置。
另外，在上述实施方式所记载的半导体模块中，所述IGBT区及FWD区沿与所述栅极流道交叉的方向延伸。
另外，在上述实施方式所记载的半导体模块中，所述IGBT区具有比所述FWD区的宽度大的宽度。
另外，在上述实施方式所记载的半导体模块中，所述布线构件在俯视时相对于所述IGBT区和所述FWD区的延伸方向倾斜。
另外，在上述实施方式所记载的半导体模块中，所述布线构件具有至少1个在俯视时与所述IGBT区及所述FWD区这双方重叠的连接点。
另外，在上述实施方式所记载的半导体模块中，所述半导体元件具有在俯视时呈矩形的形状，所述半导体元件还具有配置在矩形形状的一边上的栅极焊盘，所述栅极流道具有：外周部，其从所述栅极焊盘起沿着所述半导体元件的外周缘延伸；以及直线部，其与所述外周部相连，且以将所述半导体元件的中央分割的方式延伸，所述布线构件以跨越所述直线部和/或外周部的上方的方式配置。
另外，上述实施方式所记载的半导体模块具备：层叠基板，在所述层叠基板中，在绝缘板的上表面配置有多个电路板；半导体元件，其配置在规定的电路板上，在所述半导体元件的上表面具有主电极、栅极焊盘以及与所述栅极焊盘电连接的栅极流道；以及布线构件，其将所述主电极与其它电路板电连接，所述半导体元件是将IGBT(Insulated GateBipolar Transistor)与FWD(Free Wheeling Diode)一体化而成的RC(ReverseConducting)-IGBT元件，所述半导体元件还具有在俯视时呈带状地延伸且交替地配置的多个IGBT区和FWD区，所述栅极流道具有：第一直线部，其以将所述主电极分割为一方侧和另一方侧的方式延伸；以及第二直线部，其与所述第一直线部相向地配置，且沿着所述半导体元件的外周缘延伸，所述第一直线部及所述第二直线部沿与所述IGBT区及所述FWD区交叉的方向延伸，所述布线构件以至少跨越所述第一直线部的上方的方式配置，所述布线构件的与所述主电极的连接点的至少一部分在俯视时同位于与所述第一直线部及所述第二直线部等距离的位置的中心线重叠。
另外，在上述实施方式所记载的半导体模块中，所述中心线在所述第一直线部与所述第二直线部之间与所述第一直线部及所述第二直线部平行地延伸。
另外，在上述实施方式所记载的半导体模块中，所述半导体元件具有在俯视时呈矩形的形状，所述半导体元件在矩形形状的一边上配置有所述栅极焊盘，所述第二直线部由从所述栅极焊盘起沿着所述半导体元件的外周缘延伸的外周部的一部分构成，所述外周部构成所述半导体元件的耐热构造部，所述第一直线部与所述外周部相连，且以将所述半导体元件的中央分割的方式延伸。
另外，在上述实施方式所记载的半导体模块中，所述布线构件沿在俯视时与所述第一直线部交叉的方向延伸，所述布线构件的连接点具有在俯视时在所述布线构件的延伸方向上长的长圆形状。
另外，在上述实施方式所记载的半导体模块中，所述布线构件的连接点在俯视时与所述IGBT区重叠。
另外，在上述实施方式所记载的半导体模块中，所述布线构件的连接点在俯视时与所述FWD区重叠。
产业上的可利用性
如以上说明的那样，本发明具有能够确保主布线的连接根数来提高对热的耐性这样的效果，特别对半导体模块是有用的。
本申请基于2020年7月7日申请的日本特愿2020-117233。在此包含其全部内容。

Claims (20)

1.一种半导体模块，具备：
层叠基板，在所述层叠基板中，在绝缘板的上表面配置有多个电路板；
半导体元件，其配置在规定的电路板上，在所述半导体元件的上表面具有主电极、栅极焊盘以及与所述栅极焊盘电连接的栅极流道；以及
布线构件，其将所述主电极与其它电路板电连接，
所述栅极流道以将所述主电极分割为一方侧和另一方侧的方式延伸，
所述布线构件以跨越所述栅极流道的上方的方式配置。
2.根据权利要求1所述的半导体模块，其中，
所述半导体元件具有在俯视时呈矩形的形状，
所述栅极焊盘配置在所述半导体元件的与所述一方侧对应的一边上，
所述其它电路板隔着所述半导体元件的与所述另一方侧对应的另一边配置于所述栅极焊盘的相反侧，
所述栅极流道与所述布线构件在俯视时交叉。
3.根据权利要求1或2所述的半导体模块，其中，
所述栅极流道以将所述半导体元件的上表面中央分割的方式延伸，将所述主电极分割为至少2个。
4.根据权利要求1至3中的任一项所述的半导体模块，其中，
所述布线构件由多个导体线构成。
5.根据权利要求1至4中的任一项所述的半导体模块，其中，
还具备第二布线构件，所述第二布线构件比所述布线构件短，且在所述另一方侧具有至少1个连接点。
6.根据权利要求5所述的半导体模块，其中，
所述布线构件在所述半导体元件的上表面的所述一方侧具有至少1个连接点。
7.根据权利要求5或6所述的半导体模块，其中，
所述布线构件和所述第二布线构件的在所述另一方侧的连接点的数量比在所述一方侧的连接点的数量多。
8.根据权利要求5或6所述的半导体模块，其中，
所述布线构件和所述第二布线构件的在所述一方侧的连接点的数量与在所述另一方侧的连接点的数量相同。
9.根据权利要求1至7中的任一项所述的半导体模块，其中，
所述半导体元件是将绝缘栅双极型晶体管即IGBT与续流二极管即FWD一体化而成的逆导型IGBT元件即RC-IGBT元件，所述半导体元件还具有在俯视时呈带状地延伸的多个IGBT区和FWD区，
多个所述IGBT区与所述FWD区交替地配置。
10.根据权利要求9所述的半导体模块，其中，
所述IGBT区及FWD区沿与所述栅极流道交叉的方向延伸。
11.根据权利要求9或10所述的半导体模块，其中，
所述IGBT区具有比所述FWD区的宽度大的宽度。
12.根据权利要求9至11中的任一项所述的半导体模块，其中，
所述布线构件在俯视时相对于所述IGBT区和所述FWD区的延伸方向倾斜。
13.根据权利要求9至11中的任一项所述的半导体模块，其中，
所述布线构件具有至少1个在俯视时与所述IGBT区及所述FWD区这双方重叠的连接点。
14.根据权利要求1至13中的任一项所述的半导体模块，其中，
所述半导体元件具有在俯视时呈矩形的形状，所述半导体元件还具有配置在矩形形状的一边上的栅极焊盘，
所述栅极流道具有：
外周部，其从所述栅极焊盘起沿着所述半导体元件的外周缘延伸；以及
直线部，其与所述外周部相连，且以将所述半导体元件的中央分割的方式延伸，
所述布线构件以跨越所述直线部和/或外周部的上方的方式配置。
15.一种半导体模块，具备：
层叠基板，在所述层叠基板中，在绝缘板的上表面配置有多个电路板；
半导体元件，其配置在规定的电路板上，在所述半导体元件的上表面具有主电极、栅极焊盘以及与所述栅极焊盘电连接的栅极流道；以及
布线构件，其将所述主电极与其它电路板电连接，
所述半导体元件是将绝缘栅双极型晶体管即IGBT与续流二极管即FWD一体化而成的逆导型IGBT元件即RC-IGBT元件，所述半导体元件还具有在俯视时呈带状地延伸且交替地配置的多个IGBT区和FWD区，
所述栅极流道具有：
第一直线部，其以将所述主电极分割为一方侧和另一方侧的方式延伸；以及
第二直线部，其与所述第一直线部相向地配置，且沿着所述半导体元件的外周缘延伸，
所述第一直线部及所述第二直线部沿与所述IGBT区及所述FWD区交叉的方向延伸，
所述布线构件以至少跨越所述第一直线部的上方的方式配置，所述布线构件的与所述主电极的连接点的至少一部分在俯视时同位于与所述第一直线部及所述第二直线部等距离的位置的中心线重叠。
16.根据权利要求15所述的半导体模块，其中，
所述中心线在所述第一直线部与所述第二直线部之间与所述第一直线部及所述第二直线部平行地延伸。
17.根据权利要求15或16所述的半导体模块，其中，
所述半导体元件具有在俯视时呈矩形的形状，所述半导体元件在矩形形状的一边上配置有所述栅极焊盘，
所述第二直线部由从所述栅极焊盘起沿着所述半导体元件的外周缘延伸的外周部的一部分构成，
所述外周部构成所述半导体元件的耐热构造部，
所述第一直线部与所述外周部相连，且以将所述半导体元件的中央分割的方式延伸。
18.根据权利要求15至17中的任一项所述的半导体模块，其中，
所述布线构件沿在俯视时与所述第一直线部交叉的方向延伸，
所述布线构件的连接点具有在俯视时在所述布线构件的延伸方向上长的长圆形状。
19.根据权利要求15至18中的任一项所述的半导体模块，其中，
所述布线构件的连接点在俯视时与所述IGBT区重叠。
20.根据权利要求15至19中的任一项所述的半导体模块，其中，
所述布线构件的连接点在俯视时与所述FWD区重叠。
CN202180008032.4A 2020-07-07 2021-06-07 半导体模块 Pending CN114902407A (zh)

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