JP7010116B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7010116B2
JP7010116B2 JP2018071779A JP2018071779A JP7010116B2 JP 7010116 B2 JP7010116 B2 JP 7010116B2 JP 2018071779 A JP2018071779 A JP 2018071779A JP 2018071779 A JP2018071779 A JP 2018071779A JP 7010116 B2 JP7010116 B2 JP 7010116B2
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JP
Japan
Prior art keywords
high frequency
underfill
semiconductor chip
wall portion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018071779A
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English (en)
Japanese (ja)
Other versions
JP2019186281A (ja
JP2019186281A5 (enExample
Inventor
幸太郎 安藤
智史 細野
篤志 柏崎
俊文 城崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2018071779A priority Critical patent/JP7010116B2/ja
Priority to PCT/JP2019/011947 priority patent/WO2019193986A1/ja
Publication of JP2019186281A publication Critical patent/JP2019186281A/ja
Publication of JP2019186281A5 publication Critical patent/JP2019186281A5/ja
Application granted granted Critical
Publication of JP7010116B2 publication Critical patent/JP7010116B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2018071779A 2018-04-03 2018-04-03 半導体装置 Active JP7010116B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018071779A JP7010116B2 (ja) 2018-04-03 2018-04-03 半導体装置
PCT/JP2019/011947 WO2019193986A1 (ja) 2018-04-03 2019-03-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018071779A JP7010116B2 (ja) 2018-04-03 2018-04-03 半導体装置

Publications (3)

Publication Number Publication Date
JP2019186281A JP2019186281A (ja) 2019-10-24
JP2019186281A5 JP2019186281A5 (enExample) 2020-12-24
JP7010116B2 true JP7010116B2 (ja) 2022-01-26

Family

ID=68100712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018071779A Active JP7010116B2 (ja) 2018-04-03 2018-04-03 半導体装置

Country Status (2)

Country Link
JP (1) JP7010116B2 (enExample)
WO (1) WO2019193986A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7248849B1 (ja) 2022-08-03 2023-03-29 株式会社フジクラ 半導体パッケージおよび高周波モジュール

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269384A (ja) 1999-03-12 2000-09-29 Nec Corp マイクロ波・ミリ波回路装置及びその製造方法
JP2006287962A (ja) 2006-05-19 2006-10-19 Mitsubishi Electric Corp 高周波送受信モジュール
JP2006344672A (ja) 2005-06-07 2006-12-21 Fujitsu Ltd 半導体チップとそれを用いた半導体装置
JP2007518379A (ja) 2004-01-13 2007-07-05 レイセオン・カンパニー 回路基板組み立て品および回路基板へのチップの取り付け方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3207222B2 (ja) * 1991-08-29 2001-09-10 株式会社東芝 電子部品装置
JPH06204293A (ja) * 1992-12-28 1994-07-22 Rohm Co Ltd 半導体装置
JP6183811B2 (ja) * 2014-06-30 2017-08-23 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 接合構造体および無線通信装置
JP6566846B2 (ja) * 2015-11-20 2019-08-28 新日本無線株式会社 中空パッケージ及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269384A (ja) 1999-03-12 2000-09-29 Nec Corp マイクロ波・ミリ波回路装置及びその製造方法
JP2007518379A (ja) 2004-01-13 2007-07-05 レイセオン・カンパニー 回路基板組み立て品および回路基板へのチップの取り付け方法
JP2006344672A (ja) 2005-06-07 2006-12-21 Fujitsu Ltd 半導体チップとそれを用いた半導体装置
JP2006287962A (ja) 2006-05-19 2006-10-19 Mitsubishi Electric Corp 高周波送受信モジュール

Also Published As

Publication number Publication date
JP2019186281A (ja) 2019-10-24
WO2019193986A1 (ja) 2019-10-10

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