JP7007745B2 - 保護キャップ層を用いるプラチナ含有薄膜のエッチング - Google Patents
保護キャップ層を用いるプラチナ含有薄膜のエッチング Download PDFInfo
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- JP7007745B2 JP7007745B2 JP2019539226A JP2019539226A JP7007745B2 JP 7007745 B2 JP7007745 B2 JP 7007745B2 JP 2019539226 A JP2019539226 A JP 2019539226A JP 2019539226 A JP2019539226 A JP 2019539226A JP 7007745 B2 JP7007745 B2 JP 7007745B2
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- C01G55/004—Oxides; Hydroxides
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| WO2019066977A1 (en) | 2017-09-29 | 2019-04-04 | Intel Corporation | FIRST-LEVEL THIN-LEVEL INTERCONNECTIONS DEFINED BY AUTOCATALYTIC METAL FOR LITHOGRAPHIC INTERCONNECTION HOLES |
| US11011381B2 (en) | 2018-07-27 | 2021-05-18 | Texas Instruments Incorporated | Patterning platinum by alloying and etching platinum alloy |
| JP7036001B2 (ja) * | 2018-12-28 | 2022-03-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
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2017
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- 2018-01-19 WO PCT/US2018/014522 patent/WO2018136795A2/en not_active Ceased
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006506827A (ja) | 2002-11-16 | 2006-02-23 | エルジー イノテック カンパニー リミテッド | 光デバイス及びその製造方法 |
| JP2008118088A (ja) | 2006-10-11 | 2008-05-22 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2009176975A (ja) | 2008-01-25 | 2009-08-06 | Renesas Technology Corp | 半導体装置の製造方法 |
| US20100035401A1 (en) | 2008-08-11 | 2010-02-11 | Kuo-Chih Lai | Method for fabricating mos transistors |
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| WO2018136795A3 (en) | 2018-09-07 |
| EP3571709B1 (en) | 2023-11-22 |
| US20240222470A1 (en) | 2024-07-04 |
| US20180204734A1 (en) | 2018-07-19 |
| US11929423B2 (en) | 2024-03-12 |
| US20200083050A1 (en) | 2020-03-12 |
| WO2018136795A2 (en) | 2018-07-26 |
| JP2022043249A (ja) | 2022-03-15 |
| EP3571709A4 (en) | 2020-02-12 |
| CN117153816A (zh) | 2023-12-01 |
| US10504733B2 (en) | 2019-12-10 |
| US11069530B2 (en) | 2021-07-20 |
| EP3571709A2 (en) | 2019-11-27 |
| JP7244030B2 (ja) | 2023-03-22 |
| JP2020507207A (ja) | 2020-03-05 |
| CN110709966B (zh) | 2023-09-19 |
| CN110709966A (zh) | 2020-01-17 |
| US20210313179A1 (en) | 2021-10-07 |
| WO2018136795A8 (en) | 2019-12-12 |
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