TW463309B - A titanium-cap/nickel (platinum) salicide process - Google Patents

Abstract

A method of forming silicide, comprising the following steps. A semiconductor substrate having at least one device thereon having exposed silicon is provided. A layer of nickel-platinum (Ni(Pt)) alloy is deposited at least over the device. A titanium (Ti) capping layer is deposited over the Ni(Pt) alloy layer to form a Ti capped-Ni(Pt) film. The structure is then subjected to a rapid thermal anneal (RTA) to form a silicide over the exposed silicon.

Description

4 6 33 0 9 V. Description of the invention (1) ---------

[Background of the Invention 3 (1) Field of the Invention 1 The present invention # A relates to the use of a shape of a silicide layer, and more particularly a quasi-silicide process: titanium-cap / nickel for semiconductor device manufacturing (Board) 's own explanation of (2) Xi Guangji's stone art, is not: dv Ge self-aligns the reaction between the silicide metal and silicon (with) to limit the power system 1 ί ΐ ΐ is formed by the nucleation of the phases undergoing growth. Restricted, spread over most of the silicon :: δ increases and is noticed in the square root of time / TC ». & & ΐ, (Ti) or cobalt- (c0) -based self-aligned silicide process, system 2 limits the reaction. Due to the lack of nucleation, the necking gate length will ultimately limit the completion of the fir to limit the reaction silicide. Phase transitions, this limitation will cause narrow width chip resistor burring. U.S. Patent No. 5,966,60 7 (〇 ^ 6 61; 31.) Describes a process for forming a metal self-aligned dream material layer on a (metal oxide semiconductor) transistor structure, which can reduce the The risk of metal silicide bridges between the region and a complex crystal gate. Relatively thin nickel or platinum metal layers are formed on the surface of the M0S transistor structure and are used to form metal self-aligned silicides. A thin Ni or Pt metal layer on the surface of the gate sidewall gap reduces the likelihood of metal silicide defects from occurring. U.S. Patent No. 6,025,205 (Park et al.) Describes a platinum alloy film 'specially' (111), (200) or (220) Pt film with nitrogen annealing by limiting the Pt film deposition On a substrate containing nitrogen

Page 6 463309 V. Description of the invention (2) and emotional gases (Ar, Ne, Kr, Xe) are provided and heated to room temperature to 500 ° C. During its formation, the Pt film is then Annealing simultaneously removes nitrogen introduced into the Pt film. US Patent No. 5,668,040 (Byun) describes a capacitor process in which a first metal layer is deposited on a silicon substrate or a silicon oxide layer. The first metal layer contains a titanium-like Group IVB, or VB refractory metal transition elements, and group VIII near inert metal transition elements, such as Ni or Pt, are deposited on the first metal layer, and the substrate and metal layer are heat-treated in an ammonia environment to A refractory metal nitride layer is formed between the refractory metal and a layer close to the inert metal, and if the refractory metal system is deposited on a silicon substrate, during the heat treatment, a silicide layer system is formed between the refractory metal layer and the substrate, However, if the refractory metal oxide layer is formed on the silicon oxide layer, a refractory metal oxide layer is formed during the heat treatment. In the article "On the Ni-Si Phase Transformation With / Without Native Oxide", by PSLee et al, Microelectronic Engineering, 5 Bu 52 (2000), pp. 58 3 to 59 4 describes a research paper , Complete the verification of the effect of natural oxides on the formation of Ni silicide. Ni films of different thicknesses are sputtered on si (100) wafers without oxides, and have natural oxides and RT0 oxide, and performing RTA in a nitrogen environment of about 250 to 90 ° C for one minute, it will be found that the Ni film does not react below 80 ° C, and it is found at 800 to 900 ° CN i S i & will react. In the article " Formation and Stability of Ni (Pt) silicide on (l〇〇) Si and (lll) Si ", D. Mangelinck 6 士 31. 'was accepted in discussion 31 ; .1 ^ 5.5〇 <:, 5711 ^,? 1'〇 (:,; 1999

463309 V. Description of the Invention (3) ~~ Spring Conference [6 pages], describing a research result, the effect of a small amount of Pt (percentage 5) on U 0 0) S 1 and (1 1 1) N i S i Thermal stability of the film, additional whitening (Pt) results in an increase in the nucleation temperature of the disilicide to 900 ° C, and therefore a better stability of a NiSi at a high IC temperature. [Summary of the Invention] Therefore, one of the main objects of the present invention is to provide _Ti —

Process of Ni (Pt). B Another object of the present invention is to separate the natural oxides in the Ni (Pt) silicide formation. Another object of the present invention is to provide a N {-based self-aligned silicide process to form a Ni-based silicide that is thermally stable and independent of line width (for power rather than diffusion limitation). Other purposes will be revealed below. It has been found that the above and other objects of the present invention can be accomplished by the following methods. In particular, a semiconductor substrate having at least one element thereon is provided, with exposed silicon, and at least one layer of nickel-nickel (Ni (pt)) alloy is deposited and coated on the component. A titanium cap layer The system is deposited over the (pt) alloy layer to form a cap-Ni (pt) film. The structure is then subjected to a rapid thermal annealing (RTA) to form a silicide to cover the exposed silicon. [Brief description of the drawings] The features and advantages of the method according to the present invention will be further enhanced by the following description with reference to the drawings: it is understood that the same reference numerals represent similar or equivalent elements, regions and parts, and among them:

4 6 33 0 9 V. Description of the invention (4) Figures 1 to 5 illustrate a preferred embodiment of the present invention. [Brief description of figure number] 10 semiconductor substrate 12 multi-gate 14 multi-gate region 16 sidewall spacer 18 source / drain region 20 active region 22 oxide layer 24 pre-aligned silicide cleaning 26 field oxide region 28 Ni (Pt) layer 30 Ti cap layer 3 2 Rapid heating annealing 40 Ti cap-Ni (Pt) film 50 silicide 6 0 * 5 [Description of the preferred embodiment] Unless otherwise specified, use other methods In addition, all structures, layers, etc. can be formed or completed by known prior art practices. In order to avoid the restriction of nucleation restriction reaction, it is the diffusion restriction rather than the nucleation restriction. It has been suggested to use a nickel- (N i) -based self-aligned silicide process. However, a Ni-based self-aligned silicide process has been suggested. The semiconductor back-end process has insufficient thermal stability to make it worse, and the Ni silicidation process is sensitive to natural oxides.

463309 V. Description of the invention (5) ~ __ Self-aligned silicide process to form a self-aligned silicide layer / metal [prior art known to the inventors] Recently, in order to overcome the thermal instability of nickel silicide, nickel, (N i (ρ alloy stone oxide compounds have been suggested to be stable at 90 (TC temperature, which is applicable to ^)) & wire process' However, 'Ni cannot easily reduce natural oxidation (Si〇2)' Interfacial oxides pose a dangerous problem in the Ni (pt) -self-aligned hardened process, for example, with natural oxides (Si〇2) overlaid on a stone slab (natural oxide blocking). ) The presence of the upper layer '= Nickel (N i) cannot react with S i until annealing at 500 ° C. [Brief Summary of the Invention] In order to overcome these limitations, the author has discovered a novel method for silicide The process is a titanium cap-nickel platinum alloy (Ti cap-Νί (ρΐ)) quasi-fragmentation process, in which a titanium cap from the upper Ni (Pt) layer is used as a suction Agent to separate any natural oxide (si 〇2) and allow the formation of NiSi (nickel silicide) ° To put it simply, the present invention produces a process for cleaning the active and multi-gate regions of semiconductor elements to remove any oxides formed thereon. A layer of (Pt) alloy is formed to cover the clean active and multi-gate regions. Gate region—1 A paper cap layer is then formed to cover the Ni (Pt) layer. A separate rapid thermal annealing (RTA) step is used for Ti-Ni CPt in a Ti cap-Ni (Pt) film. ^ Phase transition, a self-aligned silicide etchback is performed to remove excess Ni (Pt) and unreacted Ti, and then the contact window and post-transmission process are performed.

463309 V. Description of the invention (6) [Detailed description of the preferred embodiment] Therefore, 'as shown in Figure 1, the semiconductor substrate 10 has formed a multi-gate 12 on it' and is in the multi-gate region 1 4 The semiconductor 10 is preferably formed of silicon. The sidewall spacer 16 can be formed adjacent to the multi-gate 12 and the source / drain region 18, and adjacent to the sidewall spacer 16 in the active region 20. The field oxide region (FOX) 26 can be formed adjacent to and outward from the active region 20 to isolate the active region 20 from other adjacent elements or regions. Other starting structures can be used in the process of the present invention. The structure shown in Figure 1 is used for illustrative purposes only. The pre-aligned silicide structure is exposed to the surrounding oxygen and / or moisture, which allows the formation of a layer of oxide 22 to cover the source / inverted region 18, and the multi-gate 12 is usually about 5 To 30 Angstroms thick. In order to remove the oxide layer 22 that has been formed on the exposed debris, a pre-self-alignment dream compound cleaning 24 may be performed, such as a 'diluted hydrofluoric acid (DHF) solution (about HF: Η 2 0 1 0 0: 1) 'Apply to the structure of the first circle, from about 100 to 800 seconds' to remove any oxide layer from the active area 20 and the multi-gate area 14 4 Pre-aligned dream material Washing will remove the total amount of oxide layer 22. However, it is possible that some oxides will stay on the source / drain region 18 or the multi-gate 12 after the pre-aligned debris is cleaned. It is possible that an additional oxide (such as a natural oxide) can be formed on the exposed silicon before the deposition of oxygen or moisture in the atmospheric environment near the structure. 0 and multi-gate region 丨 4.

4 6 33 0 9 V. Description of the invention (7) Ni iPt) deposition As shown in Fig. 2, the Ni (Pt) layer 28 is deposited on the structure and is covered on the multi-gate 12 and the active element. For example, if the source / drain region 18 (ie, any natural oxide (not shown)), the 1 ^ (? 1;) layer 28 is preferably deposited by sputtering, using a layer of nickel (N i) The alloy metal target is from about 0.2 to 10 atomic percent platinum (Pt), and the Ni (Pt) layer 28 is preferably between 50 and 300 angstroms thick. The deposition can be done at or above room temperature. The sputtering can be radio frequency (RF) or non-radio frequency, and the sputtering environment can be argon or an argon: nitrogen mixture. Suitable alloy metal targets include Ni (Pd).

Ti deposition is shown in Figure 3. The Ti cap layer 30 is deposited over the Ni (Pt) layer 28. The Ti cap layer 30 is preferably deposited by sputtering, and The thickness is preferably between 10 and 300 angstroms, and preferably between about 30 and 200 angstroms. The Ti cap layer 30 is formed to form a Ti cap-Ni (Pt) film. Prior to the annealing step of 40, the sputtering conditions can be from room temperature to 40 ITC and plasma assisted with or without NWN2 / Ar conditions. T i N can be used for the T i cap layer 30.

Stringent RTA for NiSi formation As shown in Figure 4, after the formation of the Ti cap layer 30, a rapid thermal annealing (RTA) 32 series is suitable for Ni (Pt) in the Ti cap-Ni (Pt) 40 film. ) The phase transition structure of the lithium oxide, the annealing conditions and the thickness of the deposited layer determine the total amount of silicides 50 and 60 formed, and the total amount of depleted Ti cap layer 30 and Ni (Pt) layer 28. Figure 4 illustrates the partial consumption of the τ 1 capping layer 30 and "(? 1 :) layer 28 forming silicide layers 50, 60. RTA 3 2 is preferably guided from about 400 to Temperature of 8 0 0 ° C '

Page 12 463309 V. Description of the invention (8) ~ To 60 seconds, the RTA temperature rises from about 20 to 100 t / S and the RTA immersion time is from about 5 to 60 seconds.

The Ni (Pt) layer 28 will be stable at about 80 ° C, which is higher than the maximum RTA temperature ', and is used for pure Ni ~ 600 ° C for self-aligned petrochemical processing. For the purposes of the present invention,' RTA32 During this time, the presence of titanium in the Ti cap layer 30 will act as a getter 'to separate any natural oxides between the Ni (Pt) layer 28 and the active region 20 / multi-gate region 14 (s丨 〇2), after the pre-aligned silicide cleaning step in FIG. 1, such natural oxides may exist on the source / and electrode region 18 or multi-gate 12 or may be formed on the Self-aligning the precious metal cleaning step and the formation of the Ni (Pt) layer 28 in FIG. 2, as described above, such natural oxides can be formed to a thickness of about 5 to 80 angstroms, or about 5 To 20 angstroms. The response design varies depending on the thickness of both the Ti cap layer 30 and the Ni (Pt) alloy layer 28 'and their relative thickness ratios. In addition, since it is between 4 0 and 8 0 0 The thermal budget of Ni (Pt) self-aligned silicidation between t, the reaction process and the final structure are determined by the temperature of self-aligned silicidation.

Ti and Ni (Pt) are deposited on the surface. During annealing 3 2 (RTA in N 2 N 2 / A r environment),

The Ti cap layer 30 can prevent the oxidation of the Ni (Pt) alloy layer 28 through a TiO and TiON protective layer (not shown). RTA process Due to the fact that Ni or Ni (Pt) in this embodiment will not reduce the salty natural oxides of SiO, as described in P.S. Lee et al. &Quot; Ni-Si Phase Transformation With / Without Native Oxide "

Number! Page 46 46 33 0 9 V. Description of the invention (9) It is described that T i of the T i cap layer 30 can diffuse through the Ni (P t) alloy layer 2 8 and is slightly tired to the NUP t) alloy layer. The interface between 28 and the bottom layer reduces oxides (not shown) and forms a [Ni (Pt)] xTiy0 internal dielectric layer. "(卩 1;) can diffuse through [] ^ (? 1;); ^ 1 '丨 70 internal dielectric layer and react with silicon to form Ni (Pt) Si silicide layers 50 and 60. The reacted Ni (Pt) will stay on top of Ni (Pt) Si. During the etch-back process, these unreacted Ni (Pt) and Ti-based oxide (TiO) or nitrogen oxide (TiON) — The silicide layer 50 can be formed to cover the source / drain region 18 in the active region 20, and the silicide layer 60 can be formed to cover the multiple gates. The multiple gates 12 in region 14 are transformed from about 50 to 100% of the Ni (Pt) layer 28 to the silicide layers 50 and 60, and from about 2 to 80% of T The i cap layer 30 (according to its thickness) reduces natural oxides. For temperatures S 80 0 ° C, the silicide layers 50 and 60 include 100% Ni (P t) S i; for> 8 0 0 ° C. The silicide layers 50 and 60 also include the total amount of Ni (Pt) Si and Ni (Pt) Si. Self-aligned silicide etchback As shown in Figure 5, a self-aligned silicide etchback The etch system is performed on the structure of Fig. 4 to remove excess Ni (Pt) and unreacted Ti '. It is best to oxidize sulfuric acid in about 1 to 10 minutes. The mixture (H 2S0 4, Η 20 2, Η 20) is applied to the structure, and the sulfuric acid and hydrogen peroxide mixture aligns itself with the silicide etchback solution, preferably from 5 to 55% of H2S04, from 1 to 22.5 % Η 20 2, and from 1 to 2 2. 5% Η 20, the etchback temperature is from 30 to 80 ° C, and

Page 14 4 6 33 0 9 V. Description of the invention (ίο) 1 to 30 minutes. For further processing, this self-aligned silicide etch-back is exposed to the broken material layer 60 in the multi-gate region 14 and the broken material layer 50 in the active region 20, and then a contact window and a custom can be performed. Revert to the latter process. M 3k of the present invention. The advantages of the process of the present invention include: i) the dissociation of natural oxides during the formation of Ni (Pt) Si50, 60; ii) the thermally stable Ni (Pt) Si process, It can prevent the formation of NiSi and has a better agglutination resistance; and iii) T i cap layer 30 prevents oxygen pollution from the surrounding air pressure. Although the present invention has been particularly shown and described with reference to the preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. .

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Claims (1)

4 6 33 0 9 VI. Scope of Patent Application 1. A method for forming silicide, comprising the steps of: providing a semiconductor substrate having at least one element thereon and having exposed silicon; depositing at least one layer of nickel-platinum (Ni (Pt)) alloy is covered on the element; a titanium (T i) cap layer is deposited on the Ni (P t) alloy layer to form a Ti-cap Ni (Pt) film; and The substrate is subjected to a rapid thermal annealing (RT A) to form a silicide to cover the exposed silicon. 2 _ The method described in item 1 of the scope of patent application, wherein the Ni (Pt) alloy layer is between 50 and 300 angstroms thick, and the Ti cap layer is between 30 and 300 angstroms thick . 3. The method as described in item 1 of the scope of the patent application, wherein the Ni (Pt) alloy layer consists of 0.2 to 10 atomic percent platinum in nickel. 4. The method as described in item 1 of the scope of the patent application, wherein the Ni (Pt) alloy layer is formed by sputtering a metal target having 0 in Ni alloy. 2 to 10 atomic percent platinum. 5. The method according to item 1 of the scope of patent application, wherein the rapid heating annealing is performed at a temperature of 400 to 800 ° C, and 10 to 60 seconds. 6 · The method as described in item 1 of the scope of patent application, before the step of depositing the Ni (Pt) alloy layer, including the step of cleaning the semiconductor substrate and components, using a 100: 1 HF solution at 100 Time to 80 seconds 07. The method described in item 1 of the scope of patent application, after the rapid heating annealing step, includes removing any residue by an etch back Page 17 463309 VI. The scope of patent application Ni (P) alloy layer and T i capping step. 8 · The method as described in item 1 of the scope of patent application, which includes a step of removing any remaining Ni (Pt) alloy layer and Ti cap layer by an etch-back after the rapid heating annealing step. ; The etch-back is performed by using a mixture of sulfuric acid and hydrogen peroxide, between 1 and 30 minutes. _ The method as described in item 1 of the patent application scope, after the rapid heating annealing step, including There is a step of removing any remaining Ni (Pt) alloy layer and Ti capping layer by an etchback; the etchback is performed by using a sulfuric acid hydrogen peroxide mixture in a time of 1 to 30 minutes At 30 to 70 ° C; the sulfuric acid hydrogen peroxide mixture includes 5 to 55% of H2S04, 1 to 22.5% of H2O2, and 1 to 22.5% of H20 〇1 0 · As requested The method according to item 1 of the patent, wherein the silicide comprises Ni (Pt) Si. 11. A method for forming silicide, comprising the steps of: providing a semiconductor substrate having at least one active region and at least one multi-gate region; cleaning the semiconductor substrate; depositing at least one layer of nickel-nitride (N i (P t)) an alloy covering the active region and the multi-gate region; depositing a titanium (Ti) cap layer on the Ni (Pt) alloy layer to form a Ti-cap Ni (Pt) film; and Subjecting the substrate to a rapid thermal annealing (RTA) to form a silicide Page 18 463309 VI. Scope of patent application Covers the exposed silicon. 1 2 _ The method described in item 11 of the scope of patent application, wherein the Nic P t) alloy layer is between 50 and 300 angstroms thick, and the Ti cap layer is between 30 and 300 angstroms Between thick. 1 3. The method according to item 11 of the patent application park, wherein the Ni (Pt) alloy layer is made of 0.2 to 10 atomic percent i in nickel. 1 4 · The method as described in item 11 of the scope of patent application, wherein the Ni (Pt) alloy layer is formed by a Tibetan ore-metal handle material, and the metallic material is contained in the Ni alloy. 0.2 to 10 atomic percent platinum. 15 · The method as described in item 11 of the scope of patent application, wherein the rapid thermal annealing is performed at a temperature from 400 to 800 ° C, and from 10 to 60 seconds. The method according to item 11 of the scope of patent application, wherein before the step of depositing the Ni (Pt) alloy layer, a step of cleaning the semiconductor substrate and components is used, using a 100: 1 HF solution, In 100 to 800 seconds. 17 · The method as described in item 11 of the scope of patent application, after the rapid heating and annealing step, including removing any residual Ni (Pt) alloy layer and Ti cap layer by an etchback. step. 18 · The method as described in item 11 of the scope of patent application, which includes the step of removing any remaining Ni (Pt) alloy layer and Ti cap layer by returning a surname after the rapid heating annealing step; The etch-back is carried out by using a mixture of sulfuric acid and hydrogen peroxide, in the range of 1 to 30 minutes. Page 19 463309 VI. Patent Application Range 19 9 _ The method described in item 11 of the patent application range, after the rapid heating and rapid fire step, includes removing any residual N i (P t) the steps of the alloy layer and the Ti cap layer; the etchback is carried out by using a mixture of sulfuric acid and hydrogen peroxide, ranging from 30 minutes to 30 minutes, and sulfuric acid; The hydrogen peroxide mixture includes H 20 2 from 5 to 5 5% and H 20 from 1 to 22.5%. 2 0. The method as described in item 11 of the scope of the patent application, wherein the silicide includes Ni (Pt) Si. 2 1 · A method for forming a silicide, comprising the steps of: providing a semiconductor substrate having at least one active region and at least one multi-gate region; cleaning the semiconductor substrate; depositing at least one layer of nickel from Ni (Ni (Pt)) alloy covers the active region and the multi-gate region; the Ni (Pt) alloy layer has a thickness from 50 to 300 angstroms; a titanium (Ti) cap layer is deposited to cover Forming a Ti-cap Ni (Pt) film on the Ni (Pt) alloy layer; the Ti cap layer has a thickness from 30 to 300 Angstroms; and subjecting the substrate to a rapid thermal annealing (RTA), To form a silicide to cover the exposed silicon. 2 2. The method as described in item 21 of the scope of the patent application, wherein the Ni (P t) alloy layer consists of 0.2 to 10 atomic percent platinum in nickel. 23. The method according to item 21 of the scope of patent application, wherein the Ni (Pt) alloy layer is formed by sputtering a metal target, the metal target is Page 20 4 6 33 0 9 VI. Patent application scope It has 0.2 to 10 atomic percent platinum in Ni alloy. 24. The method according to item 21 of the scope of patent application, wherein the rapid heating annealing is performed at a temperature from 400 to 800 ° C, and from 10 to 60 seconds. The method according to item 21 of the patent application range, wherein the semiconductor substrate cleaning step is performed by applying a 100: 1 HF solution in a time of 100 to 800 seconds. 2 6 The method as described in item 21 of the scope of patent application, after the rapid heating and annealing step, includes a step of removing any remaining Ni (Pt) alloy layer and Ti cap layer by an etch-back. 2 7 · The method as described in item 21 of the scope of patent application, after the rapid heating and annealing step, including a step of removing any remaining Ni (Pt) alloy layer and Ti cap layer by means of a backworm. The etchback is performed by using a mixture of sulfuric acid and hydrogen peroxide, between 1 and 30 minutes. The method as described in item 21 of the patent application scope, after the rapid heating annealing step Including the step of removing any remaining Ni (Pt) alloy layer and Ti cap layer by one step; the etch-back is performed by using a mixture of sulfuric acid and argon peroxide in 1 to 30 minutes At 30 to 70 ° C, the hydrogen peroxide sulfate mixture includes H2S04 from 5 to 55%, H20 2 from 1 to 22.5%, and H20 from 1 to 22.5%. The method as described in claim 21, wherein the silicide includes Ni (Pt) Si.