TW410389B - Manufacture of semiconductor device - Google Patents

Abstract

The present invention discloses a method of manufacturing a semiconductor device using a titanium nitride/titanium capping layer (Ti/TiN) to form a gate electrode, a source region and a drain region which are made of cobalt silicide. A substrate has a gate electrode, a source region and a drain region formed thereon. A cobalt layer is then formed on such semiconductor structure and covers the exposed surface of the gate electrode, the source region and the drain region. A titanium layer is deposited on the cobalt layer and a titanium nitride layer is thereafter formed on the titanium layer. A first annealing step is performed on the cobalt layer with a first temperature to form a cobalt silicide (CoSix) on the gate electrode, the source electrode and the drain electrode. A second annealing step is performed after the titanium nitride layer, the titanium and the unreacted cobalt layer are removed. The later annealing step is used to transform CoSix into CoSi2, which is a thin film with low resistance.

Description

410388 V. Description of the invention (1) " 5 ~ 1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, which includes the formation of a cobalt metal silicide. The present invention is particularly related to covering nitride before the RTp process. Manufacturing method of titanium / titanium on a metal layer. 5-2 Background of the Invention A substance 'refers to a substance formed by the reaction of high-temperature resistant gold with silicon. It has a polycrystalline silicon gate electrode structure and a polycrystalline silicon gate electrode and a silicon silicide or conductive element manufacturing process. Used to connect to each other. For example, cobalt metal silicide, source, and drain materials are used in the process of semiconductor elements' metal petrochemicals or near precious metals (n e a r-η 0 b 1 e m e t a 1) to be used in a variety of applications. In particular, when a metal-oxide semiconductor element is formed, the form of a touch window over the source / drain region of a semiconductor substrate has been widely used in electrical and metallographic applications to provide silicon to the metal. (CoS 込) in ultra large integrated circuits (ULSI) is widely used to reduce gate sheet resistance. FIG. 1A shows a conventional method for manufacturing a semiconductor device. This device includes a silicon semiconductor substrate 10 ', an isolation region 12, a gate oxide layer 14 and the like = an electrode 16, a source region 18, and a drain region 20. Cobalt metal layer μ 2 A polycrystalline silicon gate electrode that is fully deposited on a silicon semiconductor substrate 丨 0, source =

4,105 £ ο ____ 5. Description of the invention (2) Region 1 8 and drain region 20, and above the isolation region 丨 2. In order to prevent the metal layer 22 from being oxidized before the RTP process, an appropriate cap layer µ is necessary to isolate the drilled metal layer 22. This cap layer 24 is formed directly above the cobalt metal layer 22. This structure is then heated to fully react where the cobalt metal contacts the silicon, thereby forming a cobalt metal silicide. However, in the current manufacturing environment, it is an difficult task to form a thick and uniform cobalt metal silicide, and at the same time to avoid unnecessary excessive growth of the metal metal silicide. Figure 1B shows a semiconductor device with an irregular cobalt metal silicide region due to excessive growth. We can solve the problem of excessive growth of cobalt silicide by sputtering a titanium nitride capping layer over the cobalt metal layer before the RTP process. The use of this nitrided capping layer can effectively avoid the oxidation of cobalt metal and improve the relationship between the resistance of the gate sheet and the gate length. However, there are still some disadvantages to using a titanium nitride cap layer. Because titanium nitride is a compressive thin film, the interface between the metal silicide and silicon formed on the crystal can be seen to be coarse k. In addition, the 'nitride capping layer' also has a characteristic of current leakage at a non-uniform bonding surface.

^ Traditionally, the cap layer 24 (shown in Figure A) is usually a titanium nitride layer, as described elsewhere. But recently titanium caps have also been used. Titanium is used to cover the gold eyebrow layer, which is a structure formed by heating to form a cobalt metal silicide. The interface formed between the metal silicide and polycrystalline silicon is smoother than the nitride ‘too 4’. But the use of titanium can improve the disadvantages of using titanium nitride

Page 6 5. Description of the invention (3) However, after the RTP process, it will form a mixture of TiCo or TiCoSi. After the first RTP process, these mixtures were easily etched by wet cleaning. Therefore, for processes that require wider contact windows, care must be taken to avoid the formation of too thin cobalt metal silicides. As a result, neither vaporization nor titanium is suitable for forming a good cap layer of metal silicide. Therefore, the need for another technology for forming cobalt metal silicides on semiconductor surfaces is even more urgent. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned backgrounds of the invention, the traditional titanium capping layer or titanium nitride capping layer has many shortcomings. The present invention provides a method for forming a cobalt metal silicide, which includes -nitriding. Titanium / titanium / cobalt / polycrystalline silicon (TiN / Ti / Co / poly) # thin film. This method can prevent the oxidation of cobalt metal before the RTp process. The preferred embodiment of the present invention proposes a cap layer containing titanium nitride and titanium instead of the traditional single titanium cap layer or single titanium nitride cap layer. This embodiment can not only overcome many disadvantages caused by the tradition, but also save the necessary advantages of the traditional cover layer. In order to achieve the above-mentioned purpose and to cooperate with the purpose of the present invention, a condensed description of the big 2 and a specific embodiment of the present invention are described here: This embodiment includes: a TiN / Ti coating on a cobalt metal layer Manufacturing method of capping semiconductor element. The method includes at least: first, providing a silicon substrate

410388 V. Description of the Invention The semiconductor structure of the gate electrode, source region, and drain region after the ion implantation process. The above-mentioned semiconductor elements, which have been pre-cleaned, are formed on the wafer before the cobalt metal layer is deposited by sputtering. Furthermore, a metal layer is formed on the semiconductor structure and covers the exposed surface of the source electrode's source region and the drain region. Subsequently, a capping layer is covered on the cobalt metal layer, wherein the capping layer includes a titanium film and a titanium nitride layer. The titanium film is located directly above the cobalt metal layer, which is used to improve the uniformity of the metal silicide. The titanium nitride layer is located on the surface of the titanium thin film, which is used to prevent the cobalt metal layer from oxidizing. Thereafter, 'the first tempering step is performed on the junction metal layer at the first temperature to form a coba 11 si 1 ici de (CoS ix) on the gate electrode, the source region' and the drain region. Above "then, remove the titanium nitride layer 'titanium film and unreacted cobalt metal by wet etching" Finally, perform the second tempering step at a second temperature higher than the first temperature, so as to transform CoSix iC 〇Si2 structure 'is a thin film structure with lower resistance. Schematic illustrations of 5-4 diagrams: The first diagram A shows a wearing view of a semiconductor structure having a conventional titanium or titanium nitride capping layer;

410388 V. Description of the invention (5) The first diagram B shows a cross-sectional view of a conventional semiconductor structure with an irregular metal sanding region; the second diagram A shows a gate electrode, a source region, and a drain electrode. A cross-sectional view of a semiconductor structure in a polar region; and FIGS. 2B to 2G are cross-sectional views illustrating main steps of a process according to an embodiment of the present invention. Representative symbols of the main parts: 10 semiconductor substrate 12 isolation region 14 gate oxide layer 16 gate electrode 18 source region 20 drain region 2 2 starting metal layer 24 capping layer 3 0 · irregular cobalt metal silicide region 2 0 0 semiconductor substrate 202 polycrystalline silicon gate electrode 2 0 4 source region 2 6 drain region

_ £ ΐ〇3δδ V. Description of the invention (6) 2 08 Isolation area 21 ° Spacer 2 1 2 Gate oxide layer 2 1 4 (Cobalt) metal layer 21 6 Thin film 21 8 Titanium nitride layer 220 Low temperature cobalt metal silicide (C〇six) 230 high temperature cobalt metal silicide (c〇Si2) 5-5 Detailed description of the invention: The first A to the second g diagrams are cross-sectional views related to the process of the preferred embodiment of the present invention. Only the main steps of the incoming process are described. First, starting from the second A diagram, a typical semiconductor device is shown, which includes a semiconductor substrate 200, a polycrystalline silicon gate electrode 202, a source region 204, and an electrodeless region 20β formed in an ion implant. After entering the procedure, the semiconductor device further includes an isolation region 208 and a gap wall 210. This oxide layer is 21.2. Subsequently, the half-closed element that has been formed on the wafer is pre-cleaned before the cobalt metal layer is deposited by sputtering. After the pre-cleaning step, as described in the second B diagram, a body is formed—

214 on the semiconductor structure, especially covered with polycrystalline stone ^ ^ ^

Article 10 I _Jina ^ c__ ____ V. Description of the Invention (7) All exposed surfaces of the source region 202 and the drain region 206 of the electrode 202. The metal layer 214 is formed by a sputtering deposition method and has a thickness between about 50 and 300 angstroms. In addition, the metal used is an element selected from the group consisting of cobalt, tungsten, cobalt alloy 'titanium' nickel, and platinum. Among them, the above-mentioned inscriptions and alloys are the most commonly used metal materials in the ULSi process. Now, "citing the second C figure", a titanium thin film 21 6 is deposited on the cobalt metal layer 214 ', and its thickness is between about 10 and 200 angstroms. This titanium thin film 216 must be substantially equal to 溥 'in order to improve the homogeneity of the cobalt metal silicide and improve the thermal stability of the metallized silicon / polycrystalline silicon stack structure. Subsequently, as shown in FIG. 2D, a titanium nitride layer 218 is formed on the surface of the titanium thin film 216, and its thickness is thicker than that of the iridium thin film 216 and is between about 50 and 500 angstroms. The main function of the nitride layer 218 is to prevent the cobalt metal layer from being oxidized before the RTp process. The formation of the above-mentioned thin film and titanium nitride layer plays a role of a capping layer = a TiN / Ti capping layer on top of the cobalt metal layer. Thereafter, a first-rate tempering step is performed on the starting metal layer 214 at a temperature between about 400 ° C and 680 ° C, thereby forming a diamond metal oxide compound (c oba 11 si 11 'ide' CoSix) 220 is above the gate electrode 202 'source region 204 and the bismuth region 206. The overall structure of the completed semiconductor device at this time is shown in the second E diagram. After that, as shown in the figure, the titanium nitride layer, the titanium film, the unreacted unreacted metal, and all the starting metal reactants except the gold oxide are removed by wet removal. Finally, on the diamond metal eve

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41038S V. Description of the invention (8) The compound performs a second rapid tempering step at a temperature higher than the first temperature, with I between about 700 and 95. The latter rapid tempering step is used to transform the CoS ix to CoS iz structure 230, a lower-resistance film structure, as shown in the second G diagram. The above are only the preferred embodiments of the present invention, and are not used to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.

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Claims (1)

41038S I.----VI. Scope of Patent Application 1 _ A method for manufacturing a component 'which at least includes: providing a semiconductor structure having a substrate, a gate region, and a double electrode; forming a metal layer on the semiconductor The upper surface of the structure; depositing a titanium film on the metal layer; forming a titanium nitride layer on the surface of the titanium film; performing a first tempering step on the metal layer at a first temperature to form A metal silicide (MS ix); removing the titanium nitride layer, the thin film, unreacted metal, and all metal reactants other than the metal silicide; and The metal silicide performs a second tempering step at a second temperature. 2. The method according to item 1 of the patent application range, wherein the semiconductor structure described above further includes an isolation region, a gate oxide layer, and a spacer. 3. The method according to item 1 of the patent application range, wherein the above gate region contains at least polycrystalline silicon. 4. The method according to item 1 of the patent application range, wherein the above-mentioned double electrode includes at least a source region and a drain region. 5. ^ The method of applying for item 1 of the patent scope, wherein the above-mentioned metal layer system, bent from the square, consisting of a junction 'tungsten' alloy, titanium, nickel, and platinum '& Y's 41038S VI. Scope of Patent Application Elements. 6. The method according to item 5 of the scope of patent application, wherein the formation of the above metal layer is a sputtering deposition method, and its thickness is between about 50 and .300 angstroms. 7. The method of claim 1, wherein the depositing a titanium film further comprises depositing titanium metal having a thickness of about 10 to 200 angstroms on the metal layer. 8. The method according to item 7 of the patent application, wherein the titanium thin film described above has the function of a getter layer and can improve the homogeneity of the metal oxide. 9. The method of claim 1 in which the above-mentioned titanium nitride layer is about 50 to 500 angstroms thick. 10. The method according to item 9 of the scope of patent application, wherein the titanium nitride layer described above acts as a protective layer to prevent the metal layer from oxidizing. 11. The method according to item 1 of the patent application range, wherein the first temperature is about 40 ° C to 680 ° C. 1 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned second temperature is between about 70 ° C and 950 ° C. Page 14 41038S VI. Application for Patent Scope 1 3 · As in the method for applying for the scope of patent application item 1, wherein the aforementioned metal silicide (MSix) is selected from the group consisting of cobalt, tungsten, and cobalt An element in a group consisting of alloys, and X is an integer selected from the group consisting of 1, 2, 3, and 4. 14. The method according to item 1 of the scope of patent application, wherein the second tempering step is used to transform MSix IMSi2, a low-resistance thin film structure. 15. —A method of manufacturing a semiconductor device having a titanium nitride / titanium (TiN / Ti) layer_ which includes at least: providing a substrate, a gate electrode, a source region, and a drain region; A semiconductor structure; forming a cobalt metal layer on the semiconductor structure and covering the gate electrode, the source region, and the exposed surface of the drain region; depositing a titanium thin film on the cobalt metal layer to Improving the uniformity of a metal silicide; forming a titanium nitride layer on the surface of the titanium thin film to prevent the cobalt metal layer from being oxidized; performing a first tempering step on the cobalt metal layer at a first temperature, A cobalt silicide (CoSix) is formed on the gate electrode, the source region, and the drain region; the titanium nitride layer is removed, and the titanium film is not raised. Reacted cobalt metal, and all cobalt metal reactants other than cobalt metal silicides; and 41038S 6. Scope of patent application A second tempering step is performed on the cobalt metal silicide at a second temperature higher than the first temperature. 16. The method according to item 15 of the scope of patent application, wherein the above-mentioned semiconductor structure further includes an isolation region, a gate oxide layer, and a spacer. 17. The method according to item 15 of the scope of patent application, wherein the above gate region contains at least polycrystalline silicon. 18. The method according to item 15 of the scope of patent application, wherein the formation of the above-mentioned cobalt metal layer is by a sputtering deposition method, and its thickness is between about 50 and 300 angstroms. 19. The method according to item 15 of the scope of patent application, wherein the above-mentioned deposition of a titanium film further comprises depositing titanium metal having a thickness of about 10 to 200 angstroms on the cobalt metal layer. 20. The method according to item 15 of the scope of patent application, wherein the above-mentioned titanium nitride layer is about 50 to 50 angstroms thick. 21. The method according to item 15 of the patent application, wherein the first temperature mentioned above is between 400 ° C and 680 ° C. 22. The method according to item 15 of the patent application range, wherein the second temperature is between about 700 ° C and 950 ° C. Page 16 410389 6. Application scope of patent 23. The method according to item 15 of the scope of patent application, wherein the above-mentioned cobalt silicide (CoSix), whose X is selected from 1, 2, 3, and An integer in the group of 4. 24. The method according to item 15 of the scope of patent application, wherein the second tempering step is used to transform CoS ix to CoS i2, a low-resistance thin film structure. Page 17