TW442858B - Process to form gate - Google Patents

Abstract

This invention provides a process to form gates on a semiconductor chip, which can avoid circuit short resulting from residual conductive matter on the gate side wall surface. A quasi-gate structure is formed on the substrate surface, which contains, from bottom to top, a gate dielectric layer, a polysilicon layer and a transition layer. The transition layer is removed after a side wall is formed around the quasi-gate structure. Finally, a silicide layer is formed on the polysilicon layer and the silicon substrate around the side wall. The side wall will be protruded out from the both sides of the polysilicon layer, after the removal of the transition layer, to prevent circuit short due to the electric conduction between silicides on the polysilicon layer and silicon substrate caused by the residual conductive matter on the side wall surface.

Description

44285a V. Description of the invention (i) Field of the invention The present invention provides a method for fabricating a gate electrode on a semiconductor wafer, and more particularly, a method for avoiding short circuit caused by conductive substances remaining on the surface of the side wall around the gate electrode. Background Description Metal-oxide semiconductor (JJOS) transistors are thought to be very important components in semiconductor integrated circuits. The MOS transistor system is an electronic component with four contacts (1; 6]:] 11111313) composed of a gate, a source, a drain, and a substrate electrode. The main structure of the gate electrode is composed of a gate oxide layer and a gate conductive layer. Then, in the periphery of the gate structure, a side wall is used as an insulating protection layer. Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of a conventional method for fabricating a MOS transistor 40 on a semiconductor wafer 10. As shown in circle 1, a semiconductor substrate 10 includes a silicon substrate. ) 12. A conventional method is to first use a thermal oxidation method to generate silicon dioxide (silicon dioxide,

Si02) layer 10 is then deposited by chemical vapor deposition (CVD) on the surface of the silicon dioxide layer 14 with a polycrystalline silicon layer 16 and doped with the polycrystalline silicon layer 16. Then coating on the polycrystalline silicon layer 16-photoresist V. Description of the invention (2) (photoresist), and a yellow light process to define the gate circle, and finally remove the excess photoresist, Only the part of the photoresist 18 in the first one is left as a hard mask in the subsequent etching process. As shown in Min Er, a dry etching process is then performed to remove the portion not protected by the photoresist 18 downward to form the gate electrode 20. The photoresist 18 is then stripped. The gate electrode 20 includes a gate oxide layer 22 and a doped polycrystalline silicon layer 24. Then, a low-pressure CVD method is used to form a silicon oxide layer 26 on the surface of the silicon substrate 12 and the surface of the gate electrode 20. Subsequently, an ion implantation process is used to form doped regions 28 in the dream substrate 12 on both sides of the gate 20, which are used as lightly doped and lightly doped MOS transistors. drain, LDD) »Then a CVD process is performed to deposit a silicon nitride layer 30 on the surface of the silicon oxide layer 26 to uniformly cover the gate electrode 20. As shown in FIG. 3, a non-isotropic dry etching process is performed to remove the silicon nitride layer 30 downward, so that the silicon nitride layer 30 remaining around the gate electrode 20 forms a sidewall 32. Next, an ion implantation process is performed to form a doped region 34 in the silicon substrate 12 on both sides of the gate electrode 20, which is used as a source and a drain of the JJ0S transistor. Subsequently, a silicon nitride layer (not shown) is uniformly deposited on the surface of the silicon substrate 12, and the residual silicon oxide layer 26 on the surface of the silicon substrate 12 is completely removed by a cleaning process. Then, a Cobalt metal layer 36 and a titanium nitride layer 38 are formed uniformly on the surface of the semiconductor wafer 10 by sputtering method. As shown in circle four ’, a rapid heating process (rap i (1 thermal

442858 V. Description of the invention (3) process (RTP) ′ causes the cobalt metal layer 36 to react with silicon atoms on the silicon substrate 12 and the surface of the doped polycrystalline silicon layer 24 to generate cobalt self-aligned silicide 42. Then, the unreacted cobalt metal layer 36 and the titanium nitride layer 38 are removed to complete the fabrication of the MOS transistor 40. However, as the semiconductor process becomes more and more precise, conventional methods, after forming the self-aligned silicide 42 and removing the unreacted metal layers 36 and 38, often fail to completely remove the metal layer 36'38. It is clean, so that a part of the metal layer 44 remains on the surface of the side wall 32, as shown in FIG. These remaining metal layers 44 may conduct the metal silicide on the doped polycrystalline silicon layer 24 and the metal silicide layer 42 on the silicon substrate 12, which may cause a short circuit and affect the electrical properties of the MOS transistor 40. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for avoiding the residual conductive material on the surface of the side wall around the gate electrode on a semiconductor wafer to solve the problems of the conventional technology. In a preferred embodiment of the present invention, the method is to first form a quasi-electrode structure on the substrate surface of the semiconductor wafer, and the quasi-gate structure includes a gate dielectric layer and a polycrystalline silicon in order from bottom to top. Layer and a transition layer. Then, a side wall ’is formed around the quasi-gate structure, and then the transition layer is removed. Finally, a silicon base is formed on the polycrystalline silicon layer and around the side wall.

Page 6 442858 V. Description of the invention (4) A metal silicide layer is formed on the bottom. After the transition layer is removed, the top of the sidewall will protrude above the top surface of the polycrystalline silicon layer, so as to prevent conductive substances remaining on the surface of the sidewall from conducting the metal oxide layer on the polycrystalline layer and the polycrystalline silicon layer. A metal dream layer on a dream substrate. According to the present invention, the shape of the tops of the sidewalls protruding from both sides of the gate electrode is used to prevent the cobalt metal layer or the titanium nitride layer from remaining on the surface of the sidewalls after the subsequent etching or cleaning process. Even if there is a residual conductive substance, it is not easy to remain on the side surface of the side wall in a continuous state, so it is possible to avoid the short circuit caused by conducting the metal hairpin layer on the #heteropolycrystalline dream layer and the metal hairpin layer on the hair substrate. For a detailed description of the invention, please refer to ®Five to Twenty-eight's. Figures five to eight are schematic circles of a method for manufacturing a MOS transistor 80 on a half-concept wafer 50 according to the present invention. As shown in FIG. 5, the semiconductor wafer 50 includes a silicon substrate 52. The method of the present invention first uses a thermal oxidation method to form a silicon dioxide layer 54 on the surface of the silicon substrate 52 with a thickness of about 33 angstroms. Then, a chemical vapor deposition (CVD) method is used to deposit a polycrystalline silicon layer 56 on the surface of the silicon dioxide layer 54 to a thickness of about 2000 & In addition, in order to reduce the resistivity of the polycrystalline dream layer 56, after the polycrystalline silicon layer 56 is deposited, it needs to be doped again: the dopant tends to be doped by means of high-temperature diffusion or ion implantation ( drive in) or implanted in the polysilicon layer 56, or proceed to $ 442858 with the deposition reaction of the polycrystalline silicon from the beginning. 5. Description of the Invention (5) I n s i tu. An annealing is then performed at a temperature of about 800 ° C to rearrange the atomic arrangement in the silicon substrate 52. Then, a sputtering process is used to form a transition layer 57 on the surface of the polycrystalline debris layer 56 with a thickness of about 5000 to 1000. In the present invention, tungsten silicide (tungsteri filicide) is selected as the material of the transition layer 57, and the subsequent process of etching the polycrystalline silicon layer 56 and the tungsten silicide transition layer 57 can be performed in the same furnace tube. Then, a photoresist is coated on the transition layer 57 and a yellow light process is used to define the gate pattern 'finally remove the excess photoresist' and leave only the part of photoresist 58 in Figure 5 as a follow-up Hard military curtain in etching process. As shown in FIG. 6, a dry etching process is performed next to remove the portion not protected by the photoresist 5 8 to form a pre-gate structure 60 on the surface of the silicon substrate 52. The photoresist 58 is then stripped. Quasi-gate structure 60 is formed by stacking a gate oxide layer 62, a doped polycrystalline silicon layer 64, and a transition layer 65. Then, a low-pressure CVD method is used to form a silicon on the surface of silicon substrate 52 and the surface of quasi-gate structure 60. Oxygen layer 66. Next, an ion implantation process is performed to form doped regions 68 in the stone susceptor 52 on both sides of the quasi-gate structure 60, which are used as lightly doped drains (LDDs) of the Mos crystals to be completed later. Then a CVD process is used to deposit a silicon nitride layer 70 on the surface of the silicon oxide layer 66 to uniformly cover the quasi-gate structure. The silicon oxide layer 66 is mainly used as a sacrificial layer in the ion implantation process.

Page 8 4428 5 8 V. Invention ~~~~~ '— (sacrificial oxide) to avoid the occurrence of tunneling effect (channeUng), and can be used as a lining oxide layer to increase the adhesion of the subsequent nitrogen silicon layer) » As shown in FIG. 7 ′, an anisotropic dry etching process is performed, the silicon nitride layer 70 is removed downward, and the silicon nitride layer 70 remaining around the quasi-gate structure 60 is formed as a side wall 72. Next, an ion implantation process is used to form a doped region 74 in the silicon substrate 52 around the quasi-gate structure 90, which is used as a source and a drain of the MOS transistor. Subsequently, the RCA cleaning solution is used to remove the transition layer 65 composed of tungsten silicide in the quasi-gate structure 90. At the same time, the silicon oxide layer 66 may be partially lost. At this time, the gate 69 formed on the semiconductor wafer 50 will only include the gate halide layer 62 and the doped polycrystalline silicon layer 64 above it, and then a silicon oxide remaining on the surface of the silicon substrate 52 by a cleaning process. Layer 66 is completely removed. Then, a metal layer 76 and a titanium argon layer 78 are uniformly formed on the surface of the semiconductor wafer 50 by sputtering. In addition to avoiding the reaction of the surface of the metal layer 116 with oxygen, the titanium nitride layer 78 can also homogenize the subsequently generated cobalt to align itself with the Co salicide. "As shown in circle eight, 'a fast heating process is performed. (RTP), reacting the cobalt metal layer 76 with the silicon atoms on the surface of the silicon substrate 52 and the surface of the doped polycrystalline silicon layer 64 to form a cobalt metal silicide layer 82, and complete the self-aligned silicide process. Then remove the unreacted cobalt metal layer 76 and titanium nitride layer 78.

V. Description of Invention (7) Division. The rapid heating process involves a stage temperature of about 600 ° C. (: To 6 4 7 7 0 ° C. Finally, rearrange the atomic arrangement in the i substrate 5 2 at about 8 2 5 ° C. The present invention mainly forms a transition layer 65 before the quasi-gate junction, and then In the quasi electron 72, the doped polycrystalline silicon layer 64 of the transition layer 65 is removed, and the protrusion is shown as shown in the doped VII. Since it protrudes from the gate 69, the etching process and the titanium nitride layer 78 are not easy to remain on The special shape structure of the side wall 72, even if it is qualitative, is not easy to remain in a continuous state on the metal silicide layer 82 of the non-conducting doped polycrystalline silicon layer 64 and cause a short circuit. Compared with the conventional method, the wall of the present invention is steeper. The shape of the top end makes cobalt on the surface of the side wall, even if there is a residual state on the surface of the side wall, so it can be layered on the metal stone oxide layer and the silicon substrate. One or two-stage heating and heating process, ° C ' The second stage is about 730. (: A tempering process is performed to make the silicon complete the production of MOS transistor 80. Structure 90 is doped with a polycrystalline dream layer 6 4 and a gate structure 9 is formed around the sidewall. , The top of the side wall 72 will be higher than that of the heteropolycrystalline silicon layer 64 Around, if the top side of the solid side wall 72 is steeply shaped, after the cleaning process, the surface of the cobalt metal layer 76 is 72. In addition, because the surface of the side wall 72 is etched or cleaned by the remaining conductive material, the silicide layer 82 can be avoided. And the silicon substrate 52 is formed by using a side metal layer or a titanium nitride layer protruding from the peripheral surface of the gate electrode so that conductive materials are not easy to remain, and it cannot be continuous to effectively prevent the metal oxide layer on the polycrystalline dream from being turned on. short

442858 V. Description of the invention (8) The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

442858 Simple description of the circle type diagrams. Figures 1 to 4 are schematic diagrams of the conventional method for making MOS transistors on a semiconductor wafer. Figures 5 to 8 show the method of making MOS transistors on a semiconductor wafer according to the present invention. The symbol of the circle 0 indicates the 10 '50 semiconductor crystal 12' 52 silicon substrate 14, 54 m silicon oxide layer 16 '56 polycrystalline silicon layer 18, 38 photoresist layer 20' 69 gate 22> 64 gate oxide layer 24, 64 doped polycrystalline silicon layer 26 '66 silicon oxide layer 30, 70 silicon nitride layer 32' 72 sidewall 36, 76 cobalt metal layer 38 '78 hafnium nitride layer 40, 80 MOS transistor 42' 82 titanium self-aligned silicide 57 '65 Transition layer 60 Quasi-gate structure 28, 34, 68, 74 Doped regions

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Claims (1)

4 428 5 8 6. Scope of patent application 1. A method for fabricating a gate on a semiconductor wafer, the method includes the following steps: forming a pre-gate structure on the surface of the semiconductor wafer, and The quasi-gate structure includes a gate dielectric layer, a polycrystalline silicon layer, and a transition layer in order from bottom to top; forming a sidewall around the quasi-gate structure; removing the transition layer; and a surface of the polycrystalline silicon layer A metal silicide layer is formed on the substrate around the side wall to complete the fabrication of the gate. 2. The method of claim 1 in the patent application method, wherein the method for forming the quasi-gate structure includes: forming an oxide layer on the surface of the semiconductor wafer; forming a polycrystalline silicon layer on the oxide layer; and forming the polycrystalline silicon Forming the transition layer on the layer; performing a yellow light process to define the pattern of the quasi-gate structure; and performing an etching process to remove the transition layer, the polycrystalline silicon layer, and the excess portion of the oxide layer to form the quasi-gate structure . 3. The method according to item 2 of the patent application, wherein the polycrystalline silicon layer is a doped silicon room. 4. The method according to item 2 of the scope of patent application, wherein the transition layer is a tungsten silicide layer, and the polycrystalline dream layer and the transition layer are Page 13 ^ 42 85 ο 6. Scope of patent application The crossing layer can be etched in the same furnace tube. 5. The method of claim i in the scope of patent application, wherein the method of forming the sidewall includes: uniformly forming a silicon nitride layer on the surface of the semiconductor crystal, and covering the quasi-gate structure And etching the silicon nitride layer, so that a portion of the silicon nitride layer remaining around the quasi-gate structure forms the sidewall. 6. The method of claim 1 in which the method of removing the transition layer is a cleaning process. 7. The method of claim 1, wherein the surface of the semiconductor wafer includes a substrate, and the metal dream layer is formed by a self-alignment method, the self-alignment method includes: on the silicon A metal layer is uniformly deposited on the substrate surface and the quasi-gate structure surface; a high temperature process is performed to make the metal layer react with the silicon substrate around the sidewall and the polycrystalline silicon layer to form the metal silicide layer; and remove the surface of the silicon substrate And the metal layer of the unreacted portion of the sidewall sub-surface. 8. The method according to item 1 of the patent application, wherein the top of the side wall is higher than the polycrystalline silicon layer after removing the transition layer to avoid remaining on the polycrystalline silicon layer. Page U 4 42858 VI. Patent application area ~~~ ^ ~ --- The metal layer on the side surface of the side wall conducts the metal on the polycrystalline silicon layer and the metal silicide layer on the substrate. There is a conductive substrate for crossing the layer from below; for removing the metal layer; entering the bottom and removing the metal layer; its polycrystalline silicon metal metal is a method to avoid a semiconductor wafer path, which contains the following steps and causes the method to be short The dream substrate is sequentially covered with the quasi-gate in addition to the transition. The surface of the dream substrate forms a surrounding layer containing a gate structure; the surface and the row are subjected to a high-temperature process to make the phase act on the bottom surface and the polycrystalline dream layer. The top layer of the silicon-based layer removes the debris layer and the transition layer to prevent the residual polycrystalline debris layer from causing a short circuit around the sub-surface of the side wall around the it55 pole. And the quasi-gate dielectric layer, a polycrystalline silicon layer, and a side wall. A metal layer is uniformly deposited on the surface of the quasi-closed pole structure and the metal silicide layer is formed around the side wall; and the unreacted part of the surface of the side wall 'The top of the side wall will remain on the surface of the side wall of the non-reversing metal dream material layer and the dream base 10. If the method of the scope of patent application item 9, The method of forming the quasi-closed structure includes: physical layer residual a silicon structure—over one gold silicon-based gold on the bottom of the application part W2858 -------- --------- 6. Scope of Shen Qi's patents 1 ~ One forms an oxide layer on the surface of the wonderful substrate; forms the polycrystalline silicon layer on the halogenated layer; Forming the transition layer on the polycrystalline silicon layer; performing a yellow light process to define a pattern of the quasi-gate structure; and performing an etching process to remove the transition layer, the polycrystalline silicon layer, and an excess portion of the oxide layer to form the quasi-gate structure. 11. The method according to item 9 of the patent application, wherein the polycrystalline silicon layer is a doped polycrystalline silicon layer "12. The method according to item 9 of the patent application, wherein the transition layer is a tungsten silicide Layers, and the process of etching the polycrystalline hair layer and etching the transition layer can be performed in the same furnace tube.