JP3334692B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a self-aligned silicide film on a gate electrode and a diffusion layer having a high impurity concentration in a semiconductor device by using a salicide technique. The present invention relates to a method for manufacturing a semiconductor device to be formed.

[0002]

2. Description of the Related Art In a silicide technique (self-aligned silicide, Self Align Silicide, salicide) for forming a silicide film in a self-alignment manner on a gate electrode and a diffusion layer of a semiconductor device, a film thickness is formed on the gate electrode and the diffusion layer. It is important to form a silicide film which is uniform and has a low and stable electric resistance. Therefore, the specific resistance of the silicide film is low, and both p-type and n-type silicon (Si)
A salicide technique using cobalt (Co) having an appropriate Schottky barrier height is adopted.

However, with the miniaturization of semiconductor devices, the impurity concentration on the surface of the gate electrode and the diffusion layer has been increased, and the pattern size has also been miniaturized. High resistance by oxidation of Co during silicidation heat treatment, p
Problems such as deterioration of the -n junction leak characteristic and aggregation of the silicide film have occurred, and it has become difficult to form the silicide film on the gate electrode and the diffusion layer in a self-aligned manner.

Accordingly, K. Goto et al, Technical Diges
t of IEEE International Electron Device Meeting 199
5 (IEDM95), p449 (1995) discloses a method of depositing a metal film for protecting the surface on Co and selectively forming a silicide film in a self-aligned manner on the gate electrode and the diffusion layer. (Conventional example 1). FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device described in Conventional Example 1 in the order of steps.

[0005] As shown in FIG.
01, a MOSFET (Metal Oxide Se
A conductor field effect (metal-oxide-semiconductor field-effect transistor) 110 is formed. MOSFET
At 110, first, an element isolation region 102 made of a silicon oxide film having a trench filling structure is formed on the surface of a silicon substrate 101. Next, a gate silicon film 104 is formed on the semiconductor substrate 101 in the element region partitioned by the element isolation region 102 with a gate oxide film 103 interposed therebetween. Then, a gate electrode is patterned by a lithography technique and an etching technique. After that, a silicon oxide film is deposited,
A sidewall 105 is formed by anisotropic etching until the gate electrode is exposed, and impurity ions are implanted using the sidewall 106 and the gate silicon film 104 as a mask to form a diffusion layer 106 as a source / drain region. Thus, MOSFET 110 is formed using known materials and methods. Then, a disilicide is formed on the gate silicon film 104 and the diffusion layer 106 of the MOSFET 110.

[0006] First, as shown in FIG.
A first Co film 107a is formed on the ET110 by a sputtering method so as to have a thickness of 10 nm. Subsequently, a titanium nitride (TiN) film 109 is formed on the first Co film 107a.
Is formed by sputtering to have a thickness of 30 nm. This TiN film 109 is formed for the purpose of preventing oxidation during the heat treatment for silicidation of Co.

Next, as shown in FIG. 5 (c), a rapid thermal anneal (RTA)
By subjecting the silicon substrate 101 to a first heat treatment at a heat treatment temperature of 550 ° C. and a treatment time of 30 seconds in a nitrogen atmosphere, the surface portions of the gate silicon film 104 and the diffusion layer 106 react with the first Co film 107a, Co and Si
Forming a self-aligned manner on Co _x Si _y film 108a (x ≧ y) of the gate silicon layer 104 and on the diffusion layer 106 is a reaction layer with.

Subsequently, as shown in FIG. 5D, TiN
After the unreacted first Co film remaining on the film 109 and the MOSFET 110 is sequentially removed by a wet etching method, a heat treatment temperature of 750 to 900 ° C. and a treatment time of 30 seconds in a nitrogen atmosphere are performed by a ramp rapid heating method. 2 is performed to form the gate silicon film 104 and the diffusion layer 1.
The Co _x Si _y film 108a on the surface of the No. 06 surface is thermally and compositionally stable, and has a low resistance cobalt disilicide (CoSi
₂ ) A phase transition is made to the film 108b. As described above, the TiN film 109 is used as the first Co film 1 as the Co oxidation prevention film during the heat treatment.
After formation on the layer 07a, a silicide film is formed to prevent oxidation of the Co film.

Further, a technique has been disclosed in which a Co film or a Ti film is deposited on a semiconductor device, and a heat treatment temperature and an atmosphere are regulated to form a low-resistance high-melting-point metal silicide on the semiconductor device (Japanese Patent Laid-Open Publication No. HEI 9-26139). JP-A-8-264482, Patent 2
785810, etc .: Conventional example 2). JP-A-8-264
According to the technology described in Japanese Patent Publication No.
After forming an O film and a TiN film thereon, a cobalt silicide film is selectively formed by a first heat treatment, and then a second heat treatment for lowering the resistance of the CoSi film is performed. A third heat treatment at a temperature higher than that of the heat treatment is performed. The reverse heat leakage characteristic at the pn junction immediately below the refractory metal silicide film varies only by the second heat treatment, but the third heat treatment improves the reverse leakage characteristic.

On the other hand, K. Inoue et al, Technical Digital
of IEEE International Electron Device Meeting 1995
(IEDM95), pp445 (1995) discloses a technique for preventing the oxidation of Co during heat treatment and reducing the sheet resistance by increasing the reactivity between Co and Si. (Conventional example 3). FIG. 6 is a sectional view showing a method of manufacturing a semiconductor device described in Conventional Example 3 in the order of steps.

First, as shown in FIG. 6A, in a predetermined region on a silicon substrate 101, an element isolation region 102, a gate oxide film 103, a gate silicon film 104, a side wall are formed by a known material and method. 105 and diffusion layer 1
The MOS transistor 120 composed of the MOS transistor 06 is formed.

Then, according to the process sequence shown in FIG. 6B, as shown in FIG. 6C, a first Co film 107a having a thickness of 10 nm is formed by sputtering while heating the silicon substrate. While maintaining a vacuum state, the silicon substrate is subjected to a heat treatment to form a Co _x Si _y film 108a (x ≧ y) by a reaction between Co and silicon. That is, the MOS transistor 120 until the elapsed time t1
The first Co film 107a is deposited by elevating the temperature of the substrate and performing sputtering for the elapsed time t1 to t2, and thereafter, the substrate is heated until the elapsed time t3.

Next, as shown in FIG. 6D, the silicon substrate 1 is heated in a nitrogen atmosphere by a lamp rapid heating method.
01 is subjected to the first heat treatment, so that the surface portions of the gate silicon film 104 and the diffusion layer 106 and the first Co film 107 are formed.
Further promote the reaction with a. Subsequently, after the unreacted first Co film remaining on the element isolation region and the sidewalls is sequentially removed by wet etching, a second heat treatment is performed in a nitrogen atmosphere by a lamp rapid heating method to form a gate silicon. The surfaces of the film 104 and the diffusion layer 106 undergo a phase transition to the CoSi ₂ film 108b.

[0014]

However, according to the technique of the prior art 1, since a TiN film having a high internal stress and a small thermal expansion coefficient is formed on the upper layer of the Co film, Co and Si are formed.
However, there is a problem that the stress caused by the change in volume when reacting with the metal cannot be relaxed and an excessive reaction (spike) occurs locally to deteriorate the junction leak characteristic.

[0015] Further, in the techniques of Conventional Examples 2 and 3,
If the miniaturization of the device further progresses and it becomes necessary to further increase the impurity concentration on the surface of the gate and the diffusion layer in order to prevent depletion, the reactivity between Co and Si further decreases. The oxidation of Co at the time cannot be ignored. Therefore, there is a problem in application to a fine semiconductor device requiring a high surface impurity concentration. That is,
As described above, these methods cannot fundamentally solve problems such as high resistance due to oxidation of Co, deterioration of pn junction leak characteristics, and aggregation of a silicide film.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to provide a silicide film having a low resistance and stable electric characteristics even on a fine gate electrode and a diffusion layer having a high impurity concentration. An object of the present invention is to provide a method for manufacturing a semiconductor device which can be formed in a self-aligned manner without causing deterioration.

[0017]

[0018]

[0019]

According to a method of manufacturing a semiconductor device according to the present invention, a gate insulating film, a gate electrode, a sidewall on a side surface of the gate electrode and source / drain regions are formed in a predetermined region of an element region on a silicon substrate. Forming a transistor including a diffusion layer, and selectively forming a silicide film on the diffusion layer and the gate electrode, wherein the silicide film formation step includes heating the silicon substrate. After intermittently depositing the first metal film, titanium nitride (TiN) or tan is deposited on the first metal film.
Forming a second metal film made of gustene (W) ;
A heat treatment is performed at a temperature higher than the deposition temperature of the metal film to form a silicide film on the diffusion layer and the gate electrode.

In the present invention, the first metal film for forming the silicide film on the diffusion layer and the gate electrode is formed intermittently in a plurality of times. (1) An intermediate reaction layer is selectively formed between the metal film, the diffusion layer, and the gate electrode. Therefore, the first
After the second metal film is formed on the upper surface of the metal film as an antioxidant film, even if the silicon substrate is heated, the intermediate reaction layer has already been formed under the second metal film. There is almost no change in volume, and no stress is generated inside the second metal film.
Therefore, the concentration of the internal stress does not cause a non-uniform reaction between the first metal film and the diffusion layer or the gate electrode, thereby deteriorating the junction leakage characteristic. The oxidation of the metal film and the intermediate reaction layer can be prevented, and the reactivity of the first metal film with the diffusion layer and the gate electrode can be further improved.

The heat treatment includes a step of performing a first heat treatment at a temperature higher than a deposition temperature of the first metal film, and a step of removing the unreacted first metal film in the first heat treatment. And performing a second heat treatment at a temperature higher than the temperature of the first heat treatment, whereby a disilicide film may be formed on the diffusion layer and the gate electrode.

Further, the first metal film is made of titanium (T
i), one kind of metal selected from the group consisting of cobalt (Co) and nickel (Ni).

Further, the first metal film can be formed by any one of a sputtering method and a chemical vapor deposition method.

[0024]

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. 1 and 2 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

As shown in FIG. 1A, a silicon substrate 1
The element isolation region 2 is formed on the surface of the substrate, and a plurality of element regions are formed. In this element region, a diffusion layer 6 serving as a source / drain region is selectively formed.
A gate oxide film 3 and a gate silicon film 4 serving as a gate electrode thereabove are formed on the region surrounded by. The side wall 5 is formed on the side surface of the gate oxide film 3 and the gate silicon film 4 to form a MOS. The transistor 10 is configured.

As a method for manufacturing such a MOS transistor 10, first, an element isolation region 2 made of a silicon oxide film having a trench filling structure is formed on the surface of a silicon substrate 1 by a thickness of, for example, 300 to 400 nm and a width of, for example, 200.
To about 500 nm. Note that the element isolation region 2 is a LOCOS (Local Oxidation of Silico).
n; selective oxidation). Next, the semiconductor substrate 1 in the element region partitioned by the element isolation region 2
A silicon film having a thickness of, for example, 100 to 250 nm is formed thereon via a gate oxide film 3 having a thickness of, for example, about 3 nm. Then, a gate silicon film 4 as a gate electrode having a width of, for example, about 100 to 250 nm and a film thickness of, for example, about 100 to 150 nm is formed by lithography and etching. Thereafter, a silicon oxide film having a thickness of, for example, about 80 to 100 nm is deposited,
The sidewall 5 is formed by anisotropic etching until the gate silicon film 4 is exposed. Then, impurity ions are implanted by using the gate silicon film 4 and the sidewalls 5 as a mask to form a diffusion layer 6 serving as a source / drain region. As described above, the MOS transistor 10 is formed using known materials and methods.

Next, in order to selectively form a silicide film on the gate silicon film 4 and the diffusion layer 6 of the MOS transistor 10, a Co film is intermittently deposited on the silicon substrate 1. Note that Ti or Ni may be used as a metal for forming the silicide film. In order to intermittently deposit a Co film, a voltage is intermittently applied to the sputtering apparatus according to the process sequence shown in FIG.
In FIG. 1B, the horizontal axis represents elapsed time, and the vertical axis represents sputter power. First, the substrate is heated and heated by an elapsed time t0 in the sputtering apparatus, for example, 200 to 40.
On the silicon substrate 1 held at a temperature of 0 ° C., a first Co having a thickness of, for example, 5 nm is formed during the elapsed time t0 to t1.
After the film 7a is deposited and the sputtering is stopped for the elapsed time t1 to t2, the second Co film 7b having a thickness of, for example, 5 nm is deposited for the elapsed time t2 to t3, and the sputtering process is terminated. The time for stopping the sputtering during the elapsed time t1 to t2 is, for example, about 5 to 60 seconds.

At the elapsed time t1 when the deposition of the first Co film 7a is completed, Co of the deposited first Co film and Si of the gate silicon film 4 and the diffusion layer 6 hardly react with each other. At time t2, the reaction between Co and Si proceeds, and as shown in FIG. 1C, Co and Si are selectively deposited on the gate silicon film 4 and the diffusion layer 6.
Then, a Co _x Si _y film (x ≧ y) 8a, which is an intermediate reaction layer between them, is formed.

Then, at the elapsed time t3 when the deposition of the second Co film is completed, as shown in FIG. 2A, the second Co film 7b is deposited on the Co _x Si _y film (x ≧ y) 8a. .

As described above, by intermittently depositing a Co film and forming a thin Co film on the semiconductor substrate 1 in a plurality of times, the reaction between Co and Si is reduced as in the prior art. Co is promoted rather than forming a Co film at one time, and has high surface impurity concentration and high oxidation resistance even in a fine pattern.
A -Si intermediate reaction layer can be formed.

This is because in the initial stage of the reaction of Co—Si, C
Although o becomes a diffusion species, the thinner the film thickness of the Co film to be deposited, the higher the vacancy concentration and the density of lattice defects in the Co film. This is because it easily occurs.

Thereafter, as shown in FIG. 2B, the substrate temperature is higher than the substrate temperature when the first Co film 7a and the second Co film 7b are formed on the silicon substrate 1 by sputtering in a nitrogen atmosphere by a rapid lamp heating method. By performing the first heat treatment at the temperature, the reaction between the surface of the gate silicon film 4 and the diffusion layer 6 and Co is further promoted. Subsequently, the unreacted second Co film 7b and first Co film 7a in the first heat treatment are sequentially removed by a wet etching method. Thereafter, a second heat treatment at a higher temperature than the first heat treatment is performed in a nitrogen atmosphere by a lamp rapid heating method,
C formed on the gate silicon film 4 and the diffusion layer 6
The o _x Si _y film is phase transition CoSi ₂ film 8b.

In the present embodiment, when the reaction between Co-Si hardly occurs in the above-mentioned manufacturing method and a low sheet resistance is hardly obtained by oxidation during heat treatment, the second C
After providing an oxidation preventing film made of TiN or W on the o film 7b, a first heat treatment can be performed.

In the technique of Conventional Example 1, if a TiN film is formed on Co, the stress caused by the volume change during the Co-Si reaction cannot be relaxed, and there is a problem that a local excessive reaction occurs. In the embodiment, since the Co—Si intermediate reaction layer is formed before the first heat treatment,
Even if, for example, a TiN film is formed thereon and heat-treated,
Since the Co film below the iN film has already formed an intermediate reaction layer with Si, its volume change is small even when the reaction between Co and Si proceeds. Therefore, it is hardly affected by the stress, and local overreaction does not occur.

As described above, in the first embodiment, by intermittently applying the voltage of the sputtering apparatus, the Co film for selectively forming the silicide film on the transistor 10 is deposited a plurality of times. By reducing the film thickness deposited at a time to increase the vacancy concentration and the density of lattice defects in the Co film, the reaction between Co and Si is likely to occur, and Co— has high oxidation resistance. The Si intermediate reaction layer can be selectively formed on the diffusion layer and the gate electrode. Therefore, the silicide reaction is unlikely to occur, and even on a fine gate electrode and a diffusion layer having a high surface impurity concentration,
Since oxidation of Co during silicidation heat treatment can be prevented, and a low-resistance silicide film in which Co and Si have uniformly reacted can be formed in a self-aligned manner, a semiconductor device having excellent electric characteristics can be manufactured. be able to.

If a TiN film or the like for preventing oxidation is formed on the second Co film 7b, the oxidation of the Co film is more difficult to occur, so that even when the silicide reaction is harder to occur, the gate is selectively formed. A low-resistance silicide film can be stably formed on the silicon film 4 and the diffusion layer 6.

Next, a second embodiment of the present invention will be described. In this embodiment, as in the first embodiment, Co is used for the metal film to be silicided, and the surface impurity concentration is higher than in the first embodiment, and a low-resistance silicide film is formed on a fine pattern. That is the way you can. Also in this embodiment, Ti is used as a metal for forming silicide.
Alternatively, N may be used. 3 and 4 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present embodiment in the order of steps. In the second embodiment shown in FIGS. 3 and 4, the same components as those in the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as shown in FIG. 3A, a MOS transistor 10 similar to that of the first embodiment is formed on a silicon substrate 1.
To form That is, a plurality of device isolation regions 2, a gate oxide film 3, a gate silicon film 4, a diffusion layer 6 serving as a source / drain region, and a gate oxide film and a gate silicon film are formed in a predetermined region of the silicon substrate 1 by a known material and method. A MOS transistor 10 including the side wall 5 on the side surface of the film 4 is formed.

Thereafter, in order to selectively form a disilicide film on the gate silicon film 4 and the diffusion layer 6 of the MOS transistor 10, a Co film is intermittently deposited on the silicon substrate 1. In order to intermittently deposit a Co film, a voltage is intermittently applied to the sputtering apparatus according to the process sequence shown in FIG. In FIG. 3B, the horizontal axis represents the elapsed time, and the vertical axis represents the sputter power. Thus, a Co film can be intermittently deposited on the silicon substrate 1 heated and maintained at, for example, 200 to 500 ° C. First, the substrate of the MOS transistor 10 is heated and heated by the elapsed time t0 in the sputtering apparatus, a first Co film having a thickness of, for example, 4 nm is deposited during the elapsed time t0 to t1, and the first Co film is deposited during the elapsed time t1 to t2. After the sputtering is stopped, a second Co film 7b having a thickness of, for example, 3 nm is deposited between the elapsed times t2 and t3, and the elapsed time t3
After the sputtering is stopped again during the period from t4 to t4, the elapsed time t
The third Co film 7c having a thickness of, for example, 3 nm between 4 and t5.
Then, the temperature of the silicon substrate is maintained at, for example, a temperature of 200 to 500 while the vacuum state is maintained for an elapsed time t5 to t6. The elapsed times t1 to t2, the elapsed times t3 to t4, and C
The elapsed time t5 to t6 for heating the substrate after the film formation is
For example, about 5 to 30 seconds.

In the elapsed time t1 after the formation of the first Co film, Co and Si hardly reacted with each other. However, in the elapsed time t2 after the first stop of the sputtering, the reaction between Co and Si progressed. As shown in (c), the gate silicon film 4
And Co _x Si _y, which is an intermediate reaction layer between them, on the diffusion layer 6.
The film (x ≧ y) 8a is selectively formed.

Then, the elapsed time t3 after the formation of the second Co film is
Then, as shown in FIG. 4A, the Co _x Si _y film (x ≧
y) The structure is such that the second Co film 7b exists on 8a.

Further, as shown in FIG. 4 (b), at the elapsed time t4 after the suspension of the second sputtering, the Co-Si reaction proceeds, and the Co _x Si _y on the gate silicon film 4 and the diffusion layer 6 is formed.
The thickness of the film (x ≧ y) 8a increases, and the Co _x Si _y film (x
≧ y) 8d. Then, at the elapsed time t5 after the formation of the third Co film, the Co _x Si _y film (x ≧ y) 8 having the increased thickness is used.
The structure has the third Co film 7c on d. Further, at the elapsed time t6 at which the sputtering process ends, the Co-Si reaction further progresses due to heating during the period from t5 to t6, and the film thickness of the Co _x Si _y film (x ≧ y) 8d further increases, and The ratio of Si in the inside also increases.

Thereafter, in the same manner as in the first embodiment,
The first Co film 7a, the second Co film 7b, and the third C film 3 are formed on the silicon substrate 1 in a nitrogen atmosphere by a lamp rapid heating method.
By performing the first heat treatment at a temperature higher than the substrate temperature when the o film 7c is formed by sputtering, the reaction between the surfaces of the gate silicon film 4 and the diffusion layer 6 and Co is further promoted. Subsequently, unreacted 3C in the first heat treatment
The o film 7c, the second Co film 7b, and the first Co film 7a are sequentially removed by a wet etching method. Then, FIG.
As shown in (c), a second heat treatment is performed in a nitrogen atmosphere at a temperature higher than the first heat treatment by a lamp rapid heating method, and Co _x formed on the surfaces of the gate silicon film 4 and the diffusion layer 6 is formed. The phase transition of the intermediate reaction layer of the Si _y film is performed to the CoSi ₂ film 8b. As the silicide of Co and Si, at formation temperatures of 350 to 500 ° C., the crystal structure of the orthorhombic system is PbCl ₂ Co ₂ Si, making temperature 4
At 25 to 500 ° C, the cubic crystal structure is B20 C
There is a silicide phase such as CoSi ₂ having oSi and a formation temperature of 550 ° C. and a cubic crystal structure of Cl, and the second heat treatment forms a Co _x Si _y film of an intermediate reaction layer made of Co ₂ Si, CoSi, and the like. Phase transition to CoSi ₂ .

As described above, by intermittently applying a voltage to the sputtering apparatus, the Co film is formed in a plurality of times, and the thickness of the Co film deposited at one time can be reduced. The reaction between Co and Si is promoted as compared with the conventional method of depositing a 10 nm Co film all at once,
A Co-Si intermediate reaction layer having high oxidation resistance even in a fine pattern having a high surface impurity concentration can be selectively formed on the diffusion layer and the gate electrode. This is because, as described above, Co becomes a diffusion species in the initial stage of the reaction of Co-Si. However, when the Co film is made thinner to increase the vacancy concentration and the density of lattice defects in the Co film, these become Co-Si. This is because a reaction between Co and Si is likely to occur as a diffusion path of the metal. The vacancy concentration and lattice defect concentration in the Co film become higher as the deposited Co film becomes thinner.
After the film formation, the gate silicon film 4 is subjected to a heat treatment from t5 to t6 while maintaining the vacuum state.
The reaction between Co and the surface of the diffusion layer 6 is further promoted as compared with the first embodiment.

Therefore, in order to form the silicide film in a self-aligned manner as in the present embodiment, a voltage is intermittently applied to the sputtering apparatus to deposit a thin film in a plurality of times to form a film having a predetermined thickness. By a method of forming a Co film and subsequently heating the inside of the apparatus while maintaining a vacuum state, even in a fine pattern having a higher impurity concentration than in the first embodiment, the Co on the gate electrode and the diffusion layer can be removed. Since Si and Si can react very uniformly and a low-resistance silicide film can be selectively formed, a semiconductor device having excellent electric characteristics can be manufactured.

Also in this embodiment, a TiN film or a W film may be formed on the Co film as a film for preventing oxidation. For example, when a TiN film is formed as the oxidation preventing film, the Co-Si film has already reacted with the gate silicon film 4 and the diffusion layer 6 to form a Co _x Si _y film as an intermediate reaction layer. The stress caused by the volume change accompanying the reaction can be reduced. Accordingly, even when a TiN film or the like having a higher internal stress and a smaller thermal expansion coefficient than the Co film is formed on the Co film and heat treatment is performed, the junction leak characteristics are maintained without locally causing excessive reaction. It is possible to form a silicide film with low resistance and high uniformity as it is.

It should be noted that the present invention is not limited to the above embodiments, but can be variously modified within the technical scope based on the claims.

[0049]

As described above in detail, according to the method of manufacturing a semiconductor device according to the present invention, a metal film to be silicided is intermittently formed on a silicon substrate held at a high temperature in a plurality of times. Therefore, the thickness of the metal film formed at one time can be reduced. Therefore, the vacancy concentration and the concentration of interstitial defects in the formed metal film are increased, and these become diffusion paths between Si of the gate electrode and the diffusion layer and the metal film. Even in a semiconductor device having a silicide reaction that is unlikely to occur, the reaction between the two is likely to occur, and when the metal film is intermittently formed, the metal film and the Si are interposed between the gate electrode and the diffusion layer and the metal film. An intermediate reaction layer having high oxidation resistance is formed. If the intermediate reaction layer is further reacted by heat treatment, the reaction between the metal film and Si is promoted while suppressing the oxidation of the metal film during the silicidation heat treatment, so that the metal film and Si react uniformly. A resistance silicide film can be selectively formed on the diffusion layer and the gate electrode.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIGS. 2A and 2B are views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps, and FIGS. It is sectional drawing which shows the process following the shown process in the order of the process.

FIGS. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIGS. 4A to 4C are views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps, and FIGS. It is sectional drawing which shows the process following the shown process in the order of the process.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Conventional Example 1 in the order of steps.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device of Conventional Example 3 in the order of steps.

[Explanation of symbols]

1, 101; silicon substrate 2, 102; element isolation region 3, 103; gate oxide film 4, 104; gate silicon film 5, 105; sidewall 6, 106; diffusion layer 7a, 107a; first Co film 7b, 107b; Second Co film 7c; Third Co film 8a, 108a, 108d; CoxSiy (x ≧ y) film 8b, 108b; CoSi ₂ film 9, 109; TiN film

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/28 301 H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] A step of forming a transistor including a gate insulating film, a gate electrode, a sidewall on a side surface of the gate electrode, and a diffusion layer serving as a source / drain region in a predetermined region of an element region on a silicon substrate; And selectively forming a silicide film on the gate electrode, wherein the silicide film forming step comprises: intermittently depositing a first metal film while heating the silicon substrate; Titanium nitride (TiN) or tan on metal film
Forming a second metal film made of gustene (W) ;
A method of manufacturing a semiconductor device, comprising forming a silicide film on the diffusion layer and the gate electrode by performing a heat treatment at a temperature higher than a deposition temperature of a metal film. 2. The heat treatment includes a step of performing a first heat treatment at a temperature higher than a deposition temperature of the first metal film, and a step of removing the unreacted first metal film in the first heat treatment. Performing a second heat treatment at a temperature higher than the temperature of the first heat treatment, and forming a disilicide film on the diffusion layer and the gate electrode.
2. The method for manufacturing a semiconductor device according to item 1 . Wherein said first metal film, a titanium (Ti), claim 1, wherein the cobalt (Co) and to consist of one kind of metal selected from the group consisting of nickel (Ni)
Or a method for manufacturing a semiconductor device according to item 2 . Wherein said first metal film, a method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that it is formed by any method sputtering or chemical vapor deposition.