CN110709966B - 使用保护盖层蚀刻含铂薄膜 - Google Patents
使用保护盖层蚀刻含铂薄膜 Download PDFInfo
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- CN110709966B CN110709966B CN201880015666.0A CN201880015666A CN110709966B CN 110709966 B CN110709966 B CN 110709966B CN 201880015666 A CN201880015666 A CN 201880015666A CN 110709966 B CN110709966 B CN 110709966B
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- C01G55/004—Oxides; Hydroxides
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| PCT/US2018/014522 WO2018136795A2 (en) | 2017-01-19 | 2018-01-19 | Etching platinum-containing thin film using protective cap layer |
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| US10504733B2 (en) * | 2017-01-19 | 2019-12-10 | Texas Instruments Incorporated | Etching platinum-containing thin film using protective cap layer |
| WO2019066977A1 (en) | 2017-09-29 | 2019-04-04 | Intel Corporation | FIRST-LEVEL THIN-LEVEL INTERCONNECTIONS DEFINED BY AUTOCATALYTIC METAL FOR LITHOGRAPHIC INTERCONNECTION HOLES |
| US11011381B2 (en) | 2018-07-27 | 2021-05-18 | Texas Instruments Incorporated | Patterning platinum by alloying and etching platinum alloy |
| JP7036001B2 (ja) * | 2018-12-28 | 2022-03-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US11990369B2 (en) | 2021-08-20 | 2024-05-21 | Applied Materials, Inc. | Selective patterning with molecular layer deposition |
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2017
- 2017-09-25 US US15/714,169 patent/US10504733B2/en active Active
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2018
- 2018-01-19 WO PCT/US2018/014522 patent/WO2018136795A2/en not_active Ceased
- 2018-01-19 CN CN202311109377.6A patent/CN117153816A/zh active Pending
- 2018-01-19 JP JP2019539226A patent/JP7007745B2/ja active Active
- 2018-01-19 EP EP18741450.3A patent/EP3571709B1/en active Active
- 2018-01-19 CN CN201880015666.0A patent/CN110709966B/zh active Active
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2019
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2021
- 2021-06-15 US US17/347,715 patent/US11929423B2/en active Active
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2024
- 2024-01-31 US US18/428,198 patent/US20240222470A1/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4804438A (en) * | 1988-02-08 | 1989-02-14 | Eastman Kodak Company | Method of providing a pattern of conductive platinum silicide |
| JPH1187401A (ja) * | 1997-09-05 | 1999-03-30 | Haruki Yokono | 半導体装置 |
| US6265779B1 (en) * | 1998-08-11 | 2001-07-24 | International Business Machines Corporation | Method and material for integration of fuorine-containing low-k dielectrics |
| JP2002124487A (ja) * | 2000-08-10 | 2002-04-26 | Chartered Semiconductor Manufacturing Inc | シリサイドの形成方法 |
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| Publication number | Publication date |
|---|---|
| US10504733B2 (en) | 2019-12-10 |
| JP7007745B2 (ja) | 2022-01-25 |
| JP7244030B2 (ja) | 2023-03-22 |
| US20180204734A1 (en) | 2018-07-19 |
| WO2018136795A3 (en) | 2018-09-07 |
| US11929423B2 (en) | 2024-03-12 |
| US20210313179A1 (en) | 2021-10-07 |
| WO2018136795A2 (en) | 2018-07-26 |
| US20200083050A1 (en) | 2020-03-12 |
| US11069530B2 (en) | 2021-07-20 |
| EP3571709A4 (en) | 2020-02-12 |
| WO2018136795A8 (en) | 2019-12-12 |
| US20240222470A1 (en) | 2024-07-04 |
| CN117153816A (zh) | 2023-12-01 |
| JP2022043249A (ja) | 2022-03-15 |
| EP3571709A2 (en) | 2019-11-27 |
| EP3571709B1 (en) | 2023-11-22 |
| JP2020507207A (ja) | 2020-03-05 |
| CN110709966A (zh) | 2020-01-17 |
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